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Update autogenerated files.

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0.96
Török Edvin 15 years ago
parent 24cb93723b
commit 5f42f86347
24 changed files with 78194 additions and 114498 deletions
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  1. 5591
      libclamav/c++/ARMGenAsmWriter.inc
  2. 686
      libclamav/c++/ARMGenCodeEmitter.inc
  3. 64365
      libclamav/c++/ARMGenDAGISel.inc
  4. 3767
      libclamav/c++/ARMGenInstrInfo.inc
  5. 3448
      libclamav/c++/ARMGenInstrNames.inc
  6. 12
      libclamav/c++/Makefile.am
  7. 161
      libclamav/c++/Makefile.in
  8. 170
      libclamav/c++/PPCGenAsmWriter.inc
  9. 14
      libclamav/c++/PPCGenCallingConv.inc
  10. 10
      libclamav/c++/PPCGenCodeEmitter.inc
  11. 14140
      libclamav/c++/PPCGenDAGISel.inc
  12. 746
      libclamav/c++/PPCGenInstrInfo.inc
  13. 748
      libclamav/c++/PPCGenInstrNames.inc
  14. 12
      libclamav/c++/PPCGenRegisterInfo.inc
  15. 24
      libclamav/c++/X86GenAsmMatcher.inc
  16. 349
      libclamav/c++/X86GenAsmWriter.inc
  17. 373
      libclamav/c++/X86GenAsmWriter1.inc
  18. 92748
      libclamav/c++/X86GenDAGISel.inc
  19. 20
      libclamav/c++/X86GenFastISel.inc
  20. 2432
      libclamav/c++/X86GenInstrInfo.inc
  21. 2352
      libclamav/c++/X86GenInstrNames.inc
  22. 512
      libclamav/c++/X86GenRegisterInfo.inc
  23. 0
      libclamav/c++/llvm/docs/doxygen.cfg.in
  24. 12
      libclamav/c++/strip-llvm.sh

5591
libclamav/c++/ARMGenAsmWriter.inc
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686
libclamav/c++/ARMGenCodeEmitter.inc
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64365
libclamav/c++/ARMGenDAGISel.inc
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3767
libclamav/c++/ARMGenInstrInfo.inc
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3448
libclamav/c++/ARMGenInstrNames.inc
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12
libclamav/c++/Makefile.am
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@ -169,6 +169,7 @@ tblgen_SOURCES=\
llvm/utils/TableGen/DAGISelMatcher.cpp\
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp\
llvm/utils/TableGen/DAGISelMatcherGen.cpp\
llvm/utils/TableGen/DAGISelMatcherOpt.cpp\
llvm/utils/TableGen/DisassemblerEmitter.cpp\
llvm/utils/TableGen/EDEmitter.cpp\
llvm/utils/TableGen/FastISelEmitter.cpp\
@ -251,7 +252,7 @@ tblgen_SOURCES=\
TBLGEN=$(top_builddir)/tblgen
TBLGEN_V=$(AM_V_GEN)$(TBLGEN)
TBLGEN_FLAGS=-I$(top_srcdir)/llvm/include -I$(top_srcdir)/llvm/lib/Target
TBLGEN_FLAGS=-I$(top_srcdir)/llvm/include -I$(top_srcdir)/llvm/lib/Target -omit-comments
llvm/include/llvm/Intrinsics.gen: llvm/include/llvm/Intrinsics.td $(TBLGEN)
$(TBLGEN_V) $(TBLGEN_FLAGS) -gen-intrinsic -o $@ $<
@ -365,11 +366,12 @@ endif
if BUILD_X86
libllvmx86codegen_la_CPPFLAGS=$(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/X86
libllvmx86codegen_la_SOURCES=\
llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/MC/MCAsmInfoCOFF.cpp\
llvm/lib/MC/MCCodeEmitter.cpp\
llvm/lib/MC/TargetAsmBackend.cpp\
llvm/lib/Target/TargetELFWriterInfo.cpp\
llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp\
llvm/lib/Target/X86/X86AsmBackend.cpp\
llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp\
llvm/lib/Target/X86/X86CodeEmitter.cpp\
llvm/lib/Target/X86/X86ELFWriterInfo.cpp\
@ -474,7 +476,6 @@ libllvmjit_la_SOURCES=\
llvm/lib/MC/MCExpr.cpp\
llvm/lib/MC/MCSection.cpp\
llvm/lib/MC/MCSectionELF.cpp\
llvm/lib/MC/MCSectionMachO.cpp\
llvm/lib/MC/MCSymbol.cpp\
llvm/lib/Support/APFloat.cpp\
llvm/lib/Support/APInt.cpp\
@ -578,9 +579,11 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/LiveStackAnalysis.cpp\
llvm/lib/CodeGen/LiveVariables.cpp\
llvm/lib/CodeGen/LowerSubregs.cpp\
llvm/lib/CodeGen/MachineCSE.cpp\
llvm/lib/CodeGen/MachineDominators.cpp\
llvm/lib/CodeGen/MachineLICM.cpp\
llvm/lib/CodeGen/MachineLoopInfo.cpp\
llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/CodeGen/MachinePassRegistry.cpp\
llvm/lib/CodeGen/MachineSSAUpdater.cpp\
llvm/lib/CodeGen/MachineSink.cpp\
@ -630,6 +633,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/StackSlotColoring.cpp\
llvm/lib/CodeGen/StrongPHIElimination.cpp\
llvm/lib/CodeGen/TailDuplication.cpp\
llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp\
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp\
llvm/lib/CodeGen/UnreachableBlockElim.cpp\
llvm/lib/CodeGen/VirtRegMap.cpp\
@ -640,6 +644,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/MC/MCInst.cpp\
llvm/lib/MC/MCMachOStreamer.cpp\
llvm/lib/MC/MCNullStreamer.cpp\
llvm/lib/MC/MCSectionMachO.cpp\
llvm/lib/MC/MCStreamer.cpp\
llvm/lib/Target/TargetFrameInfo.cpp\
llvm/lib/Target/TargetSubtarget.cpp\
@ -806,7 +811,6 @@ libllvmfullcodegen_la_SOURCES=\
llvm/lib/CodeGen/GCMetadataPrinter.cpp\
llvm/lib/CodeGen/IfConversion.cpp\
llvm/lib/CodeGen/IntrinsicLowering.cpp\
llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/CodeGen/OcamlGC.cpp\
llvm/lib/CodeGen/RegAllocLocal.cpp\
llvm/lib/CodeGen/RegAllocPBQP.cpp\

161
libclamav/c++/Makefile.in
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@ -231,8 +231,9 @@ am_libllvmcodegen_la_OBJECTS = AliasSetTracker.lo ConstantFolding.lo \
DwarfEHPrepare.lo ExactHazardRecognizer.lo GCMetadata.lo \
GCStrategy.lo LLVMTargetMachine.lo LatencyPriorityQueue.lo \
LiveInterval.lo LiveIntervalAnalysis.lo LiveStackAnalysis.lo \
LiveVariables.lo LowerSubregs.lo MachineDominators.lo \
MachineLICM.lo MachineLoopInfo.lo MachinePassRegistry.lo \
LiveVariables.lo LowerSubregs.lo MachineCSE.lo \
MachineDominators.lo MachineLICM.lo MachineLoopInfo.lo \
MachineModuleInfoImpls.lo MachinePassRegistry.lo \
MachineSSAUpdater.lo MachineSink.lo MachineVerifier.lo \
OptimizeExts.lo OptimizePHIs.lo PHIElimination.lo Passes.lo \
PostRASchedulerList.lo PreAllocSplitting.lo \
@ -251,22 +252,23 @@ am_libllvmcodegen_la_OBJECTS = AliasSetTracker.lo ConstantFolding.lo \
SimpleRegisterCoalescing.lo SjLjEHPrepare.lo SlotIndexes.lo \
Spiller.lo StackProtector.lo StackSlotColoring.lo \
StrongPHIElimination.lo TailDuplication.lo \
TwoAddressInstructionPass.lo UnreachableBlockElim.lo \
VirtRegMap.lo VirtRegRewriter.lo MCAsmInfoDarwin.lo \
MCAsmStreamer.lo MCAssembler.lo MCInst.lo MCMachOStreamer.lo \
MCNullStreamer.lo MCStreamer.lo TargetFrameInfo.lo \
TargetSubtarget.lo CodeGenPrepare.lo GEPSplitter.lo GVN.lo \
LoopStrengthReduce.lo AddrModeMatcher.lo BasicBlockUtils.lo \
BreakCriticalEdges.lo DemoteRegToStack.lo LCSSA.lo Local.lo \
LoopSimplify.lo LowerInvoke.lo LowerSwitch.lo Mem2Reg.lo \
TargetLoweringObjectFileImpl.lo TwoAddressInstructionPass.lo \
UnreachableBlockElim.lo VirtRegMap.lo VirtRegRewriter.lo \
MCAsmInfoDarwin.lo MCAsmStreamer.lo MCAssembler.lo MCInst.lo \
MCMachOStreamer.lo MCNullStreamer.lo MCSectionMachO.lo \
MCStreamer.lo TargetFrameInfo.lo TargetSubtarget.lo \
CodeGenPrepare.lo GEPSplitter.lo GVN.lo LoopStrengthReduce.lo \
AddrModeMatcher.lo BasicBlockUtils.lo BreakCriticalEdges.lo \
DemoteRegToStack.lo LCSSA.lo Local.lo LoopSimplify.lo \
LowerInvoke.lo LowerSwitch.lo Mem2Reg.lo \
PromoteMemoryToRegister.lo SSAUpdater.lo SimplifyCFG.lo \
UnifyFunctionExitNodes.lo
libllvmcodegen_la_OBJECTS = $(am_libllvmcodegen_la_OBJECTS)
libllvmfullcodegen_la_LIBADD =
am_libllvmfullcodegen_la_OBJECTS = GCMetadataPrinter.lo \
IfConversion.lo IntrinsicLowering.lo MachineModuleInfoImpls.lo \
OcamlGC.lo RegAllocLocal.lo RegAllocPBQP.lo ShadowStackGC.lo \
Execution.lo ExternalFunctions.lo Interpreter.lo Target.lo \
IfConversion.lo IntrinsicLowering.lo OcamlGC.lo \
RegAllocLocal.lo RegAllocPBQP.lo ShadowStackGC.lo Execution.lo \
ExternalFunctions.lo Interpreter.lo Target.lo \
TargetAsmLexer.lo TargetELFWriterInfo.lo \
TargetIntrinsicInfo.lo
libllvmfullcodegen_la_OBJECTS = $(am_libllvmfullcodegen_la_OBJECTS)
@ -286,14 +288,13 @@ am_libllvmjit_la_OBJECTS = AliasAnalysis.lo BasicAliasAnalysis.lo \
JITDebugRegisterer.lo JITDwarfEmitter.lo JITEmitter.lo \
JITMemoryManager.lo OProfileJITEventListener.lo \
TargetSelect.lo MCAsmInfo.lo MCContext.lo MCExpr.lo \
MCSection.lo MCSectionELF.lo MCSectionMachO.lo MCSymbol.lo \
APFloat.lo APInt.lo Allocator.lo CommandLine.lo \
ConstantRange.lo Debug.lo Dwarf.lo ErrorHandling.lo \
FoldingSet.lo FormattedStream.lo GraphWriter.lo \
ManagedStatic.lo MemoryBuffer.lo PrettyStackTrace.lo \
SmallPtrSet.lo SmallVector.lo SourceMgr.lo Statistic.lo \
StringExtras.lo StringMap.lo StringPool.lo StringRef.lo \
TargetRegistry.lo Timer.lo Triple.lo Twine.lo \
MCSection.lo MCSectionELF.lo MCSymbol.lo APFloat.lo APInt.lo \
Allocator.lo CommandLine.lo ConstantRange.lo Debug.lo Dwarf.lo \
ErrorHandling.lo FoldingSet.lo FormattedStream.lo \
GraphWriter.lo ManagedStatic.lo MemoryBuffer.lo \
PrettyStackTrace.lo SmallPtrSet.lo SmallVector.lo SourceMgr.lo \
Statistic.lo StringExtras.lo StringMap.lo StringPool.lo \
StringRef.lo TargetRegistry.lo Timer.lo Triple.lo Twine.lo \
circular_raw_ostream.lo raw_ostream.lo Mangler.lo \
SubtargetFeature.lo TargetData.lo TargetInstrInfo.lo \
TargetLoweringObjectFile.lo TargetMachine.lo \
@ -363,11 +364,11 @@ libllvmsystem_la_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CXX \
$(AM_CXXFLAGS) $(CXXFLAGS) $(libllvmsystem_la_LDFLAGS) \
$(LDFLAGS) -o $@
libllvmx86codegen_la_LIBADD =
am__libllvmx86codegen_la_SOURCES_DIST = \
llvm/lib/CodeGen/MachineModuleInfoImpls.cpp \
llvm/lib/MC/MCAsmInfoCOFF.cpp llvm/lib/MC/MCCodeEmitter.cpp \
am__libllvmx86codegen_la_SOURCES_DIST = llvm/lib/MC/MCAsmInfoCOFF.cpp \
llvm/lib/MC/MCCodeEmitter.cpp llvm/lib/MC/TargetAsmBackend.cpp \
llvm/lib/Target/TargetELFWriterInfo.cpp \
llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp \
llvm/lib/Target/X86/X86AsmBackend.cpp \
llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp \
llvm/lib/Target/X86/X86CodeEmitter.cpp \
llvm/lib/Target/X86/X86ELFWriterInfo.cpp \
@ -385,11 +386,13 @@ am__libllvmx86codegen_la_SOURCES_DIST = \
llvm/lib/Target/X86/X86Subtarget.cpp \
llvm/lib/Target/X86/X86TargetMachine.cpp \
llvm/lib/Target/X86/X86TargetObjectFile.cpp
@BUILD_X86_TRUE@am_libllvmx86codegen_la_OBJECTS = libllvmx86codegen_la-MachineModuleInfoImpls.lo \
@BUILD_X86_TRUE@am_libllvmx86codegen_la_OBJECTS = \
@BUILD_X86_TRUE@ libllvmx86codegen_la-MCAsmInfoCOFF.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-MCCodeEmitter.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-TargetAsmBackend.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-TargetELFWriterInfo.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86TargetInfo.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86AsmBackend.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86COFFMachineModuleInfo.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86CodeEmitter.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86ELFWriterInfo.lo \
@ -517,6 +520,7 @@ am__tblgen_SOURCES_DIST = llvm/utils/TableGen/AsmMatcherEmitter.cpp \
llvm/utils/TableGen/DAGISelMatcher.cpp \
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp \
llvm/utils/TableGen/DAGISelMatcherGen.cpp \
llvm/utils/TableGen/DAGISelMatcherOpt.cpp \
llvm/utils/TableGen/DisassemblerEmitter.cpp \
llvm/utils/TableGen/EDEmitter.cpp \
llvm/utils/TableGen/FastISelEmitter.cpp \
@ -589,6 +593,7 @@ am__tblgen_SOURCES_DIST = llvm/utils/TableGen/AsmMatcherEmitter.cpp \
@MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcher.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcherEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcherGen.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcherOpt.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DisassemblerEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-EDEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-FastISelEmitter.$(OBJEXT) \
@ -1031,6 +1036,7 @@ libllvmsupport_la_SOURCES = \
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcher.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcherEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcherGen.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcherOpt.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DisassemblerEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/EDEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/FastISelEmitter.cpp\
@ -1113,7 +1119,7 @@ libllvmsupport_la_SOURCES = \
@MAINTAINER_MODE_TRUE@TBLGEN = $(top_builddir)/tblgen
@MAINTAINER_MODE_TRUE@TBLGEN_V = $(AM_V_GEN)$(TBLGEN)
@MAINTAINER_MODE_TRUE@TBLGEN_FLAGS = -I$(top_srcdir)/llvm/include -I$(top_srcdir)/llvm/lib/Target
@MAINTAINER_MODE_TRUE@TBLGEN_FLAGS = -I$(top_srcdir)/llvm/include -I$(top_srcdir)/llvm/lib/Target -omit-comments
# X86 Target
@MAINTAINER_MODE_TRUE@TBLGEN_FLAGS_X86 = $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/X86
@ -1125,11 +1131,12 @@ libllvmsupport_la_SOURCES = \
@MAINTAINER_MODE_TRUE@TBLGEN_FLAGS_ARM = $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/ARM
@BUILD_X86_TRUE@libllvmx86codegen_la_CPPFLAGS = $(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/X86
@BUILD_X86_TRUE@libllvmx86codegen_la_SOURCES = \
@BUILD_X86_TRUE@ llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
@BUILD_X86_TRUE@ llvm/lib/MC/MCAsmInfoCOFF.cpp\
@BUILD_X86_TRUE@ llvm/lib/MC/MCCodeEmitter.cpp\
@BUILD_X86_TRUE@ llvm/lib/MC/TargetAsmBackend.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/TargetELFWriterInfo.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86AsmBackend.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86CodeEmitter.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86ELFWriterInfo.cpp\
@ -1228,7 +1235,6 @@ libllvmjit_la_SOURCES = \
llvm/lib/MC/MCExpr.cpp\
llvm/lib/MC/MCSection.cpp\
llvm/lib/MC/MCSectionELF.cpp\
llvm/lib/MC/MCSectionMachO.cpp\
llvm/lib/MC/MCSymbol.cpp\
llvm/lib/Support/APFloat.cpp\
llvm/lib/Support/APInt.cpp\
@ -1332,9 +1338,11 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/LiveStackAnalysis.cpp\
llvm/lib/CodeGen/LiveVariables.cpp\
llvm/lib/CodeGen/LowerSubregs.cpp\
llvm/lib/CodeGen/MachineCSE.cpp\
llvm/lib/CodeGen/MachineDominators.cpp\
llvm/lib/CodeGen/MachineLICM.cpp\
llvm/lib/CodeGen/MachineLoopInfo.cpp\
llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/CodeGen/MachinePassRegistry.cpp\
llvm/lib/CodeGen/MachineSSAUpdater.cpp\
llvm/lib/CodeGen/MachineSink.cpp\
@ -1384,6 +1392,7 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/StackSlotColoring.cpp\
llvm/lib/CodeGen/StrongPHIElimination.cpp\
llvm/lib/CodeGen/TailDuplication.cpp\
llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp\
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp\
llvm/lib/CodeGen/UnreachableBlockElim.cpp\
llvm/lib/CodeGen/VirtRegMap.cpp\
@ -1394,6 +1403,7 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/MC/MCInst.cpp\
llvm/lib/MC/MCMachOStreamer.cpp\
llvm/lib/MC/MCNullStreamer.cpp\
llvm/lib/MC/MCSectionMachO.cpp\
llvm/lib/MC/MCStreamer.cpp\
llvm/lib/Target/TargetFrameInfo.cpp\
llvm/lib/Target/TargetSubtarget.cpp\
@ -1536,7 +1546,6 @@ libllvmfullcodegen_la_SOURCES = \
llvm/lib/CodeGen/GCMetadataPrinter.cpp\
llvm/lib/CodeGen/IfConversion.cpp\
llvm/lib/CodeGen/IntrinsicLowering.cpp\
llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/CodeGen/OcamlGC.cpp\
llvm/lib/CodeGen/RegAllocLocal.cpp\
llvm/lib/CodeGen/RegAllocPBQP.cpp\
@ -1877,6 +1886,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MCStreamer.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MCSymbol.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MachineBasicBlock.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MachineCSE.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MachineDominators.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MachineFunction.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MachineFunctionAnalysis.Plo@am__quote@
@ -1982,6 +1992,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetIntrinsicInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetLowering.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetLoweringObjectFile.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetLoweringObjectFileImpl.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetMachine.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetRegisterInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetRegistry.Plo@am__quote@
@ -2070,8 +2081,9 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmpowerpccodegen_la-PowerPCTargetInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-MCAsmInfoCOFF.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-MCCodeEmitter.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-MachineModuleInfoImpls.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-TargetAsmBackend.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-TargetELFWriterInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-X86AsmBackend.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-X86COFFMachineModuleInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-X86CodeEmitter.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-X86ELFWriterInfo.Plo@am__quote@
@ -2155,6 +2167,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-DAGISelMatcher.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-DAGISelMatcherEmitter.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-DAGISelMatcherGen.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-DAGISelMatcherOpt.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-Debug.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-DeltaAlgorithm.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-Disassembler.Po@am__quote@
@ -3131,6 +3144,14 @@ LowerSubregs.lo: llvm/lib/CodeGen/LowerSubregs.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o LowerSubregs.lo `test -f 'llvm/lib/CodeGen/LowerSubregs.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/LowerSubregs.cpp
MachineCSE.lo: llvm/lib/CodeGen/MachineCSE.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachineCSE.lo -MD -MP -MF $(DEPDIR)/MachineCSE.Tpo -c -o MachineCSE.lo `test -f 'llvm/lib/CodeGen/MachineCSE.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineCSE.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachineCSE.Tpo $(DEPDIR)/MachineCSE.Plo
@am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
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MachineDominators.lo: llvm/lib/CodeGen/MachineDominators.cpp
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@ -3155,6 +3176,14 @@ MachineLoopInfo.lo: llvm/lib/CodeGen/MachineLoopInfo.cpp
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MachineModuleInfoImpls.lo: llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
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MachinePassRegistry.lo: llvm/lib/CodeGen/MachinePassRegistry.cpp
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@ -3547,6 +3576,14 @@ TailDuplication.lo: llvm/lib/CodeGen/TailDuplication.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o TailDuplication.lo `test -f 'llvm/lib/CodeGen/TailDuplication.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/TailDuplication.cpp
TargetLoweringObjectFileImpl.lo: llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
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TwoAddressInstructionPass.lo: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
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@ -3627,6 +3664,14 @@ MCNullStreamer.lo: llvm/lib/MC/MCNullStreamer.cpp
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MCSectionMachO.lo: llvm/lib/MC/MCSectionMachO.cpp
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MCStreamer.lo: llvm/lib/MC/MCStreamer.cpp
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@ -3819,14 +3864,6 @@ IntrinsicLowering.lo: llvm/lib/CodeGen/IntrinsicLowering.cpp
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MachineModuleInfoImpls.lo: llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachineModuleInfoImpls.lo -MD -MP -MF $(DEPDIR)/MachineModuleInfoImpls.Tpo -c -o MachineModuleInfoImpls.lo `test -f 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
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OcamlGC.lo: llvm/lib/CodeGen/OcamlGC.cpp
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@ -4179,14 +4216,6 @@ MCSectionELF.lo: llvm/lib/MC/MCSectionELF.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MCSectionELF.lo `test -f 'llvm/lib/MC/MCSectionELF.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCSectionELF.cpp
MCSectionMachO.lo: llvm/lib/MC/MCSectionMachO.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MCSectionMachO.lo -MD -MP -MF $(DEPDIR)/MCSectionMachO.Tpo -c -o MCSectionMachO.lo `test -f 'llvm/lib/MC/MCSectionMachO.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCSectionMachO.cpp
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MCSymbol.lo: llvm/lib/MC/MCSymbol.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MCSymbol.lo -MD -MP -MF $(DEPDIR)/MCSymbol.Tpo -c -o MCSymbol.lo `test -f 'llvm/lib/MC/MCSymbol.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCSymbol.cpp
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@ -5043,14 +5072,6 @@ TimeValue.lo: llvm/lib/System/TimeValue.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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libllvmx86codegen_la-MachineModuleInfoImpls.lo: llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-MachineModuleInfoImpls.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-MachineModuleInfoImpls.Tpo -c -o libllvmx86codegen_la-MachineModuleInfoImpls.lo `test -f 'llvm/lib/CodeGen/MachineModuleInfoImpls.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
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libllvmx86codegen_la-MCAsmInfoCOFF.lo: llvm/lib/MC/MCAsmInfoCOFF.cpp
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@ -5067,6 +5088,14 @@ libllvmx86codegen_la-MCCodeEmitter.lo: llvm/lib/MC/MCCodeEmitter.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o libllvmx86codegen_la-MCCodeEmitter.lo `test -f 'llvm/lib/MC/MCCodeEmitter.cpp' || echo '$(srcdir)/'`llvm/lib/MC/MCCodeEmitter.cpp
libllvmx86codegen_la-TargetAsmBackend.lo: llvm/lib/MC/TargetAsmBackend.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-TargetAsmBackend.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-TargetAsmBackend.Tpo -c -o libllvmx86codegen_la-TargetAsmBackend.lo `test -f 'llvm/lib/MC/TargetAsmBackend.cpp' || echo '$(srcdir)/'`llvm/lib/MC/TargetAsmBackend.cpp
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libllvmx86codegen_la-TargetELFWriterInfo.lo: llvm/lib/Target/TargetELFWriterInfo.cpp
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@ -5083,6 +5112,14 @@ libllvmx86codegen_la-X86TargetInfo.lo: llvm/lib/Target/X86/TargetInfo/X86TargetI
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libllvmx86codegen_la-X86AsmBackend.lo: llvm/lib/Target/X86/X86AsmBackend.cpp
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@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/Target/X86/X86AsmBackend.cpp' object='libllvmx86codegen_la-X86AsmBackend.lo' libtool=yes @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o libllvmx86codegen_la-X86AsmBackend.lo `test -f 'llvm/lib/Target/X86/X86AsmBackend.cpp' || echo '$(srcdir)/'`llvm/lib/Target/X86/X86AsmBackend.cpp
libllvmx86codegen_la-X86COFFMachineModuleInfo.lo: llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libllvmx86codegen_la_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT libllvmx86codegen_la-X86COFFMachineModuleInfo.lo -MD -MP -MF $(DEPDIR)/libllvmx86codegen_la-X86COFFMachineModuleInfo.Tpo -c -o libllvmx86codegen_la-X86COFFMachineModuleInfo.lo `test -f 'llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp' || echo '$(srcdir)/'`llvm/lib/Target/X86/X86COFFMachineModuleInfo.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/libllvmx86codegen_la-X86COFFMachineModuleInfo.Tpo $(DEPDIR)/libllvmx86codegen_la-X86COFFMachineModuleInfo.Plo
@ -6035,6 +6072,22 @@ tblgen-DAGISelMatcherGen.obj: llvm/utils/TableGen/DAGISelMatcherGen.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelMatcherGen.obj `if test -f 'llvm/utils/TableGen/DAGISelMatcherGen.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelMatcherGen.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelMatcherGen.cpp'; fi`
tblgen-DAGISelMatcherOpt.o: llvm/utils/TableGen/DAGISelMatcherOpt.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelMatcherOpt.o -MD -MP -MF $(DEPDIR)/tblgen-DAGISelMatcherOpt.Tpo -c -o tblgen-DAGISelMatcherOpt.o `test -f 'llvm/utils/TableGen/DAGISelMatcherOpt.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelMatcherOpt.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelMatcherOpt.Tpo $(DEPDIR)/tblgen-DAGISelMatcherOpt.Po
@am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelMatcherOpt.cpp' object='tblgen-DAGISelMatcherOpt.o' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelMatcherOpt.o `test -f 'llvm/utils/TableGen/DAGISelMatcherOpt.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DAGISelMatcherOpt.cpp
tblgen-DAGISelMatcherOpt.obj: llvm/utils/TableGen/DAGISelMatcherOpt.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DAGISelMatcherOpt.obj -MD -MP -MF $(DEPDIR)/tblgen-DAGISelMatcherOpt.Tpo -c -o tblgen-DAGISelMatcherOpt.obj `if test -f 'llvm/utils/TableGen/DAGISelMatcherOpt.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelMatcherOpt.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelMatcherOpt.cpp'; fi`
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DAGISelMatcherOpt.Tpo $(DEPDIR)/tblgen-DAGISelMatcherOpt.Po
@am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/DAGISelMatcherOpt.cpp' object='tblgen-DAGISelMatcherOpt.obj' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelMatcherOpt.obj `if test -f 'llvm/utils/TableGen/DAGISelMatcherOpt.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelMatcherOpt.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelMatcherOpt.cpp'; fi`
tblgen-DisassemblerEmitter.o: llvm/utils/TableGen/DisassemblerEmitter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-DisassemblerEmitter.o -MD -MP -MF $(DEPDIR)/tblgen-DisassemblerEmitter.Tpo -c -o tblgen-DisassemblerEmitter.o `test -f 'llvm/utils/TableGen/DisassemblerEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/DisassemblerEmitter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/tblgen-DisassemblerEmitter.Tpo $(DEPDIR)/tblgen-DisassemblerEmitter.Po

170
libclamav/c++/PPCGenAsmWriter.inc
Unescape View File

@ -157,8 +157,7 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
268435860U, // FDIVS
268435867U, // FMADD
268435874U, // FMADDS
268468650U, // FMRD
268468650U, // FMRS
268468650U, // FMR
268468650U, // FMRSD
268435887U, // FMSUB
268435894U, // FMSUBS
@ -338,7 +337,6 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
270009560U, // STWBRX
270009568U, // STWCX
3409970408U, // STWU
3409970408U, // STWU8
268436718U, // STWUX
270009589U, // STWX
270009589U, // STWX8
@ -663,7 +661,7 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 12:
// MTFSF, STBU, STBU8, STDU, STFDU, STFSU, STHU, STHU8, STWU, STWU8
// MTFSF, STBU, STBU8, STDU, STFDU, STFSU, STHU, STHU8, STWU
printOperand(MI, 1);
O << ", ";
break;
@ -915,7 +913,7 @@ void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 45:
// STBU, STBU8, STFDU, STFSU, STHU, STHU8, STWU, STWU8
// STBU, STBU8, STFDU, STFSU, STHU, STHU8, STWU
printSymbolLo(MI, 2);
O << '(';
printOperand(MI, 3);
@ -1405,7 +1403,7 @@ const char *PPCAsmPrinter::getRegisterName(unsigned RegNo) {
/// from the instruction set description. This returns the enum name of the
/// specified instruction.
const char *PPCAsmPrinter::getInstructionName(unsigned Opcode) {
assert(Opcode < 521 && "Invalid instruction number!");
assert(Opcode < 519 && "Invalid instruction number!");
static const unsigned InstAsmOffset[] = {
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 135,
@ -1418,34 +1416,34 @@ const char *PPCAsmPrinter::getInstructionName(unsigned Opcode) {
1138, 1143, 1149, 1154, 1159, 1164, 1170, 1175, 1182, 1187, 1193, 1198, 1204, 1209,
1215, 1219, 1226, 1230, 1236, 1242, 1250, 1257, 1266, 1271, 1278, 1287, 1297, 1301,
1306, 1312, 1319, 1325, 1332, 1338, 1347, 1359, 1365, 1371, 1376, 1382, 1390, 1396,
1403, 1410, 1417, 1424, 1429, 1435, 1441, 1448, 1453, 1458, 1464, 1470, 1477, 1482,
1488, 1495, 1502, 1508, 1514, 1521, 1529, 1536, 1544, 1549, 1555, 1561, 1567, 1574,
1579, 1585, 1588, 1592, 1597, 1602, 1608, 1613, 1619, 1622, 1628, 1632, 1636, 1647,
1653, 1667, 1671, 1676, 1681, 1685, 1690, 1695, 1699, 1704, 1709, 1715, 1720, 1726,
1732, 1736, 1741, 1746, 1752, 1757, 1763, 1766, 1770, 1774, 1779, 1785, 1791, 1797,
1802, 1807, 1811, 1816, 1820, 1826, 1831, 1837, 1841, 1846, 1851, 1857, 1862, 1868,
1873, 1878, 1884, 1891, 1896, 1901, 1907, 1914, 1923, 1930, 1936, 1942, 1949, 1956,
1963, 1969, 1974, 1980, 1989, 1996, 2002, 2009, 2015, 2022, 2028, 2034, 2040, 2051,
2063, 2068, 2074, 2078, 2083, 2087, 2091, 2096, 2099, 2106, 2110, 2117, 2121, 2126,
2130, 2135, 2140, 2146, 2152, 2159, 2166, 2173, 2180, 2187, 2195, 2201, 2214, 2227,
2240, 2253, 2268, 2272, 2276, 2285, 2290, 2296, 2301, 2307, 2311, 2315, 2319, 2324,
2329, 2335, 2340, 2346, 2350, 2356, 2361, 2367, 2372, 2380, 2387, 2392, 2398, 2404,
2411, 2416, 2422, 2428, 2432, 2437, 2444, 2449, 2455, 2460, 2466, 2473, 2480, 2487,
2492, 2498, 2502, 2507, 2514, 2520, 2525, 2531, 2537, 2542, 2548, 2553, 2559, 2565,
2572, 2578, 2585, 2592, 2600, 2607, 2615, 2622, 2630, 2635, 2641, 2648, 2655, 2663,
2672, 2682, 2693, 2705, 2716, 2728, 2739, 2751, 2756, 2770, 2778, 2785, 2793, 2801,
2809, 2817, 2825, 2833, 2841, 2849, 2857, 2862, 2868, 2875, 2882, 2889, 2896, 2903,
2910, 2916, 2922, 2930, 2939, 2948, 2958, 2967, 2977, 2986, 2996, 3005, 3015, 3024,
3034, 3043, 3053, 3062, 3072, 3081, 3091, 3100, 3110, 3119, 3129, 3138, 3148, 3157,
3167, 3174, 3181, 3190, 3198, 3206, 3213, 3220, 3227, 3234, 3241, 3248, 3255, 3265,
3276, 3283, 3290, 3297, 3304, 3311, 3318, 3325, 3335, 3342, 3349, 3356, 3363, 3370,
3377, 3386, 3395, 3404, 3413, 3422, 3431, 3439, 3447, 3455, 3463, 3471, 3479, 3487,
3495, 3504, 3509, 3513, 3519, 3525, 3533, 3541, 3549, 3557, 3565, 3573, 3581, 3589,
3595, 3601, 3607, 3613, 3619, 3624, 3629, 3634, 3644, 3649, 3653, 3658, 3665, 3670,
3675, 3680, 3687, 3694, 3703, 3712, 3721, 3728, 3732, 3738, 3744, 3750, 3755, 3760,
3765, 3770, 3778, 3785, 3793, 3801, 3809, 3817, 3825, 3833, 3841, 3849, 3857, 3866,
3875, 3884, 3893, 3901, 3909, 3917, 3925, 3933, 3941, 3949, 3954, 3961, 3965, 3970,
3975, 3981, 3987, 0
1403, 1410, 1417, 1424, 1429, 1435, 1441, 1448, 1452, 1458, 1464, 1471, 1476, 1482,
1489, 1496, 1502, 1508, 1515, 1523, 1530, 1538, 1543, 1549, 1555, 1561, 1568, 1573,
1579, 1582, 1586, 1591, 1596, 1602, 1607, 1613, 1616, 1622, 1626, 1630, 1641, 1647,
1661, 1665, 1670, 1675, 1679, 1684, 1689, 1693, 1698, 1703, 1709, 1714, 1720, 1726,
1730, 1735, 1740, 1746, 1751, 1757, 1760, 1764, 1768, 1773, 1779, 1785, 1791, 1796,
1801, 1805, 1810, 1814, 1820, 1825, 1831, 1835, 1840, 1845, 1851, 1856, 1862, 1867,
1872, 1878, 1885, 1890, 1895, 1901, 1908, 1917, 1924, 1930, 1936, 1943, 1950, 1957,
1963, 1968, 1974, 1983, 1990, 1996, 2003, 2009, 2016, 2022, 2028, 2034, 2045, 2057,
2062, 2068, 2072, 2077, 2081, 2085, 2090, 2093, 2100, 2104, 2111, 2115, 2120, 2124,
2129, 2134, 2140, 2146, 2153, 2160, 2167, 2174, 2181, 2189, 2195, 2208, 2221, 2234,
2247, 2262, 2266, 2270, 2279, 2284, 2290, 2295, 2301, 2305, 2309, 2313, 2318, 2323,
2329, 2334, 2340, 2344, 2350, 2355, 2361, 2366, 2374, 2381, 2386, 2392, 2398, 2405,
2410, 2416, 2422, 2426, 2431, 2438, 2443, 2449, 2454, 2460, 2467, 2474, 2481, 2486,
2492, 2496, 2501, 2508, 2514, 2519, 2525, 2530, 2536, 2541, 2547, 2553, 2560, 2566,
2573, 2580, 2588, 2595, 2603, 2610, 2618, 2623, 2629, 2636, 2643, 2651, 2660, 2670,
2681, 2693, 2704, 2716, 2727, 2739, 2744, 2758, 2766, 2773, 2781, 2789, 2797, 2805,
2813, 2821, 2829, 2837, 2845, 2850, 2856, 2863, 2870, 2877, 2884, 2891, 2898, 2904,
2910, 2918, 2927, 2936, 2946, 2955, 2965, 2974, 2984, 2993, 3003, 3012, 3022, 3031,
3041, 3050, 3060, 3069, 3079, 3088, 3098, 3107, 3117, 3126, 3136, 3145, 3155, 3162,
3169, 3178, 3186, 3194, 3201, 3208, 3215, 3222, 3229, 3236, 3243, 3253, 3264, 3271,
3278, 3285, 3292, 3299, 3306, 3313, 3323, 3330, 3337, 3344, 3351, 3358, 3365, 3374,
3383, 3392, 3401, 3410, 3419, 3427, 3435, 3443, 3451, 3459, 3467, 3475, 3483, 3492,
3497, 3501, 3507, 3513, 3521, 3529, 3537, 3545, 3553, 3561, 3569, 3577, 3583, 3589,
3595, 3601, 3607, 3612, 3617, 3622, 3632, 3637, 3641, 3646, 3653, 3658, 3663, 3668,
3675, 3682, 3691, 3700, 3709, 3716, 3720, 3726, 3732, 3738, 3743, 3748, 3753, 3758,
3766, 3773, 3781, 3789, 3797, 3805, 3813, 3821, 3829, 3837, 3845, 3854, 3863, 3872,
3881, 3889, 3897, 3905, 3913, 3921, 3929, 3937, 3942, 3949, 3953, 3958, 3963, 3969,
3975, 0
};
const char *Strs =
@ -1475,58 +1473,58 @@ const char *PPCAsmPrinter::getInstructionName(unsigned Opcode) {
"NALLOC\000DYNALLOC8\000EQV\000EQV8\000EXTSB\000EXTSB8\000EXTSH\000EXTSH"
"8\000EXTSW\000EXTSW_32\000EXTSW_32_64\000FABSD\000FABSS\000FADD\000FADD"
"S\000FADDrtz\000FCFID\000FCMPUD\000FCMPUS\000FCTIDZ\000FCTIWZ\000FDIV\000"
"FDIVS\000FMADD\000FMADDS\000FMRD\000FMRS\000FMRSD\000FMSUB\000FMSUBS\000"
"FMUL\000FMULS\000FNABSD\000FNABSS\000FNEGD\000FNEGS\000FNMADD\000FNMADD"
"S\000FNMSUB\000FNMSUBS\000FRSP\000FSELD\000FSELS\000FSQRT\000FSQRTS\000"
"FSUB\000FSUBS\000LA\000LBZ\000LBZ8\000LBZU\000LBZU8\000LBZX\000LBZX8\000"
"LD\000LDARX\000LDU\000LDX\000LDinto_toc\000LDtoc\000LDtoc_restore\000LF"
"D\000LFDU\000LFDX\000LFS\000LFSU\000LFSX\000LHA\000LHA8\000LHAU\000LHAU"
"8\000LHAX\000LHAX8\000LHBRX\000LHZ\000LHZ8\000LHZU\000LHZU8\000LHZX\000"
"LHZX8\000LI\000LI8\000LIS\000LIS8\000LVEBX\000LVEHX\000LVEWX\000LVSL\000"
"LVSR\000LVX\000LVXL\000LWA\000LWARX\000LWAX\000LWBRX\000LWZ\000LWZ8\000"
"LWZU\000LWZU8\000LWZX\000LWZX8\000MCRF\000MFCR\000MFCTR\000MFCTR8\000MF"
"FS\000MFLR\000MFLR8\000MFOCRF\000MFVRSAVE\000MFVSCR\000MTCRF\000MTCTR\000"
"MTCTR8\000MTFSB0\000MTFSB1\000MTFSF\000MTLR\000MTLR8\000MTVRSAVE\000MTV"
"SCR\000MULHD\000MULHDU\000MULHW\000MULHWU\000MULLD\000MULLI\000MULLW\000"
"MovePCtoLR\000MovePCtoLR8\000NAND\000NAND8\000NEG\000NEG8\000NOP\000NOR"
"\000NOR8\000OR\000OR4To8\000OR8\000OR8To4\000ORC\000ORC8\000ORI\000ORI8"
"\000ORIS\000ORIS8\000RLDCL\000RLDICL\000RLDICR\000RLDIMI\000RLWIMI\000R"
"LWINM\000RLWINMo\000RLWNM\000SELECT_CC_F4\000SELECT_CC_F8\000SELECT_CC_"
"I4\000SELECT_CC_I8\000SELECT_CC_VRRC\000SLD\000SLW\000SPILL_CR\000SRAD\000"
"SRADI\000SRAW\000SRAWI\000SRD\000SRW\000STB\000STB8\000STBU\000STBU8\000"
"STBX\000STBX8\000STD\000STDCX\000STDU\000STDUX\000STDX\000STDX_32\000ST"
"D_32\000STFD\000STFDU\000STFDX\000STFIWX\000STFS\000STFSU\000STFSX\000S"
"TH\000STH8\000STHBRX\000STHU\000STHU8\000STHX\000STHX8\000STVEBX\000STV"
"EHX\000STVEWX\000STVX\000STVXL\000STW\000STW8\000STWBRX\000STWCX\000STW"
"U\000STWU8\000STWUX\000STWX\000STWX8\000SUBF\000SUBF8\000SUBFC\000SUBFC"
"8\000SUBFE\000SUBFE8\000SUBFIC\000SUBFIC8\000SUBFME\000SUBFME8\000SUBFZ"
"E\000SUBFZE8\000SYNC\000TAILB\000TAILB8\000TAILBA\000TAILBA8\000TAILBCT"
"R\000TAILBCTR8\000TCRETURNai\000TCRETURNai8\000TCRETURNdi\000TCRETURNdi"
"8\000TCRETURNri\000TCRETURNri8\000TRAP\000UPDATE_VRSAVE\000VADDCUW\000V"
"ADDFP\000VADDSBS\000VADDSHS\000VADDSWS\000VADDUBM\000VADDUBS\000VADDUHM"
"\000VADDUHS\000VADDUWM\000VADDUWS\000VAND\000VANDC\000VAVGSB\000VAVGSH\000"
"VAVGSW\000VAVGUB\000VAVGUH\000VAVGUW\000VCFSX\000VCFUX\000VCMPBFP\000VC"
"MPBFPo\000VCMPEQFP\000VCMPEQFPo\000VCMPEQUB\000VCMPEQUBo\000VCMPEQUH\000"
"VCMPEQUHo\000VCMPEQUW\000VCMPEQUWo\000VCMPGEFP\000VCMPGEFPo\000VCMPGTFP"
"\000VCMPGTFPo\000VCMPGTSB\000VCMPGTSBo\000VCMPGTSH\000VCMPGTSHo\000VCMP"
"GTSW\000VCMPGTSWo\000VCMPGTUB\000VCMPGTUBo\000VCMPGTUH\000VCMPGTUHo\000"
"VCMPGTUW\000VCMPGTUWo\000VCTSXS\000VCTUXS\000VEXPTEFP\000VLOGEFP\000VMA"
"DDFP\000VMAXFP\000VMAXSB\000VMAXSH\000VMAXSW\000VMAXUB\000VMAXUH\000VMA"
"XUW\000VMHADDSHS\000VMHRADDSHS\000VMINFP\000VMINSB\000VMINSH\000VMINSW\000"
"VMINUB\000VMINUH\000VMINUW\000VMLADDUHM\000VMRGHB\000VMRGHH\000VMRGHW\000"
"VMRGLB\000VMRGLH\000VMRGLW\000VMSUMMBM\000VMSUMSHM\000VMSUMSHS\000VMSUM"
"UBM\000VMSUMUHM\000VMSUMUHS\000VMULESB\000VMULESH\000VMULEUB\000VMULEUH"
"\000VMULOSB\000VMULOSH\000VMULOUB\000VMULOUH\000VNMSUBFP\000VNOR\000VOR"
"\000VPERM\000VPKPX\000VPKSHSS\000VPKSHUS\000VPKSWSS\000VPKSWUS\000VPKUH"
"UM\000VPKUHUS\000VPKUWUM\000VPKUWUS\000VREFP\000VRFIM\000VRFIN\000VRFIP"
"\000VRFIZ\000VRLB\000VRLH\000VRLW\000VRSQRTEFP\000VSEL\000VSL\000VSLB\000"
"VSLDOI\000VSLH\000VSLO\000VSLW\000VSPLTB\000VSPLTH\000VSPLTISB\000VSPLT"
"ISH\000VSPLTISW\000VSPLTW\000VSR\000VSRAB\000VSRAH\000VSRAW\000VSRB\000"
"VSRH\000VSRO\000VSRW\000VSUBCUW\000VSUBFP\000VSUBSBS\000VSUBSHS\000VSUB"
"SWS\000VSUBUBM\000VSUBUBS\000VSUBUHM\000VSUBUHS\000VSUBUWM\000VSUBUWS\000"
"VSUM2SWS\000VSUM4SBS\000VSUM4SHS\000VSUM4UBS\000VSUMSWS\000VUPKHPX\000V"
"UPKHSB\000VUPKHSH\000VUPKLPX\000VUPKLSB\000VUPKLSH\000VXOR\000V_SET0\000"
"XOR\000XOR8\000XORI\000XORI8\000XORIS\000XORIS8\000";
"FDIVS\000FMADD\000FMADDS\000FMR\000FMRSD\000FMSUB\000FMSUBS\000FMUL\000"
"FMULS\000FNABSD\000FNABSS\000FNEGD\000FNEGS\000FNMADD\000FNMADDS\000FNM"
"SUB\000FNMSUBS\000FRSP\000FSELD\000FSELS\000FSQRT\000FSQRTS\000FSUB\000"
"FSUBS\000LA\000LBZ\000LBZ8\000LBZU\000LBZU8\000LBZX\000LBZX8\000LD\000L"
"DARX\000LDU\000LDX\000LDinto_toc\000LDtoc\000LDtoc_restore\000LFD\000LF"
"DU\000LFDX\000LFS\000LFSU\000LFSX\000LHA\000LHA8\000LHAU\000LHAU8\000LH"
"AX\000LHAX8\000LHBRX\000LHZ\000LHZ8\000LHZU\000LHZU8\000LHZX\000LHZX8\000"
"LI\000LI8\000LIS\000LIS8\000LVEBX\000LVEHX\000LVEWX\000LVSL\000LVSR\000"
"LVX\000LVXL\000LWA\000LWARX\000LWAX\000LWBRX\000LWZ\000LWZ8\000LWZU\000"
"LWZU8\000LWZX\000LWZX8\000MCRF\000MFCR\000MFCTR\000MFCTR8\000MFFS\000MF"
"LR\000MFLR8\000MFOCRF\000MFVRSAVE\000MFVSCR\000MTCRF\000MTCTR\000MTCTR8"
"\000MTFSB0\000MTFSB1\000MTFSF\000MTLR\000MTLR8\000MTVRSAVE\000MTVSCR\000"
"MULHD\000MULHDU\000MULHW\000MULHWU\000MULLD\000MULLI\000MULLW\000MovePC"
"toLR\000MovePCtoLR8\000NAND\000NAND8\000NEG\000NEG8\000NOP\000NOR\000NO"
"R8\000OR\000OR4To8\000OR8\000OR8To4\000ORC\000ORC8\000ORI\000ORI8\000OR"
"IS\000ORIS8\000RLDCL\000RLDICL\000RLDICR\000RLDIMI\000RLWIMI\000RLWINM\000"
"RLWINMo\000RLWNM\000SELECT_CC_F4\000SELECT_CC_F8\000SELECT_CC_I4\000SEL"
"ECT_CC_I8\000SELECT_CC_VRRC\000SLD\000SLW\000SPILL_CR\000SRAD\000SRADI\000"
"SRAW\000SRAWI\000SRD\000SRW\000STB\000STB8\000STBU\000STBU8\000STBX\000"
"STBX8\000STD\000STDCX\000STDU\000STDUX\000STDX\000STDX_32\000STD_32\000"
"STFD\000STFDU\000STFDX\000STFIWX\000STFS\000STFSU\000STFSX\000STH\000ST"
"H8\000STHBRX\000STHU\000STHU8\000STHX\000STHX8\000STVEBX\000STVEHX\000S"
"TVEWX\000STVX\000STVXL\000STW\000STW8\000STWBRX\000STWCX\000STWU\000STW"
"UX\000STWX\000STWX8\000SUBF\000SUBF8\000SUBFC\000SUBFC8\000SUBFE\000SUB"
"FE8\000SUBFIC\000SUBFIC8\000SUBFME\000SUBFME8\000SUBFZE\000SUBFZE8\000S"
"YNC\000TAILB\000TAILB8\000TAILBA\000TAILBA8\000TAILBCTR\000TAILBCTR8\000"
"TCRETURNai\000TCRETURNai8\000TCRETURNdi\000TCRETURNdi8\000TCRETURNri\000"
"TCRETURNri8\000TRAP\000UPDATE_VRSAVE\000VADDCUW\000VADDFP\000VADDSBS\000"
"VADDSHS\000VADDSWS\000VADDUBM\000VADDUBS\000VADDUHM\000VADDUHS\000VADDU"
"WM\000VADDUWS\000VAND\000VANDC\000VAVGSB\000VAVGSH\000VAVGSW\000VAVGUB\000"
"VAVGUH\000VAVGUW\000VCFSX\000VCFUX\000VCMPBFP\000VCMPBFPo\000VCMPEQFP\000"
"VCMPEQFPo\000VCMPEQUB\000VCMPEQUBo\000VCMPEQUH\000VCMPEQUHo\000VCMPEQUW"
"\000VCMPEQUWo\000VCMPGEFP\000VCMPGEFPo\000VCMPGTFP\000VCMPGTFPo\000VCMP"
"GTSB\000VCMPGTSBo\000VCMPGTSH\000VCMPGTSHo\000VCMPGTSW\000VCMPGTSWo\000"
"VCMPGTUB\000VCMPGTUBo\000VCMPGTUH\000VCMPGTUHo\000VCMPGTUW\000VCMPGTUWo"
"\000VCTSXS\000VCTUXS\000VEXPTEFP\000VLOGEFP\000VMADDFP\000VMAXFP\000VMA"
"XSB\000VMAXSH\000VMAXSW\000VMAXUB\000VMAXUH\000VMAXUW\000VMHADDSHS\000V"
"MHRADDSHS\000VMINFP\000VMINSB\000VMINSH\000VMINSW\000VMINUB\000VMINUH\000"
"VMINUW\000VMLADDUHM\000VMRGHB\000VMRGHH\000VMRGHW\000VMRGLB\000VMRGLH\000"
"VMRGLW\000VMSUMMBM\000VMSUMSHM\000VMSUMSHS\000VMSUMUBM\000VMSUMUHM\000V"
"MSUMUHS\000VMULESB\000VMULESH\000VMULEUB\000VMULEUH\000VMULOSB\000VMULO"
"SH\000VMULOUB\000VMULOUH\000VNMSUBFP\000VNOR\000VOR\000VPERM\000VPKPX\000"
"VPKSHSS\000VPKSHUS\000VPKSWSS\000VPKSWUS\000VPKUHUM\000VPKUHUS\000VPKUW"
"UM\000VPKUWUS\000VREFP\000VRFIM\000VRFIN\000VRFIP\000VRFIZ\000VRLB\000V"
"RLH\000VRLW\000VRSQRTEFP\000VSEL\000VSL\000VSLB\000VSLDOI\000VSLH\000VS"
"LO\000VSLW\000VSPLTB\000VSPLTH\000VSPLTISB\000VSPLTISH\000VSPLTISW\000V"
"SPLTW\000VSR\000VSRAB\000VSRAH\000VSRAW\000VSRB\000VSRH\000VSRO\000VSRW"
"\000VSUBCUW\000VSUBFP\000VSUBSBS\000VSUBSHS\000VSUBSWS\000VSUBUBM\000VS"
"UBUBS\000VSUBUHM\000VSUBUHS\000VSUBUWM\000VSUBUWS\000VSUM2SWS\000VSUM4S"
"BS\000VSUM4SHS\000VSUM4UBS\000VSUMSWS\000VUPKHPX\000VUPKHSB\000VUPKHSH\000"
"VUPKLPX\000VUPKLSB\000VUPKLSH\000VXOR\000V_SET0\000XOR\000XOR8\000XORI\000"
"XORI8\000XORIS\000XORIS8\000";
return Strs+InstAsmOffset[Opcode];
}

14
libclamav/c++/PPCGenCallingConv.inc
Unescape View File

@ -75,14 +75,12 @@ static bool CC_PPC_SVR4_Common(unsigned ValNo, EVT ValVT,
}
if (LocVT == MVT::i32) {
if (!ArgFlags.isInReg()) {
static const unsigned RegList1[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
};
if (unsigned Reg = State.AllocateReg(RegList1, 8)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
static const unsigned RegList1[] = {
PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10
};
if (unsigned Reg = State.AllocateReg(RegList1, 8)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
}

10
libclamav/c++/PPCGenCodeEmitter.inc
Unescape View File

@ -155,8 +155,7 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
3959423012U, // FDIVS
4227858490U, // FMADD
3959423034U, // FMADDS
4227858576U, // FMRD
4227858576U, // FMRS
4227858576U, // FMR
4227858576U, // FMRSD
4227858488U, // FMSUB
3959423032U, // FMSUBS
@ -336,7 +335,6 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
2080376108U, // STWBRX
2080375085U, // STWCX
2483027968U, // STWU
2483027968U, // STWU8
2080375150U, // STWUX
2080375086U, // STWX
2080375086U, // STWX8
@ -772,8 +770,7 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::STFSU:
case PPC::STHU:
case PPC::STHU8:
case PPC::STWU:
case PPC::STWU8: {
case PPC::STWU: {
// op: A
op = getMachineOpValue(MI, MI.getOperand(1));
Value |= (op & 31U) << 21;
@ -1155,8 +1152,7 @@ unsigned PPCCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case PPC::FCFID:
case PPC::FCTIDZ:
case PPC::FCTIWZ:
case PPC::FMRD:
case PPC::FMRS:
case PPC::FMR:
case PPC::FMRSD:
case PPC::FNABSD:
case PPC::FNABSS:

14140
libclamav/c++/PPCGenDAGISel.inc
View File

File diff suppressed because it is too large Load Diff

746
libclamav/c++/PPCGenInstrInfo.inc
Unescape View File

@ -268,379 +268,377 @@ static const TargetInstrDesc PPCInsts[] = {
{ 144, 3, 1, 6, "FDIVS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #144 = FDIVS
{ 145, 4, 1, 7, "FMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #145 = FMADD
{ 146, 4, 1, 8, "FMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #146 = FMADDS
{ 147, 2, 1, 8, "FMRD", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo30 }, // Inst #147 = FMRD
{ 148, 2, 1, 8, "FMRS", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo31 }, // Inst #148 = FMRS
{ 149, 2, 1, 8, "FMRSD", 0, 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #149 = FMRSD
{ 150, 4, 1, 7, "FMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #150 = FMSUB
{ 151, 4, 1, 8, "FMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #151 = FMSUBS
{ 152, 3, 1, 7, "FMUL", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #152 = FMUL
{ 153, 3, 1, 8, "FMULS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #153 = FMULS
{ 154, 2, 1, 8, "FNABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #154 = FNABSD
{ 155, 2, 1, 8, "FNABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #155 = FNABSS
{ 156, 2, 1, 8, "FNEGD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #156 = FNEGD
{ 157, 2, 1, 8, "FNEGS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #157 = FNEGS
{ 158, 4, 1, 7, "FNMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #158 = FNMADD
{ 159, 4, 1, 8, "FNMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #159 = FNMADDS
{ 160, 4, 1, 7, "FNMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #160 = FNMSUB
{ 161, 4, 1, 8, "FNMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #161 = FNMSUBS
{ 162, 2, 1, 8, "FRSP", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo39 }, // Inst #162 = FRSP
{ 163, 4, 1, 8, "FSELD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo36 }, // Inst #163 = FSELD
{ 164, 4, 1, 8, "FSELS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo40 }, // Inst #164 = FSELS
{ 165, 2, 1, 10, "FSQRT", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #165 = FSQRT
{ 166, 2, 1, 10, "FSQRTS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo31 }, // Inst #166 = FSQRTS
{ 167, 3, 1, 8, "FSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #167 = FSUB
{ 168, 3, 1, 8, "FSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #168 = FSUBS
{ 169, 3, 1, 14, "LA", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #169 = LA
{ 170, 3, 1, 33, "LBZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #170 = LBZ
{ 171, 3, 1, 33, "LBZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #171 = LBZ8
{ 172, 4, 2, 33, "LBZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #172 = LBZU
{ 173, 4, 2, 33, "LBZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #173 = LBZU8
{ 174, 3, 1, 33, "LBZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #174 = LBZX
{ 175, 3, 1, 33, "LBZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #175 = LBZX8
{ 176, 3, 1, 35, "LD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #176 = LD
{ 177, 3, 1, 36, "LDARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo47 }, // Inst #177 = LDARX
{ 178, 4, 2, 35, "LDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #178 = LDU
{ 179, 3, 1, 35, "LDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #179 = LDX
{ 180, 1, 0, 35, "LDinto_toc", 0|(1<<TID::FoldableAsLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo48 }, // Inst #180 = LDinto_toc
{ 181, 3, 1, 35, "LDtoc", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo49 }, // Inst #181 = LDtoc
{ 182, 0, 0, 35, "LDtoc_restore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, 0 }, // Inst #182 = LDtoc_restore
{ 183, 3, 1, 37, "LFD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #183 = LFD
{ 184, 4, 2, 37, "LFDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #184 = LFDU
{ 185, 3, 1, 38, "LFDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #185 = LFDX
{ 186, 3, 1, 38, "LFS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #186 = LFS
{ 187, 4, 2, 38, "LFSU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo54 }, // Inst #187 = LFSU
{ 188, 3, 1, 38, "LFSX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #188 = LFSX
{ 189, 3, 1, 39, "LHA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #189 = LHA
{ 190, 3, 1, 39, "LHA8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #190 = LHA8
{ 191, 4, 2, 33, "LHAU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #191 = LHAU
{ 192, 4, 2, 33, "LHAU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #192 = LHAU8
{ 193, 3, 1, 39, "LHAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #193 = LHAX
{ 194, 3, 1, 39, "LHAX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #194 = LHAX8
{ 195, 3, 1, 33, "LHBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #195 = LHBRX
{ 196, 3, 1, 33, "LHZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #196 = LHZ
{ 197, 3, 1, 33, "LHZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #197 = LHZ8
{ 198, 4, 2, 33, "LHZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #198 = LHZU
{ 199, 4, 2, 33, "LHZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #199 = LHZU8
{ 200, 3, 1, 33, "LHZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #200 = LHZX
{ 201, 3, 1, 33, "LHZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #201 = LHZX8
{ 202, 2, 1, 14, "LI", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #202 = LI
{ 203, 2, 1, 14, "LI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #203 = LI8
{ 204, 2, 1, 14, "LIS", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #204 = LIS
{ 205, 2, 1, 14, "LIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #205 = LIS8
{ 206, 3, 1, 33, "LVEBX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #206 = LVEBX
{ 207, 3, 1, 33, "LVEHX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #207 = LVEHX
{ 208, 3, 1, 33, "LVEWX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #208 = LVEWX
{ 209, 3, 1, 33, "LVSL", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #209 = LVSL
{ 210, 3, 1, 33, "LVSR", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #210 = LVSR
{ 211, 3, 1, 33, "LVX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #211 = LVX
{ 212, 3, 1, 33, "LVXL", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #212 = LVXL
{ 213, 3, 1, 42, "LWA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #213 = LWA
{ 214, 3, 1, 43, "LWARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo46 }, // Inst #214 = LWARX
{ 215, 3, 1, 39, "LWAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #215 = LWAX
{ 216, 3, 1, 33, "LWBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #216 = LWBRX
{ 217, 3, 1, 33, "LWZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #217 = LWZ
{ 218, 3, 1, 33, "LWZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #218 = LWZ8
{ 219, 4, 2, 33, "LWZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #219 = LWZU
{ 220, 4, 2, 33, "LWZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #220 = LWZU8
{ 221, 3, 1, 33, "LWZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #221 = LWZX
{ 222, 3, 1, 33, "LWZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #222 = LWZX8
{ 223, 2, 1, 2, "MCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #223 = MCRF
{ 224, 1, 1, 54, "MFCR", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #224 = MFCR
{ 225, 1, 1, 56, "MFCTR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList4, NULL, NULL, OperandInfo60 }, // Inst #225 = MFCTR
{ 226, 1, 1, 56, "MFCTR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList13, NULL, NULL, OperandInfo48 }, // Inst #226 = MFCTR8
{ 227, 1, 1, 15, "MFFS", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo61 }, // Inst #227 = MFFS
{ 228, 1, 1, 56, "MFLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList14, NULL, NULL, OperandInfo60 }, // Inst #228 = MFLR
{ 229, 1, 1, 56, "MFLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList15, NULL, NULL, OperandInfo48 }, // Inst #229 = MFLR8
{ 230, 2, 1, 54, "MFOCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #230 = MFOCRF
{ 231, 1, 1, 14, "MFVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #231 = MFVRSAVE
{ 232, 1, 1, 33, "MFVSCR", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #232 = MFVSCR
{ 233, 2, 0, 3, "MTCRF", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo63 }, // Inst #233 = MTCRF
{ 234, 1, 0, 60, "MTCTR", 0, 0|1|(1<<3), NULL, ImplicitList4, Barriers4, OperandInfo60 }, // Inst #234 = MTCTR
{ 235, 1, 0, 60, "MTCTR8", 0, 0|1|(1<<3), NULL, ImplicitList13, Barriers5, OperandInfo48 }, // Inst #235 = MTCTR8
{ 236, 1, 0, 17, "MTFSB0", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #236 = MTFSB0
{ 237, 1, 0, 17, "MTFSB1", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #237 = MTFSB1
{ 238, 4, 1, 17, "MTFSF", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo64 }, // Inst #238 = MTFSF
{ 239, 1, 0, 60, "MTLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList14, NULL, OperandInfo60 }, // Inst #239 = MTLR
{ 240, 1, 0, 60, "MTLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList15, NULL, OperandInfo48 }, // Inst #240 = MTLR8
{ 241, 1, 0, 14, "MTVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<1)|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #241 = MTVRSAVE
{ 242, 1, 0, 33, "MTVSCR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #242 = MTVSCR
{ 243, 3, 1, 20, "MULHD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #243 = MULHD
{ 244, 3, 1, 21, "MULHDU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #244 = MULHDU
{ 245, 3, 1, 20, "MULHW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #245 = MULHW
{ 246, 3, 1, 21, "MULHWU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #246 = MULHWU
{ 247, 3, 1, 19, "MULLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #247 = MULLD
{ 248, 3, 1, 22, "MULLI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #248 = MULLI
{ 249, 3, 1, 20, "MULLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #249 = MULLW
{ 250, 1, 0, 52, "MovePCtoLR", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList14, NULL, OperandInfo8 }, // Inst #250 = MovePCtoLR
{ 251, 1, 0, 52, "MovePCtoLR8", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList15, NULL, OperandInfo8 }, // Inst #251 = MovePCtoLR8
{ 252, 3, 1, 14, "NAND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #252 = NAND
{ 253, 3, 1, 14, "NAND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #253 = NAND8
{ 254, 2, 1, 14, "NEG", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #254 = NEG
{ 255, 2, 1, 14, "NEG8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #255 = NEG8
{ 256, 0, 0, 14, "NOP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, 0 }, // Inst #256 = NOP
{ 257, 3, 1, 14, "NOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #257 = NOR
{ 258, 3, 1, 14, "NOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #258 = NOR8
{ 259, 3, 1, 14, "OR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #259 = OR
{ 260, 3, 1, 14, "OR4To8", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo65 }, // Inst #260 = OR4To8
{ 261, 3, 1, 14, "OR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #261 = OR8
{ 262, 3, 1, 14, "OR8To4", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo66 }, // Inst #262 = OR8To4
{ 263, 3, 1, 14, "ORC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #263 = ORC
{ 264, 3, 1, 14, "ORC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #264 = ORC8
{ 265, 3, 1, 14, "ORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #265 = ORI
{ 266, 3, 1, 14, "ORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #266 = ORI8
{ 267, 3, 1, 14, "ORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #267 = ORIS
{ 268, 3, 1, 14, "ORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #268 = ORIS8
{ 269, 4, 1, 25, "RLDCL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo67 }, // Inst #269 = RLDCL
{ 270, 4, 1, 25, "RLDICL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #270 = RLDICL
{ 271, 4, 1, 25, "RLDICR", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #271 = RLDICR
{ 272, 5, 1, 25, "RLDIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo69 }, // Inst #272 = RLDIMI
{ 273, 6, 1, 24, "RLWIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo70 }, // Inst #273 = RLWIMI
{ 274, 5, 1, 14, "RLWINM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo71 }, // Inst #274 = RLWINM
{ 275, 5, 1, 14, "RLWINMo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, ImplicitList3, NULL, OperandInfo71 }, // Inst #275 = RLWINMo
{ 276, 5, 1, 14, "RLWNM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo72 }, // Inst #276 = RLWNM
{ 277, 5, 1, 52, "SELECT_CC_F4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo73 }, // Inst #277 = SELECT_CC_F4
{ 278, 5, 1, 52, "SELECT_CC_F8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo74 }, // Inst #278 = SELECT_CC_F8
{ 279, 5, 1, 52, "SELECT_CC_I4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo75 }, // Inst #279 = SELECT_CC_I4
{ 280, 5, 1, 52, "SELECT_CC_I8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo76 }, // Inst #280 = SELECT_CC_I8
{ 281, 5, 1, 52, "SELECT_CC_VRRC", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo77 }, // Inst #281 = SELECT_CC_VRRC
{ 282, 3, 1, 25, "SLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #282 = SLD
{ 283, 3, 1, 14, "SLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #283 = SLW
{ 284, 3, 0, 52, "SPILL_CR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo42 }, // Inst #284 = SPILL_CR
{ 285, 3, 1, 25, "SRAD", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo78 }, // Inst #285 = SRAD
{ 286, 3, 1, 25, "SRADI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #286 = SRADI
{ 287, 3, 1, 26, "SRAW", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #287 = SRAW
{ 288, 3, 1, 26, "SRAWI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #288 = SRAWI
{ 289, 3, 1, 25, "SRD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #289 = SRD
{ 290, 3, 1, 14, "SRW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #290 = SRW
{ 291, 3, 0, 33, "STB", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #291 = STB
{ 292, 3, 0, 33, "STB8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #292 = STB8
{ 293, 4, 1, 33, "STBU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #293 = STBU
{ 294, 4, 1, 33, "STBU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #294 = STBU8
{ 295, 3, 0, 33, "STBX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #295 = STBX
{ 296, 3, 0, 33, "STBX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #296 = STBX8
{ 297, 3, 0, 46, "STD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #297 = STD
{ 298, 3, 0, 47, "STDCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo47 }, // Inst #298 = STDCX
{ 299, 4, 1, 46, "STDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #299 = STDU
{ 300, 3, 0, 46, "STDUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #300 = STDUX
{ 301, 3, 0, 46, "STDX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #301 = STDX
{ 302, 3, 0, 46, "STDX_32", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #302 = STDX_32
{ 303, 3, 0, 46, "STD_32", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #303 = STD_32
{ 304, 3, 0, 51, "STFD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #304 = STFD
{ 305, 4, 1, 33, "STFDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo81 }, // Inst #305 = STFDU
{ 306, 3, 0, 51, "STFDX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #306 = STFDX
{ 307, 3, 0, 51, "STFIWX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #307 = STFIWX
{ 308, 3, 0, 51, "STFS", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #308 = STFS
{ 309, 4, 1, 33, "STFSU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo82 }, // Inst #309 = STFSU
{ 310, 3, 0, 51, "STFSX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #310 = STFSX
{ 311, 3, 0, 33, "STH", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #311 = STH
{ 312, 3, 0, 33, "STH8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #312 = STH8
{ 313, 3, 0, 33, "STHBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #313 = STHBRX
{ 314, 4, 1, 33, "STHU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #314 = STHU
{ 315, 4, 1, 33, "STHU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #315 = STHU8
{ 316, 3, 0, 33, "STHX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #316 = STHX
{ 317, 3, 0, 33, "STHX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #317 = STHX8
{ 318, 3, 0, 33, "STVEBX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #318 = STVEBX
{ 319, 3, 0, 33, "STVEHX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #319 = STVEHX
{ 320, 3, 0, 33, "STVEWX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #320 = STVEWX
{ 321, 3, 0, 33, "STVX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #321 = STVX
{ 322, 3, 0, 33, "STVXL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #322 = STVXL
{ 323, 3, 0, 33, "STW", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #323 = STW
{ 324, 3, 0, 33, "STW8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #324 = STW8
{ 325, 3, 0, 33, "STWBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #325 = STWBRX
{ 326, 3, 0, 49, "STWCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo46 }, // Inst #326 = STWCX
{ 327, 4, 1, 33, "STWU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #327 = STWU
{ 328, 4, 1, 33, "STWU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #328 = STWU8
{ 329, 3, 0, 33, "STWUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #329 = STWUX
{ 330, 3, 0, 33, "STWX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #330 = STWX
{ 331, 3, 0, 33, "STWX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #331 = STWX8
{ 332, 3, 1, 14, "SUBF", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #332 = SUBF
{ 333, 3, 1, 14, "SUBF8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #333 = SUBF8
{ 334, 3, 1, 14, "SUBFC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #334 = SUBFC
{ 335, 3, 1, 14, "SUBFC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #335 = SUBFC8
{ 336, 3, 1, 14, "SUBFE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #336 = SUBFE
{ 337, 3, 1, 14, "SUBFE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #337 = SUBFE8
{ 338, 3, 1, 14, "SUBFIC", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #338 = SUBFIC
{ 339, 3, 1, 14, "SUBFIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #339 = SUBFIC8
{ 340, 2, 1, 14, "SUBFME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #340 = SUBFME
{ 341, 2, 1, 14, "SUBFME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #341 = SUBFME8
{ 342, 2, 1, 14, "SUBFZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #342 = SUBFZE
{ 343, 2, 1, 14, "SUBFZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #343 = SUBFZE8
{ 344, 0, 0, 50, "SYNC", 0|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #344 = SYNC
{ 345, 1, 0, 0, "TAILB", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #345 = TAILB
{ 346, 1, 0, 0, "TAILB8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #346 = TAILB8
{ 347, 1, 0, 0, "TAILBA", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #347 = TAILBA
{ 348, 1, 0, 0, "TAILBA8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #348 = TAILBA8
{ 349, 0, 0, 0, "TAILBCTR", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #349 = TAILBCTR
{ 350, 0, 0, 0, "TAILBCTR8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #350 = TAILBCTR8
{ 351, 2, 0, 52, "TCRETURNai", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #351 = TCRETURNai
{ 352, 2, 0, 52, "TCRETURNai8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #352 = TCRETURNai8
{ 353, 2, 0, 52, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #353 = TCRETURNdi
{ 354, 2, 0, 52, "TCRETURNdi8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #354 = TCRETURNdi8
{ 355, 2, 0, 52, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo83 }, // Inst #355 = TCRETURNri
{ 356, 2, 0, 52, "TCRETURNri8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo84 }, // Inst #356 = TCRETURNri8
{ 357, 0, 0, 33, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #357 = TRAP
{ 358, 2, 1, 52, "UPDATE_VRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo6 }, // Inst #358 = UPDATE_VRSAVE
{ 359, 3, 1, 67, "VADDCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #359 = VADDCUW
{ 360, 3, 1, 67, "VADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #360 = VADDFP
{ 361, 3, 1, 67, "VADDSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #361 = VADDSBS
{ 362, 3, 1, 67, "VADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #362 = VADDSHS
{ 363, 3, 1, 67, "VADDSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #363 = VADDSWS
{ 364, 3, 1, 70, "VADDUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #364 = VADDUBM
{ 365, 3, 1, 67, "VADDUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #365 = VADDUBS
{ 366, 3, 1, 70, "VADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #366 = VADDUHM
{ 367, 3, 1, 67, "VADDUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #367 = VADDUHS
{ 368, 3, 1, 70, "VADDUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #368 = VADDUWM
{ 369, 3, 1, 67, "VADDUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #369 = VADDUWS
{ 370, 3, 1, 67, "VAND", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #370 = VAND
{ 371, 3, 1, 67, "VANDC", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #371 = VANDC
{ 372, 3, 1, 67, "VAVGSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #372 = VAVGSB
{ 373, 3, 1, 67, "VAVGSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #373 = VAVGSH
{ 374, 3, 1, 67, "VAVGSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #374 = VAVGSW
{ 375, 3, 1, 67, "VAVGUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #375 = VAVGUB
{ 376, 3, 1, 67, "VAVGUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #376 = VAVGUH
{ 377, 3, 1, 67, "VAVGUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #377 = VAVGUW
{ 378, 3, 1, 67, "VCFSX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #378 = VCFSX
{ 379, 3, 1, 67, "VCFUX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #379 = VCFUX
{ 380, 3, 1, 68, "VCMPBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #380 = VCMPBFP
{ 381, 3, 1, 68, "VCMPBFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #381 = VCMPBFPo
{ 382, 3, 1, 68, "VCMPEQFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #382 = VCMPEQFP
{ 383, 3, 1, 68, "VCMPEQFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #383 = VCMPEQFPo
{ 384, 3, 1, 68, "VCMPEQUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #384 = VCMPEQUB
{ 385, 3, 1, 68, "VCMPEQUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #385 = VCMPEQUBo
{ 386, 3, 1, 68, "VCMPEQUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #386 = VCMPEQUH
{ 387, 3, 1, 68, "VCMPEQUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #387 = VCMPEQUHo
{ 388, 3, 1, 68, "VCMPEQUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #388 = VCMPEQUW
{ 389, 3, 1, 68, "VCMPEQUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #389 = VCMPEQUWo
{ 390, 3, 1, 68, "VCMPGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #390 = VCMPGEFP
{ 391, 3, 1, 68, "VCMPGEFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #391 = VCMPGEFPo
{ 392, 3, 1, 68, "VCMPGTFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #392 = VCMPGTFP
{ 393, 3, 1, 68, "VCMPGTFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #393 = VCMPGTFPo
{ 394, 3, 1, 68, "VCMPGTSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #394 = VCMPGTSB
{ 395, 3, 1, 68, "VCMPGTSBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #395 = VCMPGTSBo
{ 396, 3, 1, 68, "VCMPGTSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #396 = VCMPGTSH
{ 397, 3, 1, 68, "VCMPGTSHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #397 = VCMPGTSHo
{ 398, 3, 1, 68, "VCMPGTSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #398 = VCMPGTSW
{ 399, 3, 1, 68, "VCMPGTSWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #399 = VCMPGTSWo
{ 400, 3, 1, 68, "VCMPGTUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #400 = VCMPGTUB
{ 401, 3, 1, 68, "VCMPGTUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #401 = VCMPGTUBo
{ 402, 3, 1, 68, "VCMPGTUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #402 = VCMPGTUH
{ 403, 3, 1, 68, "VCMPGTUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #403 = VCMPGTUHo
{ 404, 3, 1, 68, "VCMPGTUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #404 = VCMPGTUW
{ 405, 3, 1, 68, "VCMPGTUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #405 = VCMPGTUWo
{ 406, 3, 1, 67, "VCTSXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #406 = VCTSXS
{ 407, 3, 1, 67, "VCTUXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #407 = VCTUXS
{ 408, 2, 1, 67, "VEXPTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #408 = VEXPTEFP
{ 409, 2, 1, 67, "VLOGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #409 = VLOGEFP
{ 410, 4, 1, 67, "VMADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #410 = VMADDFP
{ 411, 3, 1, 67, "VMAXFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #411 = VMAXFP
{ 412, 3, 1, 67, "VMAXSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #412 = VMAXSB
{ 413, 3, 1, 67, "VMAXSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #413 = VMAXSH
{ 414, 3, 1, 67, "VMAXSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #414 = VMAXSW
{ 415, 3, 1, 67, "VMAXUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #415 = VMAXUB
{ 416, 3, 1, 67, "VMAXUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #416 = VMAXUH
{ 417, 3, 1, 67, "VMAXUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #417 = VMAXUW
{ 418, 4, 1, 67, "VMHADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #418 = VMHADDSHS
{ 419, 4, 1, 67, "VMHRADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #419 = VMHRADDSHS
{ 420, 3, 1, 67, "VMINFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #420 = VMINFP
{ 421, 3, 1, 67, "VMINSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #421 = VMINSB
{ 422, 3, 1, 67, "VMINSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #422 = VMINSH
{ 423, 3, 1, 67, "VMINSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #423 = VMINSW
{ 424, 3, 1, 67, "VMINUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #424 = VMINUB
{ 425, 3, 1, 67, "VMINUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #425 = VMINUH
{ 426, 3, 1, 67, "VMINUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #426 = VMINUW
{ 427, 4, 1, 67, "VMLADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #427 = VMLADDUHM
{ 428, 3, 1, 67, "VMRGHB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #428 = VMRGHB
{ 429, 3, 1, 67, "VMRGHH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #429 = VMRGHH
{ 430, 3, 1, 67, "VMRGHW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #430 = VMRGHW
{ 431, 3, 1, 67, "VMRGLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #431 = VMRGLB
{ 432, 3, 1, 67, "VMRGLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #432 = VMRGLH
{ 433, 3, 1, 67, "VMRGLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #433 = VMRGLW
{ 434, 4, 1, 67, "VMSUMMBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #434 = VMSUMMBM
{ 435, 4, 1, 67, "VMSUMSHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #435 = VMSUMSHM
{ 436, 4, 1, 67, "VMSUMSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #436 = VMSUMSHS
{ 437, 4, 1, 67, "VMSUMUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #437 = VMSUMUBM
{ 438, 4, 1, 67, "VMSUMUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #438 = VMSUMUHM
{ 439, 4, 1, 67, "VMSUMUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #439 = VMSUMUHS
{ 440, 3, 1, 67, "VMULESB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #440 = VMULESB
{ 441, 3, 1, 67, "VMULESH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #441 = VMULESH
{ 442, 3, 1, 67, "VMULEUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #442 = VMULEUB
{ 443, 3, 1, 67, "VMULEUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #443 = VMULEUH
{ 444, 3, 1, 67, "VMULOSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #444 = VMULOSB
{ 445, 3, 1, 67, "VMULOSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #445 = VMULOSH
{ 446, 3, 1, 67, "VMULOUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #446 = VMULOUB
{ 447, 3, 1, 67, "VMULOUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #447 = VMULOUH
{ 448, 4, 1, 67, "VNMSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #448 = VNMSUBFP
{ 449, 3, 1, 67, "VNOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #449 = VNOR
{ 450, 3, 1, 67, "VOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #450 = VOR
{ 451, 4, 1, 67, "VPERM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #451 = VPERM
{ 452, 3, 1, 67, "VPKPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #452 = VPKPX
{ 453, 3, 1, 67, "VPKSHSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #453 = VPKSHSS
{ 454, 3, 1, 67, "VPKSHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #454 = VPKSHUS
{ 455, 3, 1, 67, "VPKSWSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #455 = VPKSWSS
{ 456, 3, 1, 67, "VPKSWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #456 = VPKSWUS
{ 457, 3, 1, 67, "VPKUHUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #457 = VPKUHUM
{ 458, 3, 1, 67, "VPKUHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #458 = VPKUHUS
{ 459, 3, 1, 67, "VPKUWUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #459 = VPKUWUM
{ 460, 3, 1, 67, "VPKUWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #460 = VPKUWUS
{ 461, 2, 1, 67, "VREFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #461 = VREFP
{ 462, 2, 1, 67, "VRFIM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #462 = VRFIM
{ 463, 2, 1, 67, "VRFIN", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #463 = VRFIN
{ 464, 2, 1, 67, "VRFIP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #464 = VRFIP
{ 465, 2, 1, 67, "VRFIZ", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #465 = VRFIZ
{ 466, 3, 1, 67, "VRLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #466 = VRLB
{ 467, 3, 1, 67, "VRLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #467 = VRLH
{ 468, 3, 1, 67, "VRLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #468 = VRLW
{ 469, 2, 1, 67, "VRSQRTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #469 = VRSQRTEFP
{ 470, 4, 1, 67, "VSEL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #470 = VSEL
{ 471, 3, 1, 67, "VSL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #471 = VSL
{ 472, 3, 1, 67, "VSLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #472 = VSLB
{ 473, 4, 1, 67, "VSLDOI", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo89 }, // Inst #473 = VSLDOI
{ 474, 3, 1, 67, "VSLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #474 = VSLH
{ 475, 3, 1, 67, "VSLO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #475 = VSLO
{ 476, 3, 1, 67, "VSLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #476 = VSLW
{ 477, 3, 1, 71, "VSPLTB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #477 = VSPLTB
{ 478, 3, 1, 71, "VSPLTH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #478 = VSPLTH
{ 479, 2, 1, 71, "VSPLTISB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #479 = VSPLTISB
{ 480, 2, 1, 71, "VSPLTISH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #480 = VSPLTISH
{ 481, 2, 1, 71, "VSPLTISW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #481 = VSPLTISW
{ 482, 3, 1, 71, "VSPLTW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #482 = VSPLTW
{ 483, 3, 1, 67, "VSR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #483 = VSR
{ 484, 3, 1, 67, "VSRAB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #484 = VSRAB
{ 485, 3, 1, 67, "VSRAH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #485 = VSRAH
{ 486, 3, 1, 67, "VSRAW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #486 = VSRAW
{ 487, 3, 1, 67, "VSRB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #487 = VSRB
{ 488, 3, 1, 67, "VSRH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #488 = VSRH
{ 489, 3, 1, 67, "VSRO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #489 = VSRO
{ 490, 3, 1, 67, "VSRW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #490 = VSRW
{ 491, 3, 1, 67, "VSUBCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #491 = VSUBCUW
{ 492, 3, 1, 70, "VSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #492 = VSUBFP
{ 493, 3, 1, 67, "VSUBSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #493 = VSUBSBS
{ 494, 3, 1, 67, "VSUBSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #494 = VSUBSHS
{ 495, 3, 1, 67, "VSUBSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #495 = VSUBSWS
{ 496, 3, 1, 70, "VSUBUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #496 = VSUBUBM
{ 497, 3, 1, 67, "VSUBUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #497 = VSUBUBS
{ 498, 3, 1, 70, "VSUBUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #498 = VSUBUHM
{ 499, 3, 1, 67, "VSUBUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #499 = VSUBUHS
{ 500, 3, 1, 70, "VSUBUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #500 = VSUBUWM
{ 501, 3, 1, 67, "VSUBUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #501 = VSUBUWS
{ 502, 3, 1, 67, "VSUM2SWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #502 = VSUM2SWS
{ 503, 3, 1, 67, "VSUM4SBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #503 = VSUM4SBS
{ 504, 3, 1, 67, "VSUM4SHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #504 = VSUM4SHS
{ 505, 3, 1, 67, "VSUM4UBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #505 = VSUM4UBS
{ 506, 3, 1, 67, "VSUMSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #506 = VSUMSWS
{ 507, 2, 1, 67, "VUPKHPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #507 = VUPKHPX
{ 508, 2, 1, 67, "VUPKHSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #508 = VUPKHSB
{ 509, 2, 1, 67, "VUPKHSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #509 = VUPKHSH
{ 510, 2, 1, 67, "VUPKLPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #510 = VUPKLPX
{ 511, 2, 1, 67, "VUPKLSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #511 = VUPKLSB
{ 512, 2, 1, 67, "VUPKLSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #512 = VUPKLSH
{ 513, 3, 1, 67, "VXOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #513 = VXOR
{ 514, 1, 1, 67, "V_SET0", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo62 }, // Inst #514 = V_SET0
{ 515, 3, 1, 14, "XOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #515 = XOR
{ 516, 3, 1, 14, "XOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #516 = XOR8
{ 517, 3, 1, 14, "XORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #517 = XORI
{ 518, 3, 1, 14, "XORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #518 = XORI8
{ 519, 3, 1, 14, "XORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #519 = XORIS
{ 520, 3, 1, 14, "XORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #520 = XORIS8
{ 147, 2, 1, 8, "FMR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo31 }, // Inst #147 = FMR
{ 148, 2, 1, 8, "FMRSD", 0, 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #148 = FMRSD
{ 149, 4, 1, 7, "FMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #149 = FMSUB
{ 150, 4, 1, 8, "FMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #150 = FMSUBS
{ 151, 3, 1, 7, "FMUL", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #151 = FMUL
{ 152, 3, 1, 8, "FMULS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #152 = FMULS
{ 153, 2, 1, 8, "FNABSD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #153 = FNABSD
{ 154, 2, 1, 8, "FNABSS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #154 = FNABSS
{ 155, 2, 1, 8, "FNEGD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo30 }, // Inst #155 = FNEGD
{ 156, 2, 1, 8, "FNEGS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo31 }, // Inst #156 = FNEGS
{ 157, 4, 1, 7, "FNMADD", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #157 = FNMADD
{ 158, 4, 1, 8, "FNMADDS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #158 = FNMADDS
{ 159, 4, 1, 7, "FNMSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo36 }, // Inst #159 = FNMSUB
{ 160, 4, 1, 8, "FNMSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo37 }, // Inst #160 = FNMSUBS
{ 161, 2, 1, 8, "FRSP", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo39 }, // Inst #161 = FRSP
{ 162, 4, 1, 8, "FSELD", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo36 }, // Inst #162 = FSELD
{ 163, 4, 1, 8, "FSELS", 0, 0|(3<<3), NULL, NULL, NULL, OperandInfo40 }, // Inst #163 = FSELS
{ 164, 2, 1, 10, "FSQRT", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo30 }, // Inst #164 = FSQRT
{ 165, 2, 1, 10, "FSQRTS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo31 }, // Inst #165 = FSQRTS
{ 166, 3, 1, 8, "FSUB", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo32 }, // Inst #166 = FSUB
{ 167, 3, 1, 8, "FSUBS", 0, 0|(3<<3), ImplicitList10, NULL, NULL, OperandInfo33 }, // Inst #167 = FSUBS
{ 168, 3, 1, 14, "LA", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #168 = LA
{ 169, 3, 1, 33, "LBZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #169 = LBZ
{ 170, 3, 1, 33, "LBZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #170 = LBZ8
{ 171, 4, 2, 33, "LBZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #171 = LBZU
{ 172, 4, 2, 33, "LBZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #172 = LBZU8
{ 173, 3, 1, 33, "LBZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #173 = LBZX
{ 174, 3, 1, 33, "LBZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #174 = LBZX8
{ 175, 3, 1, 35, "LD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #175 = LD
{ 176, 3, 1, 36, "LDARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo47 }, // Inst #176 = LDARX
{ 177, 4, 2, 35, "LDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #177 = LDU
{ 178, 3, 1, 35, "LDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #178 = LDX
{ 179, 1, 0, 35, "LDinto_toc", 0|(1<<TID::FoldableAsLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo48 }, // Inst #179 = LDinto_toc
{ 180, 3, 1, 35, "LDtoc", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo49 }, // Inst #180 = LDtoc
{ 181, 0, 0, 35, "LDtoc_restore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, 0 }, // Inst #181 = LDtoc_restore
{ 182, 3, 1, 37, "LFD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #182 = LFD
{ 183, 4, 2, 37, "LFDU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo51 }, // Inst #183 = LFDU
{ 184, 3, 1, 38, "LFDX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #184 = LFDX
{ 185, 3, 1, 38, "LFS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #185 = LFS
{ 186, 4, 2, 38, "LFSU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo54 }, // Inst #186 = LFSU
{ 187, 3, 1, 38, "LFSX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #187 = LFSX
{ 188, 3, 1, 39, "LHA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #188 = LHA
{ 189, 3, 1, 39, "LHA8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #189 = LHA8
{ 190, 4, 2, 33, "LHAU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #190 = LHAU
{ 191, 4, 2, 33, "LHAU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #191 = LHAU8
{ 192, 3, 1, 39, "LHAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #192 = LHAX
{ 193, 3, 1, 39, "LHAX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #193 = LHAX8
{ 194, 3, 1, 33, "LHBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #194 = LHBRX
{ 195, 3, 1, 33, "LHZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #195 = LHZ
{ 196, 3, 1, 33, "LHZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #196 = LHZ8
{ 197, 4, 2, 33, "LHZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #197 = LHZU
{ 198, 4, 2, 33, "LHZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #198 = LHZU8
{ 199, 3, 1, 33, "LHZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #199 = LHZX
{ 200, 3, 1, 33, "LHZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #200 = LHZX8
{ 201, 2, 1, 14, "LI", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #201 = LI
{ 202, 2, 1, 14, "LI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #202 = LI8
{ 203, 2, 1, 14, "LIS", 0|(1<<TID::Rematerializable), 0|(1<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #203 = LIS
{ 204, 2, 1, 14, "LIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo57 }, // Inst #204 = LIS8
{ 205, 3, 1, 33, "LVEBX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #205 = LVEBX
{ 206, 3, 1, 33, "LVEHX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #206 = LVEHX
{ 207, 3, 1, 33, "LVEWX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #207 = LVEWX
{ 208, 3, 1, 33, "LVSL", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #208 = LVSL
{ 209, 3, 1, 33, "LVSR", 0, 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #209 = LVSR
{ 210, 3, 1, 33, "LVX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #210 = LVX
{ 211, 3, 1, 33, "LVXL", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #211 = LVXL
{ 212, 3, 1, 42, "LWA", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #212 = LWA
{ 213, 3, 1, 43, "LWARX", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo46 }, // Inst #213 = LWARX
{ 214, 3, 1, 39, "LWAX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #214 = LWAX
{ 215, 3, 1, 33, "LWBRX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #215 = LWBRX
{ 216, 3, 1, 33, "LWZ", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #216 = LWZ
{ 217, 3, 1, 33, "LWZ8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #217 = LWZ8
{ 218, 4, 2, 33, "LWZU", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo44 }, // Inst #218 = LWZU
{ 219, 4, 2, 33, "LWZU8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo45 }, // Inst #219 = LWZU8
{ 220, 3, 1, 33, "LWZX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #220 = LWZX
{ 221, 3, 1, 33, "LWZX8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #221 = LWZX8
{ 222, 2, 1, 2, "MCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo59 }, // Inst #222 = MCRF
{ 223, 1, 1, 54, "MFCR", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #223 = MFCR
{ 224, 1, 1, 56, "MFCTR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList4, NULL, NULL, OperandInfo60 }, // Inst #224 = MFCTR
{ 225, 1, 1, 56, "MFCTR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList13, NULL, NULL, OperandInfo48 }, // Inst #225 = MFCTR8
{ 226, 1, 1, 15, "MFFS", 0, 0|(1<<1)|(3<<3), ImplicitList10, NULL, NULL, OperandInfo61 }, // Inst #226 = MFFS
{ 227, 1, 1, 56, "MFLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList14, NULL, NULL, OperandInfo60 }, // Inst #227 = MFLR
{ 228, 1, 1, 56, "MFLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), ImplicitList15, NULL, NULL, OperandInfo48 }, // Inst #228 = MFLR8
{ 229, 2, 1, 54, "MFOCRF", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<3), NULL, NULL, NULL, OperandInfo56 }, // Inst #229 = MFOCRF
{ 230, 1, 1, 14, "MFVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #230 = MFVRSAVE
{ 231, 1, 1, 33, "MFVSCR", 0|(1<<TID::MayLoad), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #231 = MFVSCR
{ 232, 2, 0, 3, "MTCRF", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<3), NULL, NULL, NULL, OperandInfo63 }, // Inst #232 = MTCRF
{ 233, 1, 0, 60, "MTCTR", 0, 0|1|(1<<3), NULL, ImplicitList4, Barriers4, OperandInfo60 }, // Inst #233 = MTCTR
{ 234, 1, 0, 60, "MTCTR8", 0, 0|1|(1<<3), NULL, ImplicitList13, Barriers5, OperandInfo48 }, // Inst #234 = MTCTR8
{ 235, 1, 0, 17, "MTFSB0", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #235 = MTFSB0
{ 236, 1, 0, 17, "MTFSB1", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo8 }, // Inst #236 = MTFSB1
{ 237, 4, 1, 17, "MTFSF", 0, 0|(1<<1)|(3<<3), ImplicitList10, ImplicitList10, NULL, OperandInfo64 }, // Inst #237 = MTFSF
{ 238, 1, 0, 60, "MTLR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList14, NULL, OperandInfo60 }, // Inst #238 = MTLR
{ 239, 1, 0, 60, "MTLR8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<3), NULL, ImplicitList15, NULL, OperandInfo48 }, // Inst #239 = MTLR8
{ 240, 1, 0, 14, "MTVRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<1)|(1<<3), NULL, NULL, NULL, OperandInfo60 }, // Inst #240 = MTVRSAVE
{ 241, 1, 0, 33, "MTVSCR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo62 }, // Inst #241 = MTVSCR
{ 242, 3, 1, 20, "MULHD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #242 = MULHD
{ 243, 3, 1, 21, "MULHDU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #243 = MULHDU
{ 244, 3, 1, 20, "MULHW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #244 = MULHW
{ 245, 3, 1, 21, "MULHWU", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #245 = MULHWU
{ 246, 3, 1, 19, "MULLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #246 = MULLD
{ 247, 3, 1, 22, "MULLI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #247 = MULLI
{ 248, 3, 1, 20, "MULLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #248 = MULLW
{ 249, 1, 0, 52, "MovePCtoLR", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList14, NULL, OperandInfo8 }, // Inst #249 = MovePCtoLR
{ 250, 1, 0, 52, "MovePCtoLR8", 0|(1<<TID::UnmodeledSideEffects), 0|(7<<3), NULL, ImplicitList15, NULL, OperandInfo8 }, // Inst #250 = MovePCtoLR8
{ 251, 3, 1, 14, "NAND", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #251 = NAND
{ 252, 3, 1, 14, "NAND8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #252 = NAND8
{ 253, 2, 1, 14, "NEG", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo6 }, // Inst #253 = NEG
{ 254, 2, 1, 14, "NEG8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo7 }, // Inst #254 = NEG8
{ 255, 0, 0, 14, "NOP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, 0 }, // Inst #255 = NOP
{ 256, 3, 1, 14, "NOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #256 = NOR
{ 257, 3, 1, 14, "NOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #257 = NOR8
{ 258, 3, 1, 14, "OR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #258 = OR
{ 259, 3, 1, 14, "OR4To8", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo65 }, // Inst #259 = OR4To8
{ 260, 3, 1, 14, "OR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #260 = OR8
{ 261, 3, 1, 14, "OR8To4", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo66 }, // Inst #261 = OR8To4
{ 262, 3, 1, 14, "ORC", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #262 = ORC
{ 263, 3, 1, 14, "ORC8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #263 = ORC8
{ 264, 3, 1, 14, "ORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #264 = ORI
{ 265, 3, 1, 14, "ORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #265 = ORI8
{ 266, 3, 1, 14, "ORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #266 = ORIS
{ 267, 3, 1, 14, "ORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #267 = ORIS8
{ 268, 4, 1, 25, "RLDCL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo67 }, // Inst #268 = RLDCL
{ 269, 4, 1, 25, "RLDICL", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #269 = RLDICL
{ 270, 4, 1, 25, "RLDICR", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo68 }, // Inst #270 = RLDICR
{ 271, 5, 1, 25, "RLDIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo69 }, // Inst #271 = RLDIMI
{ 272, 6, 1, 24, "RLWIMI", 0|(1<<TID::Commutable)|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, NULL, NULL, OperandInfo70 }, // Inst #272 = RLWIMI
{ 273, 5, 1, 14, "RLWINM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo71 }, // Inst #273 = RLWINM
{ 274, 5, 1, 14, "RLWINMo", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<2)|(1<<3), NULL, ImplicitList3, NULL, OperandInfo71 }, // Inst #274 = RLWINMo
{ 275, 5, 1, 14, "RLWNM", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<3), NULL, NULL, NULL, OperandInfo72 }, // Inst #275 = RLWNM
{ 276, 5, 1, 52, "SELECT_CC_F4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo73 }, // Inst #276 = SELECT_CC_F4
{ 277, 5, 1, 52, "SELECT_CC_F8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo74 }, // Inst #277 = SELECT_CC_F8
{ 278, 5, 1, 52, "SELECT_CC_I4", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo75 }, // Inst #278 = SELECT_CC_I4
{ 279, 5, 1, 52, "SELECT_CC_I8", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo76 }, // Inst #279 = SELECT_CC_I8
{ 280, 5, 1, 52, "SELECT_CC_VRRC", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<1), NULL, NULL, NULL, OperandInfo77 }, // Inst #280 = SELECT_CC_VRRC
{ 281, 3, 1, 25, "SLD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #281 = SLD
{ 282, 3, 1, 14, "SLW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #282 = SLW
{ 283, 3, 0, 52, "SPILL_CR", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo42 }, // Inst #283 = SPILL_CR
{ 284, 3, 1, 25, "SRAD", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo78 }, // Inst #284 = SRAD
{ 285, 3, 1, 25, "SRADI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #285 = SRADI
{ 286, 3, 1, 26, "SRAW", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #286 = SRAW
{ 287, 3, 1, 26, "SRAWI", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #287 = SRAWI
{ 288, 3, 1, 25, "SRD", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo78 }, // Inst #288 = SRD
{ 289, 3, 1, 14, "SRW", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #289 = SRW
{ 290, 3, 0, 33, "STB", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #290 = STB
{ 291, 3, 0, 33, "STB8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #291 = STB8
{ 292, 4, 1, 33, "STBU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #292 = STBU
{ 293, 4, 1, 33, "STBU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #293 = STBU8
{ 294, 3, 0, 33, "STBX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #294 = STBX
{ 295, 3, 0, 33, "STBX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #295 = STBX8
{ 296, 3, 0, 46, "STD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #296 = STD
{ 297, 3, 0, 47, "STDCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo47 }, // Inst #297 = STDCX
{ 298, 4, 1, 46, "STDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #298 = STDU
{ 299, 3, 0, 46, "STDUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #299 = STDUX
{ 300, 3, 0, 46, "STDX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #300 = STDX
{ 301, 3, 0, 46, "STDX_32", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #301 = STDX_32
{ 302, 3, 0, 46, "STD_32", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #302 = STD_32
{ 303, 3, 0, 51, "STFD", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo50 }, // Inst #303 = STFD
{ 304, 4, 1, 33, "STFDU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo81 }, // Inst #304 = STFDU
{ 305, 3, 0, 51, "STFDX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #305 = STFDX
{ 306, 3, 0, 51, "STFIWX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo52 }, // Inst #306 = STFIWX
{ 307, 3, 0, 51, "STFS", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo53 }, // Inst #307 = STFS
{ 308, 4, 1, 33, "STFSU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo82 }, // Inst #308 = STFSU
{ 309, 3, 0, 51, "STFSX", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo55 }, // Inst #309 = STFSX
{ 310, 3, 0, 33, "STH", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #310 = STH
{ 311, 3, 0, 33, "STH8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #311 = STH8
{ 312, 3, 0, 33, "STHBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #312 = STHBRX
{ 313, 4, 1, 33, "STHU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #313 = STHU
{ 314, 4, 1, 33, "STHU8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo80 }, // Inst #314 = STHU8
{ 315, 3, 0, 33, "STHX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #315 = STHX
{ 316, 3, 0, 33, "STHX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #316 = STHX8
{ 317, 3, 0, 33, "STVEBX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #317 = STVEBX
{ 318, 3, 0, 33, "STVEHX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #318 = STVEHX
{ 319, 3, 0, 33, "STVEWX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #319 = STVEWX
{ 320, 3, 0, 33, "STVX", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #320 = STVX
{ 321, 3, 0, 33, "STVXL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo58 }, // Inst #321 = STVXL
{ 322, 3, 0, 33, "STW", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo42 }, // Inst #322 = STW
{ 323, 3, 0, 33, "STW8", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo43 }, // Inst #323 = STW8
{ 324, 3, 0, 33, "STWBRX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #324 = STWBRX
{ 325, 3, 0, 49, "STWCX", 0|(1<<TID::MayStore), 0, NULL, ImplicitList3, NULL, OperandInfo46 }, // Inst #325 = STWCX
{ 326, 4, 1, 33, "STWU", 0|(1<<TID::MayStore), 0|(2<<3), NULL, NULL, NULL, OperandInfo79 }, // Inst #326 = STWU
{ 327, 3, 0, 33, "STWUX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|(2<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #327 = STWUX
{ 328, 3, 0, 33, "STWX", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo46 }, // Inst #328 = STWX
{ 329, 3, 0, 33, "STWX8", 0|(1<<TID::MayStore), 0|(1<<2)|(2<<3), NULL, NULL, NULL, OperandInfo47 }, // Inst #329 = STWX8
{ 330, 3, 1, 14, "SUBF", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #330 = SUBF
{ 331, 3, 1, 14, "SUBF8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #331 = SUBF8
{ 332, 3, 1, 14, "SUBFC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #332 = SUBFC
{ 333, 3, 1, 14, "SUBFC8", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #333 = SUBFC8
{ 334, 3, 1, 14, "SUBFE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #334 = SUBFE
{ 335, 3, 1, 14, "SUBFE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #335 = SUBFE8
{ 336, 3, 1, 14, "SUBFIC", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #336 = SUBFIC
{ 337, 3, 1, 14, "SUBFIC8", 0, 0|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #337 = SUBFIC8
{ 338, 2, 1, 14, "SUBFME", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #338 = SUBFME
{ 339, 2, 1, 14, "SUBFME8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #339 = SUBFME8
{ 340, 2, 1, 14, "SUBFZE", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #340 = SUBFZE
{ 341, 2, 1, 14, "SUBFZE8", 0, 0|(1<<3), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #341 = SUBFZE8
{ 342, 0, 0, 50, "SYNC", 0|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #342 = SYNC
{ 343, 1, 0, 0, "TAILB", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #343 = TAILB
{ 344, 1, 0, 0, "TAILB8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #344 = TAILB8
{ 345, 1, 0, 0, "TAILBA", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #345 = TAILBA
{ 346, 1, 0, 0, "TAILBA8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList10, NULL, NULL, OperandInfo8 }, // Inst #346 = TAILBA8
{ 347, 0, 0, 0, "TAILBCTR", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #347 = TAILBCTR
{ 348, 0, 0, 0, "TAILBCTR8", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(7<<3), ImplicitList7, NULL, NULL, 0 }, // Inst #348 = TAILBCTR8
{ 349, 2, 0, 52, "TCRETURNai", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #349 = TCRETURNai
{ 350, 2, 0, 52, "TCRETURNai8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #350 = TCRETURNai8
{ 351, 2, 0, 52, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #351 = TCRETURNdi
{ 352, 2, 0, 52, "TCRETURNdi8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo9 }, // Inst #352 = TCRETURNdi8
{ 353, 2, 0, 52, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo83 }, // Inst #353 = TCRETURNri
{ 354, 2, 0, 52, "TCRETURNri8", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, ImplicitList10, NULL, NULL, OperandInfo84 }, // Inst #354 = TCRETURNri8
{ 355, 0, 0, 33, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, 0 }, // Inst #355 = TRAP
{ 356, 2, 1, 52, "UPDATE_VRSAVE", 0|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo6 }, // Inst #356 = UPDATE_VRSAVE
{ 357, 3, 1, 67, "VADDCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #357 = VADDCUW
{ 358, 3, 1, 67, "VADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #358 = VADDFP
{ 359, 3, 1, 67, "VADDSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #359 = VADDSBS
{ 360, 3, 1, 67, "VADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #360 = VADDSHS
{ 361, 3, 1, 67, "VADDSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #361 = VADDSWS
{ 362, 3, 1, 70, "VADDUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #362 = VADDUBM
{ 363, 3, 1, 67, "VADDUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #363 = VADDUBS
{ 364, 3, 1, 70, "VADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #364 = VADDUHM
{ 365, 3, 1, 67, "VADDUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #365 = VADDUHS
{ 366, 3, 1, 70, "VADDUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #366 = VADDUWM
{ 367, 3, 1, 67, "VADDUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #367 = VADDUWS
{ 368, 3, 1, 67, "VAND", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #368 = VAND
{ 369, 3, 1, 67, "VANDC", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #369 = VANDC
{ 370, 3, 1, 67, "VAVGSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #370 = VAVGSB
{ 371, 3, 1, 67, "VAVGSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #371 = VAVGSH
{ 372, 3, 1, 67, "VAVGSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #372 = VAVGSW
{ 373, 3, 1, 67, "VAVGUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #373 = VAVGUB
{ 374, 3, 1, 67, "VAVGUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #374 = VAVGUH
{ 375, 3, 1, 67, "VAVGUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #375 = VAVGUW
{ 376, 3, 1, 67, "VCFSX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #376 = VCFSX
{ 377, 3, 1, 67, "VCFUX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #377 = VCFUX
{ 378, 3, 1, 68, "VCMPBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #378 = VCMPBFP
{ 379, 3, 1, 68, "VCMPBFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #379 = VCMPBFPo
{ 380, 3, 1, 68, "VCMPEQFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #380 = VCMPEQFP
{ 381, 3, 1, 68, "VCMPEQFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #381 = VCMPEQFPo
{ 382, 3, 1, 68, "VCMPEQUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #382 = VCMPEQUB
{ 383, 3, 1, 68, "VCMPEQUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #383 = VCMPEQUBo
{ 384, 3, 1, 68, "VCMPEQUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #384 = VCMPEQUH
{ 385, 3, 1, 68, "VCMPEQUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #385 = VCMPEQUHo
{ 386, 3, 1, 68, "VCMPEQUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #386 = VCMPEQUW
{ 387, 3, 1, 68, "VCMPEQUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #387 = VCMPEQUWo
{ 388, 3, 1, 68, "VCMPGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #388 = VCMPGEFP
{ 389, 3, 1, 68, "VCMPGEFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #389 = VCMPGEFPo
{ 390, 3, 1, 68, "VCMPGTFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #390 = VCMPGTFP
{ 391, 3, 1, 68, "VCMPGTFPo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #391 = VCMPGTFPo
{ 392, 3, 1, 68, "VCMPGTSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #392 = VCMPGTSB
{ 393, 3, 1, 68, "VCMPGTSBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #393 = VCMPGTSBo
{ 394, 3, 1, 68, "VCMPGTSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #394 = VCMPGTSH
{ 395, 3, 1, 68, "VCMPGTSHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #395 = VCMPGTSHo
{ 396, 3, 1, 68, "VCMPGTSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #396 = VCMPGTSW
{ 397, 3, 1, 68, "VCMPGTSWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #397 = VCMPGTSWo
{ 398, 3, 1, 68, "VCMPGTUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #398 = VCMPGTUB
{ 399, 3, 1, 68, "VCMPGTUBo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #399 = VCMPGTUBo
{ 400, 3, 1, 68, "VCMPGTUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #400 = VCMPGTUH
{ 401, 3, 1, 68, "VCMPGTUHo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #401 = VCMPGTUHo
{ 402, 3, 1, 68, "VCMPGTUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #402 = VCMPGTUW
{ 403, 3, 1, 68, "VCMPGTUWo", 0, 0|(5<<3), NULL, ImplicitList16, NULL, OperandInfo85 }, // Inst #403 = VCMPGTUWo
{ 404, 3, 1, 67, "VCTSXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #404 = VCTSXS
{ 405, 3, 1, 67, "VCTUXS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #405 = VCTUXS
{ 406, 2, 1, 67, "VEXPTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #406 = VEXPTEFP
{ 407, 2, 1, 67, "VLOGEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #407 = VLOGEFP
{ 408, 4, 1, 67, "VMADDFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #408 = VMADDFP
{ 409, 3, 1, 67, "VMAXFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #409 = VMAXFP
{ 410, 3, 1, 67, "VMAXSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #410 = VMAXSB
{ 411, 3, 1, 67, "VMAXSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #411 = VMAXSH
{ 412, 3, 1, 67, "VMAXSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #412 = VMAXSW
{ 413, 3, 1, 67, "VMAXUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #413 = VMAXUB
{ 414, 3, 1, 67, "VMAXUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #414 = VMAXUH
{ 415, 3, 1, 67, "VMAXUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #415 = VMAXUW
{ 416, 4, 1, 67, "VMHADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #416 = VMHADDSHS
{ 417, 4, 1, 67, "VMHRADDSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #417 = VMHRADDSHS
{ 418, 3, 1, 67, "VMINFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #418 = VMINFP
{ 419, 3, 1, 67, "VMINSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #419 = VMINSB
{ 420, 3, 1, 67, "VMINSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #420 = VMINSH
{ 421, 3, 1, 67, "VMINSW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #421 = VMINSW
{ 422, 3, 1, 67, "VMINUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #422 = VMINUB
{ 423, 3, 1, 67, "VMINUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #423 = VMINUH
{ 424, 3, 1, 67, "VMINUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #424 = VMINUW
{ 425, 4, 1, 67, "VMLADDUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #425 = VMLADDUHM
{ 426, 3, 1, 67, "VMRGHB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #426 = VMRGHB
{ 427, 3, 1, 67, "VMRGHH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #427 = VMRGHH
{ 428, 3, 1, 67, "VMRGHW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #428 = VMRGHW
{ 429, 3, 1, 67, "VMRGLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #429 = VMRGLB
{ 430, 3, 1, 67, "VMRGLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #430 = VMRGLH
{ 431, 3, 1, 67, "VMRGLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #431 = VMRGLW
{ 432, 4, 1, 67, "VMSUMMBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #432 = VMSUMMBM
{ 433, 4, 1, 67, "VMSUMSHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #433 = VMSUMSHM
{ 434, 4, 1, 67, "VMSUMSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #434 = VMSUMSHS
{ 435, 4, 1, 67, "VMSUMUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #435 = VMSUMUBM
{ 436, 4, 1, 67, "VMSUMUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #436 = VMSUMUHM
{ 437, 4, 1, 67, "VMSUMUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #437 = VMSUMUHS
{ 438, 3, 1, 67, "VMULESB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #438 = VMULESB
{ 439, 3, 1, 67, "VMULESH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #439 = VMULESH
{ 440, 3, 1, 67, "VMULEUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #440 = VMULEUB
{ 441, 3, 1, 67, "VMULEUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #441 = VMULEUH
{ 442, 3, 1, 67, "VMULOSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #442 = VMULOSB
{ 443, 3, 1, 67, "VMULOSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #443 = VMULOSH
{ 444, 3, 1, 67, "VMULOUB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #444 = VMULOUB
{ 445, 3, 1, 67, "VMULOUH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #445 = VMULOUH
{ 446, 4, 1, 67, "VNMSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #446 = VNMSUBFP
{ 447, 3, 1, 67, "VNOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #447 = VNOR
{ 448, 3, 1, 67, "VOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #448 = VOR
{ 449, 4, 1, 67, "VPERM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #449 = VPERM
{ 450, 3, 1, 67, "VPKPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #450 = VPKPX
{ 451, 3, 1, 67, "VPKSHSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #451 = VPKSHSS
{ 452, 3, 1, 67, "VPKSHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #452 = VPKSHUS
{ 453, 3, 1, 67, "VPKSWSS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #453 = VPKSWSS
{ 454, 3, 1, 67, "VPKSWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #454 = VPKSWUS
{ 455, 3, 1, 67, "VPKUHUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #455 = VPKUHUM
{ 456, 3, 1, 67, "VPKUHUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #456 = VPKUHUS
{ 457, 3, 1, 67, "VPKUWUM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #457 = VPKUWUM
{ 458, 3, 1, 67, "VPKUWUS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #458 = VPKUWUS
{ 459, 2, 1, 67, "VREFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #459 = VREFP
{ 460, 2, 1, 67, "VRFIM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #460 = VRFIM
{ 461, 2, 1, 67, "VRFIN", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #461 = VRFIN
{ 462, 2, 1, 67, "VRFIP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #462 = VRFIP
{ 463, 2, 1, 67, "VRFIZ", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #463 = VRFIZ
{ 464, 3, 1, 67, "VRLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #464 = VRLB
{ 465, 3, 1, 67, "VRLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #465 = VRLH
{ 466, 3, 1, 67, "VRLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #466 = VRLW
{ 467, 2, 1, 67, "VRSQRTEFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #467 = VRSQRTEFP
{ 468, 4, 1, 67, "VSEL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo88 }, // Inst #468 = VSEL
{ 469, 3, 1, 67, "VSL", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #469 = VSL
{ 470, 3, 1, 67, "VSLB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #470 = VSLB
{ 471, 4, 1, 67, "VSLDOI", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo89 }, // Inst #471 = VSLDOI
{ 472, 3, 1, 67, "VSLH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #472 = VSLH
{ 473, 3, 1, 67, "VSLO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #473 = VSLO
{ 474, 3, 1, 67, "VSLW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #474 = VSLW
{ 475, 3, 1, 71, "VSPLTB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #475 = VSPLTB
{ 476, 3, 1, 71, "VSPLTH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #476 = VSPLTH
{ 477, 2, 1, 71, "VSPLTISB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #477 = VSPLTISB
{ 478, 2, 1, 71, "VSPLTISH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #478 = VSPLTISH
{ 479, 2, 1, 71, "VSPLTISW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo90 }, // Inst #479 = VSPLTISW
{ 480, 3, 1, 71, "VSPLTW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo86 }, // Inst #480 = VSPLTW
{ 481, 3, 1, 67, "VSR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #481 = VSR
{ 482, 3, 1, 67, "VSRAB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #482 = VSRAB
{ 483, 3, 1, 67, "VSRAH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #483 = VSRAH
{ 484, 3, 1, 67, "VSRAW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #484 = VSRAW
{ 485, 3, 1, 67, "VSRB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #485 = VSRB
{ 486, 3, 1, 67, "VSRH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #486 = VSRH
{ 487, 3, 1, 67, "VSRO", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #487 = VSRO
{ 488, 3, 1, 67, "VSRW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #488 = VSRW
{ 489, 3, 1, 67, "VSUBCUW", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #489 = VSUBCUW
{ 490, 3, 1, 70, "VSUBFP", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #490 = VSUBFP
{ 491, 3, 1, 67, "VSUBSBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #491 = VSUBSBS
{ 492, 3, 1, 67, "VSUBSHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #492 = VSUBSHS
{ 493, 3, 1, 67, "VSUBSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #493 = VSUBSWS
{ 494, 3, 1, 70, "VSUBUBM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #494 = VSUBUBM
{ 495, 3, 1, 67, "VSUBUBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #495 = VSUBUBS
{ 496, 3, 1, 70, "VSUBUHM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #496 = VSUBUHM
{ 497, 3, 1, 67, "VSUBUHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #497 = VSUBUHS
{ 498, 3, 1, 70, "VSUBUWM", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #498 = VSUBUWM
{ 499, 3, 1, 67, "VSUBUWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #499 = VSUBUWS
{ 500, 3, 1, 67, "VSUM2SWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #500 = VSUM2SWS
{ 501, 3, 1, 67, "VSUM4SBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #501 = VSUM4SBS
{ 502, 3, 1, 67, "VSUM4SHS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #502 = VSUM4SHS
{ 503, 3, 1, 67, "VSUM4UBS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #503 = VSUM4UBS
{ 504, 3, 1, 67, "VSUMSWS", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #504 = VSUMSWS
{ 505, 2, 1, 67, "VUPKHPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #505 = VUPKHPX
{ 506, 2, 1, 67, "VUPKHSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #506 = VUPKHSB
{ 507, 2, 1, 67, "VUPKHSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #507 = VUPKHSH
{ 508, 2, 1, 67, "VUPKLPX", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #508 = VUPKLPX
{ 509, 2, 1, 67, "VUPKLSB", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #509 = VUPKLSB
{ 510, 2, 1, 67, "VUPKLSH", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo87 }, // Inst #510 = VUPKLSH
{ 511, 3, 1, 67, "VXOR", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo85 }, // Inst #511 = VXOR
{ 512, 1, 1, 67, "V_SET0", 0, 0|(5<<3), NULL, NULL, NULL, OperandInfo62 }, // Inst #512 = V_SET0
{ 513, 3, 1, 14, "XOR", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #513 = XOR
{ 514, 3, 1, 14, "XOR8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #514 = XOR8
{ 515, 3, 1, 14, "XORI", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #515 = XORI
{ 516, 3, 1, 14, "XORI8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #516 = XORI8
{ 517, 3, 1, 14, "XORIS", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo4 }, // Inst #517 = XORIS
{ 518, 3, 1, 14, "XORIS8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo5 }, // Inst #518 = XORIS8
};
} // End llvm namespace

748
libclamav/c++/PPCGenInstrNames.inc
Unescape View File

@ -157,381 +157,379 @@ namespace PPC {
FDIVS = 144,
FMADD = 145,
FMADDS = 146,
FMRD = 147,
FMRS = 148,
FMRSD = 149,
FMSUB = 150,
FMSUBS = 151,
FMUL = 152,
FMULS = 153,
FNABSD = 154,
FNABSS = 155,
FNEGD = 156,
FNEGS = 157,
FNMADD = 158,
FNMADDS = 159,
FNMSUB = 160,
FNMSUBS = 161,
FRSP = 162,
FSELD = 163,
FSELS = 164,
FSQRT = 165,
FSQRTS = 166,
FSUB = 167,
FSUBS = 168,
LA = 169,
LBZ = 170,
LBZ8 = 171,
LBZU = 172,
LBZU8 = 173,
LBZX = 174,
LBZX8 = 175,
LD = 176,
LDARX = 177,
LDU = 178,
LDX = 179,
LDinto_toc = 180,
LDtoc = 181,
LDtoc_restore = 182,
LFD = 183,
LFDU = 184,
LFDX = 185,
LFS = 186,
LFSU = 187,
LFSX = 188,
LHA = 189,
LHA8 = 190,
LHAU = 191,
LHAU8 = 192,
LHAX = 193,
LHAX8 = 194,
LHBRX = 195,
LHZ = 196,
LHZ8 = 197,
LHZU = 198,
LHZU8 = 199,
LHZX = 200,
LHZX8 = 201,
LI = 202,
LI8 = 203,
LIS = 204,
LIS8 = 205,
LVEBX = 206,
LVEHX = 207,
LVEWX = 208,
LVSL = 209,
LVSR = 210,
LVX = 211,
LVXL = 212,
LWA = 213,
LWARX = 214,
LWAX = 215,
LWBRX = 216,
LWZ = 217,
LWZ8 = 218,
LWZU = 219,
LWZU8 = 220,
LWZX = 221,
LWZX8 = 222,
MCRF = 223,
MFCR = 224,
MFCTR = 225,
MFCTR8 = 226,
MFFS = 227,
MFLR = 228,
MFLR8 = 229,
MFOCRF = 230,
MFVRSAVE = 231,
MFVSCR = 232,
MTCRF = 233,
MTCTR = 234,
MTCTR8 = 235,
MTFSB0 = 236,
MTFSB1 = 237,
MTFSF = 238,
MTLR = 239,
MTLR8 = 240,
MTVRSAVE = 241,
MTVSCR = 242,
MULHD = 243,
MULHDU = 244,
MULHW = 245,
MULHWU = 246,
MULLD = 247,
MULLI = 248,
MULLW = 249,
MovePCtoLR = 250,
MovePCtoLR8 = 251,
NAND = 252,
NAND8 = 253,
NEG = 254,
NEG8 = 255,
NOP = 256,
NOR = 257,
NOR8 = 258,
OR = 259,
OR4To8 = 260,
OR8 = 261,
OR8To4 = 262,
ORC = 263,
ORC8 = 264,
ORI = 265,
ORI8 = 266,
ORIS = 267,
ORIS8 = 268,
RLDCL = 269,
RLDICL = 270,
RLDICR = 271,
RLDIMI = 272,
RLWIMI = 273,
RLWINM = 274,
RLWINMo = 275,
RLWNM = 276,
SELECT_CC_F4 = 277,
SELECT_CC_F8 = 278,
SELECT_CC_I4 = 279,
SELECT_CC_I8 = 280,
SELECT_CC_VRRC = 281,
SLD = 282,
SLW = 283,
SPILL_CR = 284,
SRAD = 285,
SRADI = 286,
SRAW = 287,
SRAWI = 288,
SRD = 289,
SRW = 290,
STB = 291,
STB8 = 292,
STBU = 293,
STBU8 = 294,
STBX = 295,
STBX8 = 296,
STD = 297,
STDCX = 298,
STDU = 299,
STDUX = 300,
STDX = 301,
STDX_32 = 302,
STD_32 = 303,
STFD = 304,
STFDU = 305,
STFDX = 306,
STFIWX = 307,
STFS = 308,
STFSU = 309,
STFSX = 310,
STH = 311,
STH8 = 312,
STHBRX = 313,
STHU = 314,
STHU8 = 315,
STHX = 316,
STHX8 = 317,
STVEBX = 318,
STVEHX = 319,
STVEWX = 320,
STVX = 321,
STVXL = 322,
STW = 323,
STW8 = 324,
STWBRX = 325,
STWCX = 326,
STWU = 327,
STWU8 = 328,
STWUX = 329,
STWX = 330,
STWX8 = 331,
SUBF = 332,
SUBF8 = 333,
SUBFC = 334,
SUBFC8 = 335,
SUBFE = 336,
SUBFE8 = 337,
SUBFIC = 338,
SUBFIC8 = 339,
SUBFME = 340,
SUBFME8 = 341,
SUBFZE = 342,
SUBFZE8 = 343,
SYNC = 344,
TAILB = 345,
TAILB8 = 346,
TAILBA = 347,
TAILBA8 = 348,
TAILBCTR = 349,
TAILBCTR8 = 350,
TCRETURNai = 351,
TCRETURNai8 = 352,
TCRETURNdi = 353,
TCRETURNdi8 = 354,
TCRETURNri = 355,
TCRETURNri8 = 356,
TRAP = 357,
UPDATE_VRSAVE = 358,
VADDCUW = 359,
VADDFP = 360,
VADDSBS = 361,
VADDSHS = 362,
VADDSWS = 363,
VADDUBM = 364,
VADDUBS = 365,
VADDUHM = 366,
VADDUHS = 367,
VADDUWM = 368,
VADDUWS = 369,
VAND = 370,
VANDC = 371,
VAVGSB = 372,
VAVGSH = 373,
VAVGSW = 374,
VAVGUB = 375,
VAVGUH = 376,
VAVGUW = 377,
VCFSX = 378,
VCFUX = 379,
VCMPBFP = 380,
VCMPBFPo = 381,
VCMPEQFP = 382,
VCMPEQFPo = 383,
VCMPEQUB = 384,
VCMPEQUBo = 385,
VCMPEQUH = 386,
VCMPEQUHo = 387,
VCMPEQUW = 388,
VCMPEQUWo = 389,
VCMPGEFP = 390,
VCMPGEFPo = 391,
VCMPGTFP = 392,
VCMPGTFPo = 393,
VCMPGTSB = 394,
VCMPGTSBo = 395,
VCMPGTSH = 396,
VCMPGTSHo = 397,
VCMPGTSW = 398,
VCMPGTSWo = 399,
VCMPGTUB = 400,
VCMPGTUBo = 401,
VCMPGTUH = 402,
VCMPGTUHo = 403,
VCMPGTUW = 404,
VCMPGTUWo = 405,
VCTSXS = 406,
VCTUXS = 407,
VEXPTEFP = 408,
VLOGEFP = 409,
VMADDFP = 410,
VMAXFP = 411,
VMAXSB = 412,
VMAXSH = 413,
VMAXSW = 414,
VMAXUB = 415,
VMAXUH = 416,
VMAXUW = 417,
VMHADDSHS = 418,
VMHRADDSHS = 419,
VMINFP = 420,
VMINSB = 421,
VMINSH = 422,
VMINSW = 423,
VMINUB = 424,
VMINUH = 425,
VMINUW = 426,
VMLADDUHM = 427,
VMRGHB = 428,
VMRGHH = 429,
VMRGHW = 430,
VMRGLB = 431,
VMRGLH = 432,
VMRGLW = 433,
VMSUMMBM = 434,
VMSUMSHM = 435,
VMSUMSHS = 436,
VMSUMUBM = 437,
VMSUMUHM = 438,
VMSUMUHS = 439,
VMULESB = 440,
VMULESH = 441,
VMULEUB = 442,
VMULEUH = 443,
VMULOSB = 444,
VMULOSH = 445,
VMULOUB = 446,
VMULOUH = 447,
VNMSUBFP = 448,
VNOR = 449,
VOR = 450,
VPERM = 451,
VPKPX = 452,
VPKSHSS = 453,
VPKSHUS = 454,
VPKSWSS = 455,
VPKSWUS = 456,
VPKUHUM = 457,
VPKUHUS = 458,
VPKUWUM = 459,
VPKUWUS = 460,
VREFP = 461,
VRFIM = 462,
VRFIN = 463,
VRFIP = 464,
VRFIZ = 465,
VRLB = 466,
VRLH = 467,
VRLW = 468,
VRSQRTEFP = 469,
VSEL = 470,
VSL = 471,
VSLB = 472,
VSLDOI = 473,
VSLH = 474,
VSLO = 475,
VSLW = 476,
VSPLTB = 477,
VSPLTH = 478,
VSPLTISB = 479,
VSPLTISH = 480,
VSPLTISW = 481,
VSPLTW = 482,
VSR = 483,
VSRAB = 484,
VSRAH = 485,
VSRAW = 486,
VSRB = 487,
VSRH = 488,
VSRO = 489,
VSRW = 490,
VSUBCUW = 491,
VSUBFP = 492,
VSUBSBS = 493,
VSUBSHS = 494,
VSUBSWS = 495,
VSUBUBM = 496,
VSUBUBS = 497,
VSUBUHM = 498,
VSUBUHS = 499,
VSUBUWM = 500,
VSUBUWS = 501,
VSUM2SWS = 502,
VSUM4SBS = 503,
VSUM4SHS = 504,
VSUM4UBS = 505,
VSUMSWS = 506,
VUPKHPX = 507,
VUPKHSB = 508,
VUPKHSH = 509,
VUPKLPX = 510,
VUPKLSB = 511,
VUPKLSH = 512,
VXOR = 513,
V_SET0 = 514,
XOR = 515,
XOR8 = 516,
XORI = 517,
XORI8 = 518,
XORIS = 519,
XORIS8 = 520,
INSTRUCTION_LIST_END = 521
FMR = 147,
FMRSD = 148,
FMSUB = 149,
FMSUBS = 150,
FMUL = 151,
FMULS = 152,
FNABSD = 153,
FNABSS = 154,
FNEGD = 155,
FNEGS = 156,
FNMADD = 157,
FNMADDS = 158,
FNMSUB = 159,
FNMSUBS = 160,
FRSP = 161,
FSELD = 162,
FSELS = 163,
FSQRT = 164,
FSQRTS = 165,
FSUB = 166,
FSUBS = 167,
LA = 168,
LBZ = 169,
LBZ8 = 170,
LBZU = 171,
LBZU8 = 172,
LBZX = 173,
LBZX8 = 174,
LD = 175,
LDARX = 176,
LDU = 177,
LDX = 178,
LDinto_toc = 179,
LDtoc = 180,
LDtoc_restore = 181,
LFD = 182,
LFDU = 183,
LFDX = 184,
LFS = 185,
LFSU = 186,
LFSX = 187,
LHA = 188,
LHA8 = 189,
LHAU = 190,
LHAU8 = 191,
LHAX = 192,
LHAX8 = 193,
LHBRX = 194,
LHZ = 195,
LHZ8 = 196,
LHZU = 197,
LHZU8 = 198,
LHZX = 199,
LHZX8 = 200,
LI = 201,
LI8 = 202,
LIS = 203,
LIS8 = 204,
LVEBX = 205,
LVEHX = 206,
LVEWX = 207,
LVSL = 208,
LVSR = 209,
LVX = 210,
LVXL = 211,
LWA = 212,
LWARX = 213,
LWAX = 214,
LWBRX = 215,
LWZ = 216,
LWZ8 = 217,
LWZU = 218,
LWZU8 = 219,
LWZX = 220,
LWZX8 = 221,
MCRF = 222,
MFCR = 223,
MFCTR = 224,
MFCTR8 = 225,
MFFS = 226,
MFLR = 227,
MFLR8 = 228,
MFOCRF = 229,
MFVRSAVE = 230,
MFVSCR = 231,
MTCRF = 232,
MTCTR = 233,
MTCTR8 = 234,
MTFSB0 = 235,
MTFSB1 = 236,
MTFSF = 237,
MTLR = 238,
MTLR8 = 239,
MTVRSAVE = 240,
MTVSCR = 241,
MULHD = 242,
MULHDU = 243,
MULHW = 244,
MULHWU = 245,
MULLD = 246,
MULLI = 247,
MULLW = 248,
MovePCtoLR = 249,
MovePCtoLR8 = 250,
NAND = 251,
NAND8 = 252,
NEG = 253,
NEG8 = 254,
NOP = 255,
NOR = 256,
NOR8 = 257,
OR = 258,
OR4To8 = 259,
OR8 = 260,
OR8To4 = 261,
ORC = 262,
ORC8 = 263,
ORI = 264,
ORI8 = 265,
ORIS = 266,
ORIS8 = 267,
RLDCL = 268,
RLDICL = 269,
RLDICR = 270,
RLDIMI = 271,
RLWIMI = 272,
RLWINM = 273,
RLWINMo = 274,
RLWNM = 275,
SELECT_CC_F4 = 276,
SELECT_CC_F8 = 277,
SELECT_CC_I4 = 278,
SELECT_CC_I8 = 279,
SELECT_CC_VRRC = 280,
SLD = 281,
SLW = 282,
SPILL_CR = 283,
SRAD = 284,
SRADI = 285,
SRAW = 286,
SRAWI = 287,
SRD = 288,
SRW = 289,
STB = 290,
STB8 = 291,
STBU = 292,
STBU8 = 293,
STBX = 294,
STBX8 = 295,
STD = 296,
STDCX = 297,
STDU = 298,
STDUX = 299,
STDX = 300,
STDX_32 = 301,
STD_32 = 302,
STFD = 303,
STFDU = 304,
STFDX = 305,
STFIWX = 306,
STFS = 307,
STFSU = 308,
STFSX = 309,
STH = 310,
STH8 = 311,
STHBRX = 312,
STHU = 313,
STHU8 = 314,
STHX = 315,
STHX8 = 316,
STVEBX = 317,
STVEHX = 318,
STVEWX = 319,
STVX = 320,
STVXL = 321,
STW = 322,
STW8 = 323,
STWBRX = 324,
STWCX = 325,
STWU = 326,
STWUX = 327,
STWX = 328,
STWX8 = 329,
SUBF = 330,
SUBF8 = 331,
SUBFC = 332,
SUBFC8 = 333,
SUBFE = 334,
SUBFE8 = 335,
SUBFIC = 336,
SUBFIC8 = 337,
SUBFME = 338,
SUBFME8 = 339,
SUBFZE = 340,
SUBFZE8 = 341,
SYNC = 342,
TAILB = 343,
TAILB8 = 344,
TAILBA = 345,
TAILBA8 = 346,
TAILBCTR = 347,
TAILBCTR8 = 348,
TCRETURNai = 349,
TCRETURNai8 = 350,
TCRETURNdi = 351,
TCRETURNdi8 = 352,
TCRETURNri = 353,
TCRETURNri8 = 354,
TRAP = 355,
UPDATE_VRSAVE = 356,
VADDCUW = 357,
VADDFP = 358,
VADDSBS = 359,
VADDSHS = 360,
VADDSWS = 361,
VADDUBM = 362,
VADDUBS = 363,
VADDUHM = 364,
VADDUHS = 365,
VADDUWM = 366,
VADDUWS = 367,
VAND = 368,
VANDC = 369,
VAVGSB = 370,
VAVGSH = 371,
VAVGSW = 372,
VAVGUB = 373,
VAVGUH = 374,
VAVGUW = 375,
VCFSX = 376,
VCFUX = 377,
VCMPBFP = 378,
VCMPBFPo = 379,
VCMPEQFP = 380,
VCMPEQFPo = 381,
VCMPEQUB = 382,
VCMPEQUBo = 383,
VCMPEQUH = 384,
VCMPEQUHo = 385,
VCMPEQUW = 386,
VCMPEQUWo = 387,
VCMPGEFP = 388,
VCMPGEFPo = 389,
VCMPGTFP = 390,
VCMPGTFPo = 391,
VCMPGTSB = 392,
VCMPGTSBo = 393,
VCMPGTSH = 394,
VCMPGTSHo = 395,
VCMPGTSW = 396,
VCMPGTSWo = 397,
VCMPGTUB = 398,
VCMPGTUBo = 399,
VCMPGTUH = 400,
VCMPGTUHo = 401,
VCMPGTUW = 402,
VCMPGTUWo = 403,
VCTSXS = 404,
VCTUXS = 405,
VEXPTEFP = 406,
VLOGEFP = 407,
VMADDFP = 408,
VMAXFP = 409,
VMAXSB = 410,
VMAXSH = 411,
VMAXSW = 412,
VMAXUB = 413,
VMAXUH = 414,
VMAXUW = 415,
VMHADDSHS = 416,
VMHRADDSHS = 417,
VMINFP = 418,
VMINSB = 419,
VMINSH = 420,
VMINSW = 421,
VMINUB = 422,
VMINUH = 423,
VMINUW = 424,
VMLADDUHM = 425,
VMRGHB = 426,
VMRGHH = 427,
VMRGHW = 428,
VMRGLB = 429,
VMRGLH = 430,
VMRGLW = 431,
VMSUMMBM = 432,
VMSUMSHM = 433,
VMSUMSHS = 434,
VMSUMUBM = 435,
VMSUMUHM = 436,
VMSUMUHS = 437,
VMULESB = 438,
VMULESH = 439,
VMULEUB = 440,
VMULEUH = 441,
VMULOSB = 442,
VMULOSH = 443,
VMULOUB = 444,
VMULOUH = 445,
VNMSUBFP = 446,
VNOR = 447,
VOR = 448,
VPERM = 449,
VPKPX = 450,
VPKSHSS = 451,
VPKSHUS = 452,
VPKSWSS = 453,
VPKSWUS = 454,
VPKUHUM = 455,
VPKUHUS = 456,
VPKUWUM = 457,
VPKUWUS = 458,
VREFP = 459,
VRFIM = 460,
VRFIN = 461,
VRFIP = 462,
VRFIZ = 463,
VRLB = 464,
VRLH = 465,
VRLW = 466,
VRSQRTEFP = 467,
VSEL = 468,
VSL = 469,
VSLB = 470,
VSLDOI = 471,
VSLH = 472,
VSLO = 473,
VSLW = 474,
VSPLTB = 475,
VSPLTH = 476,
VSPLTISB = 477,
VSPLTISH = 478,
VSPLTISW = 479,
VSPLTW = 480,
VSR = 481,
VSRAB = 482,
VSRAH = 483,
VSRAW = 484,
VSRB = 485,
VSRH = 486,
VSRO = 487,
VSRW = 488,
VSUBCUW = 489,
VSUBFP = 490,
VSUBSBS = 491,
VSUBSHS = 492,
VSUBSWS = 493,
VSUBUBM = 494,
VSUBUBS = 495,
VSUBUHM = 496,
VSUBUHS = 497,
VSUBUWM = 498,
VSUBUWS = 499,
VSUM2SWS = 500,
VSUM4SBS = 501,
VSUM4SHS = 502,
VSUM4UBS = 503,
VSUMSWS = 504,
VUPKHPX = 505,
VUPKHSB = 506,
VUPKHSH = 507,
VUPKLPX = 508,
VUPKLSB = 509,
VUPKLSH = 510,
VXOR = 511,
V_SET0 = 512,
XOR = 513,
XOR8 = 514,
XORI = 515,
XORI8 = 516,
XORIS = 517,
XORIS8 = 518,
INSTRUCTION_LIST_END = 519
};
}
} // End llvm namespace

12
libclamav/c++/PPCGenRegisterInfo.inc
Unescape View File

@ -372,10 +372,8 @@ F8RCClass::F8RCClass() : TargetRegisterClass(F8RCRegClassID, "F8RC", F8RCVTs, F
G8RCClass::iterator
G8RCClass::allocation_order_begin(const MachineFunction &MF) const {
// 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
return begin()+1;
return begin();
// Darwin: r2 is reserved for CR save/restore sequence.
return begin()+1;
}
G8RCClass::iterator
G8RCClass::allocation_order_end(const MachineFunction &MF) const {
@ -391,10 +389,8 @@ G8RCClass::G8RCClass() : TargetRegisterClass(G8RCRegClassID, "G8RC", G8RCVTs, G
GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
// 32-bit SVR4 ABI: r2 is reserved for the OS.
// 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
return begin()+1;
return begin();
// Darwin: R2 is reserved for CR save/restore sequence.
return begin()+1;
}
GPRCClass::iterator
GPRCClass::allocation_order_end(const MachineFunction &MF) const {

24
libclamav/c++/X86GenAsmMatcher.inc
Unescape View File

@ -6293,7 +6293,7 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
unsigned Opcode;
ConversionKind ConvertFn;
MatchClassKind Classes[5];
} MatchTable[2049] = {
} MatchTable[2037] = {
{ X86::CBW, Convert, { MCK_cbtw } },
{ X86::CLC, Convert, { MCK_clc } },
{ X86::CLD, Convert, { MCK_cld } },
@ -7364,9 +7364,11 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
{ X86::MOVLPSrm, Convert__Reg1_2__Tie0__Mem5_1, { MCK_movlps, MCK_Mem, MCK_FR32 } },
{ X86::MOVMSKPDrr, Convert__Reg1_2__Reg1_1, { MCK_movmskpd, MCK_FR32, MCK_GR32 } },
{ X86::MOVMSKPSrr, Convert__Reg1_2__Reg1_1, { MCK_movmskps, MCK_FR32, MCK_GR32 } },
{ X86::MOVNTDQ_64mr, Convert__Mem5_2__Reg1_1, { MCK_movntdq, MCK_FR32, MCK_Mem } },
{ X86::MOVNTDQmr, Convert__Mem5_2__Reg1_1, { MCK_movntdq, MCK_FR32, MCK_Mem } },
{ X86::MOVNTDQArm, Convert__Reg1_2__Mem5_1, { MCK_movntdqa, MCK_Mem, MCK_FR32 } },
{ X86::MOVNTImr, Convert__Mem5_2__Reg1_1, { MCK_movnti, MCK_GR32, MCK_Mem } },
{ X86::MOVNTI_64mr, Convert__Mem5_2__Reg1_1, { MCK_movnti, MCK_GR64, MCK_Mem } },
{ X86::MOVNTPDmr, Convert__Mem5_2__Reg1_1, { MCK_movntpd, MCK_FR32, MCK_Mem } },
{ X86::MOVNTPSmr, Convert__Mem5_2__Reg1_1, { MCK_movntps, MCK_FR32, MCK_Mem } },
{ X86::MMX_MOVNTQmr, Convert__Mem5_2__Reg1_1, { MCK_movntq, MCK_VR64, MCK_Mem } },
@ -7411,32 +7413,18 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
{ X86::MOVSX64rm8, Convert__Reg1_2__Mem5_1, { MCK_movsbq, MCK_Mem, MCK_GR64 } },
{ X86::MOVSX16rr8W, Convert__Reg1_2__Reg1_1, { MCK_movsbw, MCK_GR8, MCK_GR16 } },
{ X86::MOVSX16rm8W, Convert__Reg1_2__Mem5_1, { MCK_movsbw, MCK_Mem, MCK_GR16 } },
{ X86::MOVLPDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
{ X86::MOVLSD2PDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
{ X86::MOVPD2SDrr, Convert__Reg1_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
{ X86::MOVSD2PDrr, Convert__Reg1_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
{ X86::MOVSDrr, Convert__Reg1_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
{ X86::MOVPD2SDmr, Convert__Mem5_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
{ X86::MOVSDrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movsd, MCK_FR32, MCK_FR32 } },
{ X86::MOVSDmr, Convert__Mem5_2__Reg1_1, { MCK_movsd, MCK_FR32, MCK_Mem } },
{ X86::MOVSD2PDrm, Convert__Reg1_2__Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
{ X86::MOVSDrm, Convert__Reg1_2__Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
{ X86::MOVZSD2PDrm, Convert__Reg1_2__Mem5_1, { MCK_movsd, MCK_Mem, MCK_FR32 } },
{ X86::MOVSHDUPrr, Convert__Reg1_2__Reg1_1, { MCK_movshdup, MCK_FR32, MCK_FR32 } },
{ X86::MOVSHDUPrm, Convert__Reg1_2__Mem5_1, { MCK_movshdup, MCK_Mem, MCK_FR32 } },
{ X86::MOVSLDUPrr, Convert__Reg1_2__Reg1_1, { MCK_movsldup, MCK_FR32, MCK_FR32 } },
{ X86::MOVSLDUPrm, Convert__Reg1_2__Mem5_1, { MCK_movsldup, MCK_Mem, MCK_FR32 } },
{ X86::MOVSX64rr32, Convert__Reg1_2__Reg1_1, { MCK_movslq, MCK_GR32, MCK_GR64 } },
{ X86::MOVSX64rm32, Convert__Reg1_2__Mem5_1, { MCK_movslq, MCK_Mem, MCK_GR64 } },
{ X86::MOVLPSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVLSS2PSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVPS2SSrr, Convert__Reg1_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVSS2PSrr, Convert__Reg1_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVSSrr, Convert__Reg1_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVPS2SSmr, Convert__Mem5_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
{ X86::MOVSSrr, Convert__Reg1_2__Tie0__Reg1_1, { MCK_movss, MCK_FR32, MCK_FR32 } },
{ X86::MOVSSmr, Convert__Mem5_2__Reg1_1, { MCK_movss, MCK_FR32, MCK_Mem } },
{ X86::MOVSS2PSrm, Convert__Reg1_2__Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
{ X86::MOVSSrm, Convert__Reg1_2__Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
{ X86::MOVZSS2PSrm, Convert__Reg1_2__Mem5_1, { MCK_movss, MCK_Mem, MCK_FR32 } },
{ X86::MOVSX32rr16, Convert__Reg1_2__Reg1_1, { MCK_movswl, MCK_GR16, MCK_GR32 } },
{ X86::MOVSX32rm16, Convert__Reg1_2__Mem5_1, { MCK_movswl, MCK_Mem, MCK_GR32 } },
{ X86::MOVSX64rr16, Convert__Reg1_2__Reg1_1, { MCK_movswq, MCK_GR16, MCK_GR64 } },
@ -8364,7 +8352,7 @@ MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
Classes[i] = InvalidMatchClass;
// Search the table.
for (const MatchEntry *it = MatchTable, *ie = MatchTable + 2049; it != ie; ++it) {
for (const MatchEntry *it = MatchTable, *ie = MatchTable + 2037; it != ie; ++it) {
if (!IsSubclass(Classes[0], it->Classes[0]))
continue;
if (!IsSubclass(Classes[1], it->Classes[1]))

349
libclamav/c++/X86GenAsmWriter.inc
Unescape View File

@ -1358,51 +1358,45 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
205657149U, // MOVLHPSrr
138286150U, // MOVLPDmr
603984966U, // MOVLPDrm
205657166U, // MOVLPDrr
138286165U, // MOVLPSmr
603984981U, // MOVLPSrm
205657181U, // MOVLPSrr
138286158U, // MOVLPSmr
603984974U, // MOVLPSrm
136712635U, // MOVLQ128mr
205657166U, // MOVLSD2PDrr
205657181U, // MOVLSS2PSrr
1279399012U, // MOVMSKPDrr
1279399022U, // MOVMSKPSrr
2281706616U, // MOVNTDQArm
138024066U, // MOVNTDQmr
136582283U, // MOVNTImr
138155155U, // MOVNTPDmr
138155164U, // MOVNTPSmr
1279398998U, // MOVMSKPDrr
1279399008U, // MOVMSKPSrr
2281706602U, // MOVNTDQArm
138024052U, // MOVNTDQ_64mr
138024052U, // MOVNTDQmr
138024052U, // MOVNTDQmr_Int
136713341U, // MOVNTI_64mr
136582269U, // MOVNTImr
136582269U, // MOVNTImr_Int
138024069U, // MOVNTPDmr
138155141U, // MOVNTPDmr_Int
138024078U, // MOVNTPSmr
138155150U, // MOVNTPSmr_Int
0U, // MOVPC32r
138286158U, // MOVPD2SDmr
1279398990U, // MOVPD2SDrr
136581531U, // MOVPDI2DImr
1279398299U, // MOVPDI2DIrr
136712635U, // MOVPQI2QImr
1279398299U, // MOVPQIto64rr
137630813U, // MOVPS2SSmr
1279399005U, // MOVPS2SSrr
1409290683U, // MOVQI2PQIrm
1279398331U, // MOVQxrxr
5285U, // MOVSB
5291U, // MOVSD
2013271118U, // MOVSD2PDrm
1279398990U, // MOVSD2PDrr
138286158U, // MOVSDmr
2013271118U, // MOVSDrm
1279398990U, // MOVSDrr
5271U, // MOVSB
5277U, // MOVSD
138286243U, // MOVSDmr
2013271203U, // MOVSDrm
205657251U, // MOVSDrr
136712635U, // MOVSDto64mr
1279398299U, // MOVSDto64rr
1946162353U, // MOVSHDUPrm
1279399089U, // MOVSHDUPrr
1946162363U, // MOVSLDUPrm
1279399099U, // MOVSLDUPrr
1946162346U, // MOVSHDUPrm
1279399082U, // MOVSHDUPrr
1946162356U, // MOVSLDUPrm
1279399092U, // MOVSLDUPrr
136581531U, // MOVSS2DImr
1279398299U, // MOVSS2DIrr
2080379997U, // MOVSS2PSrm
1279399005U, // MOVSS2PSrr
137630813U, // MOVSSmr
2080379997U, // MOVSSrm
1279399005U, // MOVSSrr
137630910U, // MOVSSmr
2080380094U, // MOVSSrm
205657278U, // MOVSSrr
5317U, // MOVSW
0U, // MOVSX16rm8
1690309835U, // MOVSX16rm8W
@ -1434,8 +1428,6 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
1279398331U, // MOVZPQILo2PQIrr
1409290683U, // MOVZQI2PQIrm
1279398299U, // MOVZQI2PQIrr
2013271118U, // MOVZSD2PDrm
2080379997U, // MOVZSS2PSrm
0U, // MOVZX16rm8
1690309899U, // MOVZX16rm8W
0U, // MOVZX16rr8
@ -2649,9 +2641,9 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
"r\t\000monitor\000movw\t%ax, \000movw\t\000movl\t%eax, \000movl\t\000mo"
"vq\t%fs:\000movq\t%gs:\000movq\t%rax, \000movabsq\t\000movb\t%al, \000m"
"ovb\t\000movddup\t\000movdqa\t\000movdqu\t\000movhlps\t\000movhpd\t\000"
"movhps\t\000movlhps\t\000movlpd\t\000movsd\t\000movlps\t\000movss\t\000"
"movmskpd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000movnti\t\000movn"
"tpd\t\000movntps\t\000movsb\000movsl\000movshdup\t\000movsldup\t\000mov"
"movhps\t\000movlhps\t\000movlpd\t\000movlps\t\000movmskpd\t\000movmskps"
"\t\000movntdqa\t\000movntdq\t\000movnti\t\000movntpd\t\000movntps\t\000"
"movsb\000movsl\000movsd\t\000movshdup\t\000movsldup\t\000movss\t\000mov"
"sw\000movsbw\t\000movswl\t\000movsbl\t\000movswq\t\000movslq\t\000movsb"
"q\t\000movupd\t\000movups\t\000movzbw\t\000movzbl\t\000movzwl\t\000movz"
"wq\t\000movzbq\t\000mpsadbw\t\000mulw\t\000mull\t\000mulq\t\000mulb\t\000"
@ -3206,7 +3198,7 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
break;
case 10:
// EXTRACTPSmr, MOVPS2SSmr, MOVSSmr
// EXTRACTPSmr, MOVSSmr
printf32mem(MI, 0);
return;
break;
@ -3222,17 +3214,17 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 13:
// MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVUPDmr, MOVUPDmr_Int, MOVUPSmr, MOVUP...
// MOVAPDmr, MOVAPSmr, MOVNTDQ_64mr, MOVNTDQmr, MOVNTDQmr_Int, MOVNTPDmr,...
printf128mem(MI, 0);
return;
break;
case 14:
// MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr, MOVNTPSmr
// MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr_Int, MOVNTPSmr_Int
printi128mem(MI, 0);
return;
break;
case 15:
// MOVHPDmr, MOVHPSmr, MOVLPDmr, MOVLPSmr, MOVPD2SDmr, MOVSDmr
// MOVHPDmr, MOVHPSmr, MOVLPDmr, MOVLPSmr, MOVSDmr
printf64mem(MI, 0);
return;
break;
@ -3312,7 +3304,7 @@ const char *X86ATTInstPrinter::getRegisterName(unsigned RegNo) {
/// from the instruction set description. This returns the enum name of the
/// specified instruction.
const char *X86ATTInstPrinter::getInstructionName(unsigned Opcode) {
assert(Opcode < 2532 && "Invalid instruction number!");
assert(Opcode < 2524 && "Invalid instruction number!");
static const unsigned InstAsmOffset[] = {
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 136,
@ -3411,91 +3403,91 @@ const char *X86ATTInstPrinter::getInstructionName(unsigned Opcode) {
13388, 13400, 13408, 13416, 13424, 13437, 13449, 13461, 13469, 13476, 13483, 13496, 13504, 13511,
13518, 13525, 13538, 13545, 13558, 13569, 13578, 13587, 13596, 13605, 13614, 13623, 13633, 13643,
13655, 13667, 13678, 13689, 13698, 13707, 13716, 13725, 13738, 13747, 13760, 13770, 13779, 13788,
13797, 13806, 13816, 13825, 13834, 13843, 13852, 13861, 13870, 13881, 13893, 13905, 13916, 13927,
13938, 13948, 13957, 13967, 13977, 13986, 13997, 14008, 14020, 14032, 14044, 14057, 14068, 14079,
14091, 14100, 14106, 14112, 14123, 14134, 14142, 14150, 14158, 14170, 14182, 14193, 14204, 14215,
14226, 14237, 14248, 14259, 14270, 14278, 14286, 14294, 14300, 14311, 14323, 14334, 14346, 14358,
14369, 14381, 14392, 14404, 14416, 14427, 14439, 14451, 14462, 14471, 14484, 14493, 14506, 14515,
14524, 14537, 14546, 14559, 14568, 14581, 14594, 14610, 14626, 14639, 14652, 14664, 14676, 14687,
14699, 14710, 14722, 14739, 14756, 14768, 14779, 14791, 14802, 14814, 14828, 14840, 14851, 14864,
14876, 14890, 14902, 14913, 14926, 14937, 14948, 14959, 14970, 14981, 14992, 15003, 15014, 15025,
15036, 15047, 15054, 15061, 15068, 15075, 15082, 15089, 15095, 15101, 15109, 15117, 15125, 15133,
15141, 15153, 15161, 15173, 15181, 15193, 15201, 15213, 15222, 15231, 15241, 15251, 15262, 15272,
15281, 15291, 15300, 15310, 15322, 15331, 15343, 15355, 15368, 15381, 15394, 15407, 15420, 15433,
15443, 15449, 15456, 15463, 15470, 15477, 15484, 15491, 15497, 15503, 15508, 15514, 15520, 15527,
15534, 15541, 15548, 15555, 15562, 15568, 15574, 15582, 15589, 15597, 15604, 15611, 15619, 15626,
15633, 15644, 15652, 15659, 15667, 15674, 15681, 15689, 15696, 15703, 15714, 15722, 15731, 15739,
15746, 15755, 15763, 15770, 15777, 15788, 15794, 15800, 15806, 15812, 15818, 15824, 15834, 15841,
15848, 15855, 15862, 15870, 15878, 15886, 15894, 15901, 15908, 15914, 15920, 15926, 15937, 15947,
15958, 15968, 15979, 15989, 16000, 16010, 16021, 16031, 16042, 16052, 16063, 16074, 16085, 16096,
16107, 16118, 16129, 16140, 16148, 16156, 16164, 16172, 16180, 16188, 16197, 16206, 16215, 16224,
16234, 16244, 16254, 16264, 16272, 16280, 16293, 16306, 16318, 16330, 16338, 16346, 16353, 16360,
16368, 16376, 16384, 16392, 16404, 16416, 16427, 16438, 16448, 16458, 16468, 16478, 16488, 16498,
16508, 16518, 16531, 16544, 16557, 16570, 16583, 16596, 16609, 16622, 16635, 16648, 16660, 16672,
16688, 16704, 16719, 16734, 16744, 16754, 16764, 16774, 16784, 16794, 16804, 16814, 16827, 16840,
16853, 16866, 16879, 16892, 16905, 16918, 16931, 16944, 16956, 16968, 16984, 17000, 17015, 17030,
17039, 17048, 17057, 17066, 17075, 17084, 17093, 17102, 17114, 17125, 17137, 17148, 17161, 17173,
17186, 17198, 17210, 17221, 17233, 17244, 17260, 17276, 17288, 17299, 17311, 17322, 17335, 17347,
17360, 17372, 17384, 17395, 17407, 17418, 17427, 17436, 17445, 17454, 17463, 17472, 17482, 17492,
17507, 17521, 17536, 17550, 17560, 17570, 17579, 17588, 17597, 17606, 17615, 17624, 17633, 17642,
17651, 17660, 17669, 17678, 17687, 17696, 17705, 17714, 17723, 17732, 17741, 17750, 17759, 17768,
17777, 17786, 17797, 17808, 17819, 17830, 17841, 17852, 17863, 17874, 17885, 17896, 17907, 17918,
17929, 17940, 17951, 17962, 17973, 17984, 17995, 18006, 18017, 18028, 18039, 18050, 18061, 18070,
18079, 18093, 18106, 18120, 18133, 18143, 18153, 18162, 18171, 18180, 18193, 18202, 18215, 18224,
18233, 18243, 18253, 18260, 18269, 18278, 18285, 18294, 18303, 18310, 18319, 18328, 18339, 18350,
18361, 18372, 18383, 18394, 18399, 18405, 18411, 18419, 18427, 18435, 18443, 18451, 18459, 18465,
18471, 18483, 18494, 18505, 18516, 18525, 18534, 18546, 18557, 18569, 18580, 18589, 18598, 18608,
18618, 18628, 18638, 18650, 18661, 18673, 18684, 18696, 18707, 18719, 18730, 18742, 18753, 18765,
18776, 18785, 18793, 18801, 18809, 18817, 18825, 18833, 18841, 18849, 18857, 18865, 18873, 18881,
18889, 18897, 18905, 18914, 18922, 18930, 18938, 18946, 18954, 18962, 18970, 18978, 18986, 18994,
19002, 19010, 19018, 19026, 19034, 19043, 19052, 19061, 19070, 19080, 19090, 19100, 19110, 19118,
19126, 19134, 19142, 19154, 19166, 19178, 19190, 19203, 19216, 19228, 19240, 19252, 19264, 19276,
19288, 19301, 19314, 19326, 19338, 19346, 19356, 19366, 19376, 19386, 19395, 19403, 19413, 19423,
19433, 19443, 19452, 19460, 19470, 19480, 19486, 19493, 19502, 19511, 19520, 19529, 19538, 19547,
19556, 19563, 19570, 19578, 19587, 19595, 19603, 19612, 19620, 19628, 19637, 19645, 19653, 19662,
19670, 19678, 19687, 19695, 19703, 19712, 19720, 19727, 19735, 19742, 19749, 19757, 19764, 19771,
19782, 19789, 19800, 19807, 19818, 19825, 19836, 19844, 19853, 19861, 19869, 19878, 19886, 19894,
19903, 19911, 19919, 19928, 19936, 19944, 19953, 19961, 19969, 19978, 19986, 19993, 20001, 20008,
20015, 20023, 20030, 20036, 20042, 20048, 20055, 20068, 20078, 20088, 20098, 20108, 20119, 20129,
20139, 20149, 20159, 20163, 20168, 20176, 20185, 20193, 20201, 20210, 20218, 20226, 20235, 20243,
20251, 20260, 20268, 20276, 20285, 20293, 20301, 20310, 20318, 20325, 20333, 20340, 20347, 20355,
20362, 20370, 20379, 20387, 20395, 20404, 20412, 20420, 20429, 20437, 20445, 20454, 20462, 20470,
20479, 20487, 20495, 20504, 20512, 20519, 20527, 20534, 20541, 20549, 20556, 20569, 20582, 20595,
20608, 20621, 20634, 20647, 20660, 20664, 20673, 20686, 20695, 20708, 20717, 20730, 20739, 20752,
20757, 20765, 20774, 20782, 20790, 20799, 20807, 20815, 20824, 20832, 20840, 20849, 20857, 20865,
20874, 20882, 20890, 20899, 20907, 20914, 20922, 20929, 20936, 20944, 20951, 20960, 20968, 20977,
20985, 20993, 21002, 21010, 21018, 21030, 21039, 21047, 21056, 21064, 21072, 21081, 21089, 21097,
21109, 21118, 21128, 21137, 21145, 21155, 21164, 21172, 21180, 21192, 21199, 21206, 21213, 21220,
21227, 21234, 21245, 21252, 21259, 21266, 21272, 21279, 21286, 21292, 21298, 21305, 21312, 21322,
21332, 21342, 21351, 21357, 21363, 21369, 21375, 21382, 21389, 21395, 21401, 21408, 21415, 21421,
21427, 21434, 21441, 21448, 21455, 21462, 21469, 21476, 21483, 21489, 21495, 21501, 21507, 21513,
21519, 21526, 21532, 21540, 21549, 21557, 21565, 21574, 21582, 21590, 21599, 21607, 21615, 21624,
21632, 21640, 21649, 21657, 21665, 21674, 21682, 21689, 21697, 21704, 21711, 21719, 21726, 21737,
21748, 21759, 21770, 21781, 21792, 21803, 21814, 21825, 21836, 21847, 21858, 21866, 21875, 21883,
21891, 21900, 21908, 21916, 21925, 21933, 21941, 21950, 21958, 21966, 21975, 21983, 21991, 22000,
22008, 22015, 22023, 22030, 22037, 22045, 22052, 22063, 22074, 22085, 22096, 22107, 22118, 22129,
22140, 22151, 22162, 22173, 22184, 22194, 22204, 22214, 22224, 22230, 22236, 22245, 22254, 22263,
22271, 22279, 22287, 22295, 22303, 22311, 22319, 22327, 22335, 22347, 22355, 22367, 22375, 22387,
22395, 22407, 22415, 22427, 22435, 22447, 22455, 22467, 22475, 22487, 22494, 22504, 22514, 22524,
22534, 22538, 22542, 22546, 22554, 22560, 22566, 22572, 22577, 22582, 22590, 22598, 22607, 22616,
22625, 22633, 22642, 22651, 22662, 22673, 22684, 22694, 22704, 22716, 22726, 22738, 22750, 22757,
22766, 22774, 22783, 22791, 22799, 22808, 22816, 22824, 22836, 22845, 22853, 22862, 22870, 22878,
22887, 22895, 22903, 22915, 22924, 22934, 22943, 22951, 22961, 22970, 22978, 22986, 22998, 23005,
23012, 23019, 23026, 23033, 23040, 23051, 23059, 23067, 23075, 23083, 23093, 23103, 23114, 23125,
23137, 23148, 23159, 23170, 23183, 23196, 23209, 23223, 23237, 23251, 23265, 23279, 23293, 23304,
23312, 23324, 23332, 23344, 23352, 23364, 23372, 23384, 23393, 23402, 23412, 23422, 23433, 23443,
23452, 23462, 23471, 23481, 23493, 23502, 23514, 23526, 23539, 23552, 23565, 23578, 23591, 23604,
23614, 23621, 23629, 23638, 23646, 23656, 23663, 23672, 23681, 23690, 23701, 23712, 23725, 23736,
23749, 23759, 23768, 23777, 23786, 23795, 23805, 23814, 23823, 23832, 23841, 23851, 23862, 23873,
23882, 23891, 23899, 23907, 23915, 23923, 23931, 23942, 23953, 23958, 23964, 23973, 23982, 23991,
24001, 24011, 24021, 24031, 24041, 24050, 24060, 24069, 24081, 24093, 24105, 24116, 24127, 24138,
24146, 24157, 24168, 24179, 24190, 24201, 24212, 24223, 24234, 24256, 24262, 24268, 24274, 24280,
24287, 24296, 24305, 24314, 24323, 24334, 24345, 24356, 24367, 24376, 24388, 24400, 24412, 24424,
24431, 24437, 24444, 24457, 24462, 24469, 24480, 24497, 24508, 24514, 24523, 24532, 24541, 24550,
24559, 24568, 24576, 24584, 24593, 24602, 24611, 24620, 24629, 24638, 24647, 24656, 24665, 24673,
24681, 24687, 24692, 24701, 24709, 24718, 24726, 24734, 24743, 24751, 24759, 24771, 24780, 24788,
24797, 24805, 24813, 24822, 24830, 24838, 24850, 24859, 24869, 24878, 24886, 24896, 24905, 24913,
24921, 24933, 24940, 24947, 24954, 24961, 24968, 24975, 24986, 24994, 25002, 25010, 0
13797, 13806, 13816, 13825, 13834, 13843, 13852, 13863, 13874, 13885, 13896, 13909, 13919, 13933,
13945, 13954, 13967, 13977, 13991, 14001, 14015, 14024, 14036, 14048, 14060, 14073, 14085, 14094,
14100, 14106, 14114, 14122, 14130, 14142, 14154, 14165, 14176, 14187, 14198, 14209, 14220, 14228,
14236, 14244, 14250, 14261, 14273, 14284, 14296, 14308, 14319, 14331, 14342, 14354, 14366, 14377,
14389, 14401, 14412, 14421, 14434, 14443, 14456, 14465, 14474, 14487, 14496, 14509, 14518, 14531,
14544, 14560, 14576, 14589, 14602, 14613, 14625, 14636, 14648, 14665, 14682, 14694, 14705, 14717,
14728, 14740, 14754, 14766, 14777, 14790, 14802, 14816, 14828, 14839, 14852, 14863, 14874, 14885,
14896, 14907, 14918, 14929, 14940, 14951, 14962, 14973, 14980, 14987, 14994, 15001, 15008, 15015,
15021, 15027, 15035, 15043, 15051, 15059, 15067, 15079, 15087, 15099, 15107, 15119, 15127, 15139,
15148, 15157, 15167, 15177, 15188, 15198, 15207, 15217, 15226, 15236, 15248, 15257, 15269, 15281,
15294, 15307, 15320, 15333, 15346, 15359, 15369, 15375, 15382, 15389, 15396, 15403, 15410, 15417,
15423, 15429, 15434, 15440, 15446, 15453, 15460, 15467, 15474, 15481, 15488, 15494, 15500, 15508,
15515, 15523, 15530, 15537, 15545, 15552, 15559, 15570, 15578, 15585, 15593, 15600, 15607, 15615,
15622, 15629, 15640, 15648, 15657, 15665, 15672, 15681, 15689, 15696, 15703, 15714, 15720, 15726,
15732, 15738, 15744, 15750, 15760, 15767, 15774, 15781, 15788, 15796, 15804, 15812, 15820, 15827,
15834, 15840, 15846, 15852, 15863, 15873, 15884, 15894, 15905, 15915, 15926, 15936, 15947, 15957,
15968, 15978, 15989, 16000, 16011, 16022, 16033, 16044, 16055, 16066, 16074, 16082, 16090, 16098,
16106, 16114, 16123, 16132, 16141, 16150, 16160, 16170, 16180, 16190, 16198, 16206, 16219, 16232,
16244, 16256, 16264, 16272, 16279, 16286, 16294, 16302, 16310, 16318, 16330, 16342, 16353, 16364,
16374, 16384, 16394, 16404, 16414, 16424, 16434, 16444, 16457, 16470, 16483, 16496, 16509, 16522,
16535, 16548, 16561, 16574, 16586, 16598, 16614, 16630, 16645, 16660, 16670, 16680, 16690, 16700,
16710, 16720, 16730, 16740, 16753, 16766, 16779, 16792, 16805, 16818, 16831, 16844, 16857, 16870,
16882, 16894, 16910, 16926, 16941, 16956, 16965, 16974, 16983, 16992, 17001, 17010, 17019, 17028,
17040, 17051, 17063, 17074, 17087, 17099, 17112, 17124, 17136, 17147, 17159, 17170, 17186, 17202,
17214, 17225, 17237, 17248, 17261, 17273, 17286, 17298, 17310, 17321, 17333, 17344, 17353, 17362,
17371, 17380, 17389, 17398, 17408, 17418, 17433, 17447, 17462, 17476, 17486, 17496, 17505, 17514,
17523, 17532, 17541, 17550, 17559, 17568, 17577, 17586, 17595, 17604, 17613, 17622, 17631, 17640,
17649, 17658, 17667, 17676, 17685, 17694, 17703, 17712, 17723, 17734, 17745, 17756, 17767, 17778,
17789, 17800, 17811, 17822, 17833, 17844, 17855, 17866, 17877, 17888, 17899, 17910, 17921, 17932,
17943, 17954, 17965, 17976, 17987, 17996, 18005, 18019, 18032, 18046, 18059, 18069, 18079, 18088,
18097, 18106, 18119, 18128, 18141, 18150, 18159, 18169, 18179, 18186, 18195, 18204, 18211, 18220,
18229, 18236, 18245, 18254, 18265, 18276, 18287, 18298, 18309, 18320, 18325, 18331, 18337, 18345,
18353, 18361, 18369, 18377, 18385, 18391, 18397, 18409, 18420, 18431, 18442, 18451, 18460, 18472,
18483, 18495, 18506, 18515, 18524, 18534, 18544, 18554, 18564, 18576, 18587, 18599, 18610, 18622,
18633, 18645, 18656, 18668, 18679, 18691, 18702, 18711, 18719, 18727, 18735, 18743, 18751, 18759,
18767, 18775, 18783, 18791, 18799, 18807, 18815, 18823, 18831, 18840, 18848, 18856, 18864, 18872,
18880, 18888, 18896, 18904, 18912, 18920, 18928, 18936, 18944, 18952, 18960, 18969, 18978, 18987,
18996, 19006, 19016, 19026, 19036, 19044, 19052, 19060, 19068, 19080, 19092, 19104, 19116, 19129,
19142, 19154, 19166, 19178, 19190, 19202, 19214, 19227, 19240, 19252, 19264, 19272, 19282, 19292,
19302, 19312, 19321, 19329, 19339, 19349, 19359, 19369, 19378, 19386, 19396, 19406, 19412, 19419,
19428, 19437, 19446, 19455, 19464, 19473, 19482, 19489, 19496, 19504, 19513, 19521, 19529, 19538,
19546, 19554, 19563, 19571, 19579, 19588, 19596, 19604, 19613, 19621, 19629, 19638, 19646, 19653,
19661, 19668, 19675, 19683, 19690, 19697, 19708, 19715, 19726, 19733, 19744, 19751, 19762, 19770,
19779, 19787, 19795, 19804, 19812, 19820, 19829, 19837, 19845, 19854, 19862, 19870, 19879, 19887,
19895, 19904, 19912, 19919, 19927, 19934, 19941, 19949, 19956, 19962, 19968, 19974, 19981, 19994,
20004, 20014, 20024, 20034, 20045, 20055, 20065, 20075, 20085, 20089, 20094, 20102, 20111, 20119,
20127, 20136, 20144, 20152, 20161, 20169, 20177, 20186, 20194, 20202, 20211, 20219, 20227, 20236,
20244, 20251, 20259, 20266, 20273, 20281, 20288, 20296, 20305, 20313, 20321, 20330, 20338, 20346,
20355, 20363, 20371, 20380, 20388, 20396, 20405, 20413, 20421, 20430, 20438, 20445, 20453, 20460,
20467, 20475, 20482, 20495, 20508, 20521, 20534, 20547, 20560, 20573, 20586, 20590, 20599, 20612,
20621, 20634, 20643, 20656, 20665, 20678, 20683, 20691, 20700, 20708, 20716, 20725, 20733, 20741,
20750, 20758, 20766, 20775, 20783, 20791, 20800, 20808, 20816, 20825, 20833, 20840, 20848, 20855,
20862, 20870, 20877, 20886, 20894, 20903, 20911, 20919, 20928, 20936, 20944, 20956, 20965, 20973,
20982, 20990, 20998, 21007, 21015, 21023, 21035, 21044, 21054, 21063, 21071, 21081, 21090, 21098,
21106, 21118, 21125, 21132, 21139, 21146, 21153, 21160, 21171, 21178, 21185, 21192, 21198, 21205,
21212, 21218, 21224, 21231, 21238, 21248, 21258, 21268, 21277, 21283, 21289, 21295, 21301, 21308,
21315, 21321, 21327, 21334, 21341, 21347, 21353, 21360, 21367, 21374, 21381, 21388, 21395, 21402,
21409, 21415, 21421, 21427, 21433, 21439, 21445, 21452, 21458, 21466, 21475, 21483, 21491, 21500,
21508, 21516, 21525, 21533, 21541, 21550, 21558, 21566, 21575, 21583, 21591, 21600, 21608, 21615,
21623, 21630, 21637, 21645, 21652, 21663, 21674, 21685, 21696, 21707, 21718, 21729, 21740, 21751,
21762, 21773, 21784, 21792, 21801, 21809, 21817, 21826, 21834, 21842, 21851, 21859, 21867, 21876,
21884, 21892, 21901, 21909, 21917, 21926, 21934, 21941, 21949, 21956, 21963, 21971, 21978, 21989,
22000, 22011, 22022, 22033, 22044, 22055, 22066, 22077, 22088, 22099, 22110, 22120, 22130, 22140,
22150, 22156, 22162, 22171, 22180, 22189, 22197, 22205, 22213, 22221, 22229, 22237, 22245, 22253,
22261, 22273, 22281, 22293, 22301, 22313, 22321, 22333, 22341, 22353, 22361, 22373, 22381, 22393,
22401, 22413, 22420, 22430, 22440, 22450, 22460, 22464, 22468, 22472, 22480, 22486, 22492, 22498,
22503, 22508, 22516, 22524, 22533, 22542, 22551, 22559, 22568, 22577, 22588, 22599, 22610, 22620,
22630, 22642, 22652, 22664, 22676, 22683, 22692, 22700, 22709, 22717, 22725, 22734, 22742, 22750,
22762, 22771, 22779, 22788, 22796, 22804, 22813, 22821, 22829, 22841, 22850, 22860, 22869, 22877,
22887, 22896, 22904, 22912, 22924, 22931, 22938, 22945, 22952, 22959, 22966, 22977, 22985, 22993,
23001, 23009, 23019, 23029, 23040, 23051, 23063, 23074, 23085, 23096, 23109, 23122, 23135, 23149,
23163, 23177, 23191, 23205, 23219, 23230, 23238, 23250, 23258, 23270, 23278, 23290, 23298, 23310,
23319, 23328, 23338, 23348, 23359, 23369, 23378, 23388, 23397, 23407, 23419, 23428, 23440, 23452,
23465, 23478, 23491, 23504, 23517, 23530, 23540, 23547, 23555, 23564, 23572, 23582, 23589, 23598,
23607, 23616, 23627, 23638, 23651, 23662, 23675, 23685, 23694, 23703, 23712, 23721, 23731, 23740,
23749, 23758, 23767, 23777, 23788, 23799, 23808, 23817, 23825, 23833, 23841, 23849, 23857, 23868,
23879, 23884, 23890, 23899, 23908, 23917, 23927, 23937, 23947, 23957, 23967, 23976, 23986, 23995,
24007, 24019, 24031, 24042, 24053, 24064, 24072, 24083, 24094, 24105, 24116, 24127, 24138, 24149,
24160, 24182, 24188, 24194, 24200, 24206, 24213, 24222, 24231, 24240, 24249, 24260, 24271, 24282,
24293, 24302, 24314, 24326, 24338, 24350, 24357, 24363, 24370, 24383, 24388, 24395, 24406, 24423,
24434, 24440, 24449, 24458, 24467, 24476, 24485, 24494, 24502, 24510, 24519, 24528, 24537, 24546,
24555, 24564, 24573, 24582, 24591, 24599, 24607, 24613, 24618, 24627, 24635, 24644, 24652, 24660,
24669, 24677, 24685, 24697, 24706, 24714, 24723, 24731, 24739, 24748, 24756, 24764, 24776, 24785,
24795, 24804, 24812, 24822, 24831, 24839, 24847, 24859, 24866, 24873, 24880, 24887, 24894, 24901,
24912, 24920, 24928, 24936, 0
};
const char *Strs =
@ -3749,57 +3741,56 @@ const char *X86ATTInstPrinter::getInstructionName(unsigned Opcode) {
"DI2SSrm\000MOVDI2SSrr\000MOVDQAmr\000MOVDQArm\000MOVDQArr\000MOVDQUmr\000"
"MOVDQUmr_Int\000MOVDQUrm\000MOVDQUrm_Int\000MOVHLPSrr\000MOVHPDmr\000MO"
"VHPDrm\000MOVHPSmr\000MOVHPSrm\000MOVLHPSrr\000MOVLPDmr\000MOVLPDrm\000"
"MOVLPDrr\000MOVLPSmr\000MOVLPSrm\000MOVLPSrr\000MOVLQ128mr\000MOVLSD2PD"
"rr\000MOVLSS2PSrr\000MOVMSKPDrr\000MOVMSKPSrr\000MOVNTDQArm\000MOVNTDQm"
"r\000MOVNTImr\000MOVNTPDmr\000MOVNTPSmr\000MOVPC32r\000MOVPD2SDmr\000MO"
"VPD2SDrr\000MOVPDI2DImr\000MOVPDI2DIrr\000MOVPQI2QImr\000MOVPQIto64rr\000"
"MOVPS2SSmr\000MOVPS2SSrr\000MOVQI2PQIrm\000MOVQxrxr\000MOVSB\000MOVSD\000"
"MOVSD2PDrm\000MOVSD2PDrr\000MOVSDmr\000MOVSDrm\000MOVSDrr\000MOVSDto64m"
"r\000MOVSDto64rr\000MOVSHDUPrm\000MOVSHDUPrr\000MOVSLDUPrm\000MOVSLDUPr"
"r\000MOVSS2DImr\000MOVSS2DIrr\000MOVSS2PSrm\000MOVSS2PSrr\000MOVSSmr\000"
"MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16rm8\000MOVSX16rm8W\000MOVSX16rr8\000"
"MOVSX16rr8W\000MOVSX32rm16\000MOVSX32rm8\000MOVSX32rr16\000MOVSX32rr8\000"
"MOVSX64rm16\000MOVSX64rm32\000MOVSX64rm8\000MOVSX64rr16\000MOVSX64rr32\000"
"MOVSX64rr8\000MOVUPDmr\000MOVUPDmr_Int\000MOVUPDrm\000MOVUPDrm_Int\000M"
"OVUPDrr\000MOVUPSmr\000MOVUPSmr_Int\000MOVUPSrm\000MOVUPSrm_Int\000MOVU"
"PSrr\000MOVZDI2PDIrm\000MOVZDI2PDIrr\000MOVZPQILo2PQIrm\000MOVZPQILo2PQ"
"Irr\000MOVZQI2PQIrm\000MOVZQI2PQIrr\000MOVZSD2PDrm\000MOVZSS2PSrm\000MO"
"VZX16rm8\000MOVZX16rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX32_NOREXrm"
"8\000MOVZX32_NOREXrr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32rr16\000MO"
"VZX32rr8\000MOVZX64rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MOVZX64rm8\000"
"MOVZX64rm8_Q\000MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32\000MOVZX64r"
"r8\000MOVZX64rr8_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp3280\000MOV_Fp6"
"432\000MOV_Fp6464\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064\000MOV_Fp80"
"80\000MPSADBWrmi\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32m\000MUL32r\000"
"MUL64m\000MUL64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr\000MULPSrm\000"
"MULPSrr\000MULSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_Int\000MULSSrm\000"
"MULSSrm_Int\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000MUL_F64m\000MUL_FI"
"16m\000MUL_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp32\000MUL_Fp32m\000"
"MUL_Fp64\000MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000MUL_Fp80m32\000MUL_"
"Fp80m64\000MUL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16m80\000MUL_FpI32m32"
"\000MUL_FpI32m64\000MUL_FpI32m80\000MUL_FrST0\000MWAIT\000NEG16m\000NEG"
"16r\000NEG32m\000NEG32r\000NEG64m\000NEG64r\000NEG8m\000NEG8r\000NOOP\000"
"NOOPL\000NOOPW\000NOT16m\000NOT16r\000NOT32m\000NOT32r\000NOT64m\000NOT"
"64r\000NOT8m\000NOT8r\000OR16i16\000OR16mi\000OR16mi8\000OR16mr\000OR16"
"ri\000OR16ri8\000OR16rm\000OR16rr\000OR16rr_REV\000OR32i32\000OR32mi\000"
"OR32mi8\000OR32mr\000OR32ri\000OR32ri8\000OR32rm\000OR32rr\000OR32rr_RE"
"V\000OR64i32\000OR64mi32\000OR64mi8\000OR64mr\000OR64ri32\000OR64ri8\000"
"OR64rm\000OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000OR8mr\000OR8ri\000O"
"R8rm\000OR8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000ORPSrm\000ORPSrr\000O"
"UT16ir\000OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000OUT8rr\000OUTSB\000"
"OUTSD\000OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr128\000PABSBrr64\000"
"PABSDrm128\000PABSDrm64\000PABSDrr128\000PABSDrr64\000PABSWrm128\000PAB"
"SWrm64\000PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PACKSSDWrr\000PACKSS"
"WBrm\000PACKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACKUSWBrm\000PACKUSW"
"Brr\000PADDBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PADDQrm\000PADDQrr\000"
"PADDSBrm\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADDUSBrm\000PADDUSBrr\000"
"PADDUSWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000PALIGNR128rm\000PALIGNR"
"128rr\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000PANDNrr\000PANDrm\000"
"PANDrr\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr\000PBLENDVBrm0\000PB"
"LENDVBrr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm\000PCMPEQBrr\000PCMP"
"EQDrm\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PCMPEQWrm\000PCMPEQWrr\000"
"PCMPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000PCMPESTRICrr\000PCMPEST"
"RIOrm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPESTRISrr\000PCMPESTRIZrm\000"
"MOVLPSmr\000MOVLPSrm\000MOVLQ128mr\000MOVMSKPDrr\000MOVMSKPSrr\000MOVNT"
"DQArm\000MOVNTDQ_64mr\000MOVNTDQmr\000MOVNTDQmr_Int\000MOVNTI_64mr\000M"
"OVNTImr\000MOVNTImr_Int\000MOVNTPDmr\000MOVNTPDmr_Int\000MOVNTPSmr\000M"
"OVNTPSmr_Int\000MOVPC32r\000MOVPDI2DImr\000MOVPDI2DIrr\000MOVPQI2QImr\000"
"MOVPQIto64rr\000MOVQI2PQIrm\000MOVQxrxr\000MOVSB\000MOVSD\000MOVSDmr\000"
"MOVSDrm\000MOVSDrr\000MOVSDto64mr\000MOVSDto64rr\000MOVSHDUPrm\000MOVSH"
"DUPrr\000MOVSLDUPrm\000MOVSLDUPrr\000MOVSS2DImr\000MOVSS2DIrr\000MOVSSm"
"r\000MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16rm8\000MOVSX16rm8W\000MOVSX1"
"6rr8\000MOVSX16rr8W\000MOVSX32rm16\000MOVSX32rm8\000MOVSX32rr16\000MOVS"
"X32rr8\000MOVSX64rm16\000MOVSX64rm32\000MOVSX64rm8\000MOVSX64rr16\000MO"
"VSX64rr32\000MOVSX64rr8\000MOVUPDmr\000MOVUPDmr_Int\000MOVUPDrm\000MOVU"
"PDrm_Int\000MOVUPDrr\000MOVUPSmr\000MOVUPSmr_Int\000MOVUPSrm\000MOVUPSr"
"m_Int\000MOVUPSrr\000MOVZDI2PDIrm\000MOVZDI2PDIrr\000MOVZPQILo2PQIrm\000"
"MOVZPQILo2PQIrr\000MOVZQI2PQIrm\000MOVZQI2PQIrr\000MOVZX16rm8\000MOVZX1"
"6rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX32_NOREXrm8\000MOVZX32_NOREX"
"rr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32rr16\000MOVZX32rr8\000MOVZX6"
"4rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MOVZX64rm8\000MOVZX64rm8_Q\000"
"MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32\000MOVZX64rr8\000MOVZX64rr8"
"_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp3280\000MOV_Fp6432\000MOV_Fp646"
"4\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064\000MOV_Fp8080\000MPSADBWrmi"
"\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32m\000MUL32r\000MUL64m\000MUL"
"64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr\000MULPSrm\000MULPSrr\000MU"
"LSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_Int\000MULSSrm\000MULSSrm_In"
"t\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000MUL_F64m\000MUL_FI16m\000MUL"
"_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp32\000MUL_Fp32m\000MUL_Fp64\000"
"MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000MUL_Fp80m32\000MUL_Fp80m64\000M"
"UL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16m80\000MUL_FpI32m32\000MUL_FpI3"
"2m64\000MUL_FpI32m80\000MUL_FrST0\000MWAIT\000NEG16m\000NEG16r\000NEG32"
"m\000NEG32r\000NEG64m\000NEG64r\000NEG8m\000NEG8r\000NOOP\000NOOPL\000N"
"OOPW\000NOT16m\000NOT16r\000NOT32m\000NOT32r\000NOT64m\000NOT64r\000NOT"
"8m\000NOT8r\000OR16i16\000OR16mi\000OR16mi8\000OR16mr\000OR16ri\000OR16"
"ri8\000OR16rm\000OR16rr\000OR16rr_REV\000OR32i32\000OR32mi\000OR32mi8\000"
"OR32mr\000OR32ri\000OR32ri8\000OR32rm\000OR32rr\000OR32rr_REV\000OR64i3"
"2\000OR64mi32\000OR64mi8\000OR64mr\000OR64ri32\000OR64ri8\000OR64rm\000"
"OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000OR8mr\000OR8ri\000OR8rm\000OR"
"8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000ORPSrm\000ORPSrr\000OUT16ir\000"
"OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000OUT8rr\000OUTSB\000OUTSD\000"
"OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr128\000PABSBrr64\000PABSDrm1"
"28\000PABSDrm64\000PABSDrr128\000PABSDrr64\000PABSWrm128\000PABSWrm64\000"
"PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PACKSSDWrr\000PACKSSWBrm\000PA"
"CKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACKUSWBrm\000PACKUSWBrr\000PAD"
"DBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PADDQrm\000PADDQrr\000PADDSBrm"
"\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADDUSBrm\000PADDUSBrr\000PADDU"
"SWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000PALIGNR128rm\000PALIGNR128rr"
"\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000PANDNrr\000PANDrm\000PANDr"
"r\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr\000PBLENDVBrm0\000PBLENDV"
"Brr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm\000PCMPEQBrr\000PCMPEQDrm"
"\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PCMPEQWrm\000PCMPEQWrr\000PC"
"MPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000PCMPESTRICrr\000PCMPESTRI"
"Orm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPESTRISrr\000PCMPESTRIZrm\000"
"PCMPESTRIZrr\000PCMPESTRIrm\000PCMPESTRIrr\000PCMPESTRM128MEM\000PCMPES"
"TRM128REG\000PCMPESTRM128rm\000PCMPESTRM128rr\000PCMPGTBrm\000PCMPGTBrr"
"\000PCMPGTDrm\000PCMPGTDrr\000PCMPGTQrm\000PCMPGTQrr\000PCMPGTWrm\000PC"

373
libclamav/c++/X86GenAsmWriter1.inc
Unescape View File

@ -1358,52 +1358,46 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
138547133U, // MOVLHPSrr
943722438U, // MOVLPDmr
139333574U, // MOVLPDrm
138547150U, // MOVLPDrr
943722453U, // MOVLPSmr
139333589U, // MOVLPSrm
138547165U, // MOVLPSrr
943722446U, // MOVLPSmr
139333582U, // MOVLPSrm
541068621U, // MOVLQ128mr
138547150U, // MOVLSD2PDrr
138547165U, // MOVLSS2PSrr
139857892U, // MOVMSKPDrr
139857902U, // MOVMSKPSrr
140775416U, // MOVNTDQArm
2818576386U, // MOVNTDQmr
406851595U, // MOVNTImr
1480593427U, // MOVNTPDmr
1480593436U, // MOVNTPSmr
139857878U, // MOVMSKPDrr
139857888U, // MOVMSKPSrr
140775402U, // MOVNTDQArm
2818576372U, // MOVNTDQ_64mr
2818576372U, // MOVNTDQmr
2818576372U, // MOVNTDQmr_Int
541069309U, // MOVNTI_64mr
406851581U, // MOVNTImr
406851581U, // MOVNTImr_Int
2818576389U, // MOVNTPDmr
1480593413U, // MOVNTPDmr_Int
2818576398U, // MOVNTPSmr
1480593422U, // MOVNTPSmr_Int
0U, // MOVPC32r
943722446U, // MOVPD2SDmr
139857870U, // MOVPD2SDrr
406850861U, // MOVPDI2DImr
139857197U, // MOVPDI2DIrr
541068621U, // MOVPQI2QImr
139857229U, // MOVPQIto64rr
809504733U, // MOVPS2SSmr
139857885U, // MOVPS2SSrr
140119373U, // MOVQI2PQIrm
139857229U, // MOVQxrxr
4133U, // MOVSB
4134U, // MOVSD
140513230U, // MOVSD2PDrm
139857870U, // MOVSD2PDrr
943722446U, // MOVSDmr
140513230U, // MOVSDrm
139857870U, // MOVSDrr
4119U, // MOVSB
4120U, // MOVSD
943722526U, // MOVSDmr
140513310U, // MOVSDrm
138547230U, // MOVSDrr
541068621U, // MOVSDto64mr
139857229U, // MOVSDto64rr
140382252U, // MOVSHDUPrm
139857964U, // MOVSHDUPrr
140382262U, // MOVSLDUPrm
139857974U, // MOVSLDUPrr
140382245U, // MOVSHDUPrm
139857957U, // MOVSHDUPrr
140382255U, // MOVSLDUPrm
139857967U, // MOVSLDUPrr
406850861U, // MOVSS2DImr
139857197U, // MOVSS2DIrr
140644317U, // MOVSS2PSrm
139857885U, // MOVSS2PSrr
809504733U, // MOVSSmr
140644317U, // MOVSSrm
139857885U, // MOVSSrr
4133U, // MOVSW
809504825U, // MOVSSmr
140644409U, // MOVSSrm
138547257U, // MOVSSrr
4119U, // MOVSW
0U, // MOVSX16rm8
140251200U, // MOVSX16rm8W
0U, // MOVSX16rr8
@ -1434,8 +1428,6 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
139857229U, // MOVZPQILo2PQIrr
140119373U, // MOVZQI2PQIrm
139857229U, // MOVZQI2PQIrr
140513230U, // MOVZSD2PDrm
140644317U, // MOVZSS2PSrm
0U, // MOVZX16rm8
140251231U, // MOVZX16rm8W
0U, // MOVZX16rr8
@ -2282,9 +2274,9 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
5658U, // STD
5662U, // STI
402658850U, // STMXCSR
4133U, // STOSB
4119U, // STOSB
5675U, // STOSD
4133U, // STOSW
4119U, // STOSW
5681U, // STRm
5681U, // STRr
805312054U, // ST_F32m
@ -2624,20 +2616,20 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
"pcklbw\t\000punpckldq\t\000punpcklwd\t\000pxor\t\000monitor\000mov\t\000"
"mov\t%ax, \000mov\t%eax, \000movq\t%fs:\000movq\t%gs:\000mov\t%rax, \000"
"movabs\t\000mov\t%al, \000movddup\t\000movdqa\t\000movdqu\t\000movhlps\t"
"\000movhpd\t\000movhps\t\000movlhps\t\000movlpd\t\000movsd\t\000movlps\t"
"\000movss\t\000movmskpd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000m"
"ovnti\t\000movntpd\t\000movntps\t\000\000movsd\000movshdup\t\000movsldu"
"p\t\000movsx\t\000movsxd\t\000movupd\t\000movups\t\000movzx\t\000mpsadb"
"w\t\000mul\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmul\t\000f"
"imul\t\000fmulp\t\000mwait\000neg\t\000nop\000nop\t\000not\t\000or\t%ax"
", \000or\t\000or\t%eax, \000or\t%rax, \000or\t%al, \000out\t\000out\t%D"
"X, %AX\000out\t%DX, %EAX\000out\t%DX, %AL\000outsb\000outsd\000outsw\000"
"pabsb\t\000pabsd\t\000pabsw\t\000packusdw\t\000palignr\t\000pblendvb\t\000"
"pblendw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000#PC"
"MPESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#PCM"
"PISTRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcmpistrm\t\000pextrb"
"\t\000pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000phaddw\t\000phmi"
"nposuw\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t\000"
"\000movhpd\t\000movhps\t\000movlhps\t\000movlpd\t\000movlps\t\000movmsk"
"pd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000movnti\t\000movntpd\t\000"
"movntps\t\000\000movsd\000movsd\t\000movshdup\t\000movsldup\t\000movss\t"
"\000movsx\t\000movsxd\t\000movupd\t\000movups\t\000movzx\t\000mpsadbw\t"
"\000mul\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmul\t\000fimu"
"l\t\000fmulp\t\000mwait\000neg\t\000nop\000nop\t\000not\t\000or\t%ax, \000"
"or\t\000or\t%eax, \000or\t%rax, \000or\t%al, \000out\t\000out\t%DX, %AX"
"\000out\t%DX, %EAX\000out\t%DX, %AL\000outsb\000outsd\000outsw\000pabsb"
"\t\000pabsd\t\000pabsw\t\000packusdw\t\000palignr\t\000pblendvb\t\000pb"
"lendw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000#PCMP"
"ESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#PCMPI"
"STRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcmpistrm\t\000pextrb\t"
"\000pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000phaddw\t\000phminp"
"osuw\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t\000"
"pinsrq\t\000pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pmaxud\t\000pmaxuw\t"
"\000pminsb\t\000pminsd\t\000pminud\t\000pminuw\t\000pmovsxbd\t\000pmovs"
"xbq\t\000pmovsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pmovsxwq\t\000pmovzx"
@ -2728,7 +2720,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
printSSECC(MI, 3);
break;
case 11:
// CMPXCHG16B, MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr, MOVNTPSmr
// CMPXCHG16B, MOVDQAmr, MOVDQUmr, MOVDQUmr_Int, MOVNTPDmr_Int, MOVNTPSmr...
printi128mem(MI, 0);
break;
case 12:
@ -2789,7 +2781,7 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
return;
break;
case 21:
// MOVAPDmr, MOVAPSmr, MOVNTDQmr, MOVUPDmr, MOVUPDmr_Int, MOVUPSmr, MOVUP...
// MOVAPDmr, MOVAPSmr, MOVNTDQ_64mr, MOVNTDQmr, MOVNTDQmr_Int, MOVNTPDmr,...
printf128mem(MI, 0);
O << ", ";
printOperand(MI, 5);
@ -3374,7 +3366,7 @@ const char *X86IntelInstPrinter::getRegisterName(unsigned RegNo) {
/// from the instruction set description. This returns the enum name of the
/// specified instruction.
const char *X86IntelInstPrinter::getInstructionName(unsigned Opcode) {
assert(Opcode < 2532 && "Invalid instruction number!");
assert(Opcode < 2524 && "Invalid instruction number!");
static const unsigned InstAsmOffset[] = {
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 136,
@ -3473,91 +3465,91 @@ const char *X86IntelInstPrinter::getInstructionName(unsigned Opcode) {
13388, 13400, 13408, 13416, 13424, 13437, 13449, 13461, 13469, 13476, 13483, 13496, 13504, 13511,
13518, 13525, 13538, 13545, 13558, 13569, 13578, 13587, 13596, 13605, 13614, 13623, 13633, 13643,
13655, 13667, 13678, 13689, 13698, 13707, 13716, 13725, 13738, 13747, 13760, 13770, 13779, 13788,
13797, 13806, 13816, 13825, 13834, 13843, 13852, 13861, 13870, 13881, 13893, 13905, 13916, 13927,
13938, 13948, 13957, 13967, 13977, 13986, 13997, 14008, 14020, 14032, 14044, 14057, 14068, 14079,
14091, 14100, 14106, 14112, 14123, 14134, 14142, 14150, 14158, 14170, 14182, 14193, 14204, 14215,
14226, 14237, 14248, 14259, 14270, 14278, 14286, 14294, 14300, 14311, 14323, 14334, 14346, 14358,
14369, 14381, 14392, 14404, 14416, 14427, 14439, 14451, 14462, 14471, 14484, 14493, 14506, 14515,
14524, 14537, 14546, 14559, 14568, 14581, 14594, 14610, 14626, 14639, 14652, 14664, 14676, 14687,
14699, 14710, 14722, 14739, 14756, 14768, 14779, 14791, 14802, 14814, 14828, 14840, 14851, 14864,
14876, 14890, 14902, 14913, 14926, 14937, 14948, 14959, 14970, 14981, 14992, 15003, 15014, 15025,
15036, 15047, 15054, 15061, 15068, 15075, 15082, 15089, 15095, 15101, 15109, 15117, 15125, 15133,
15141, 15153, 15161, 15173, 15181, 15193, 15201, 15213, 15222, 15231, 15241, 15251, 15262, 15272,
15281, 15291, 15300, 15310, 15322, 15331, 15343, 15355, 15368, 15381, 15394, 15407, 15420, 15433,
15443, 15449, 15456, 15463, 15470, 15477, 15484, 15491, 15497, 15503, 15508, 15514, 15520, 15527,
15534, 15541, 15548, 15555, 15562, 15568, 15574, 15582, 15589, 15597, 15604, 15611, 15619, 15626,
15633, 15644, 15652, 15659, 15667, 15674, 15681, 15689, 15696, 15703, 15714, 15722, 15731, 15739,
15746, 15755, 15763, 15770, 15777, 15788, 15794, 15800, 15806, 15812, 15818, 15824, 15834, 15841,
15848, 15855, 15862, 15870, 15878, 15886, 15894, 15901, 15908, 15914, 15920, 15926, 15937, 15947,
15958, 15968, 15979, 15989, 16000, 16010, 16021, 16031, 16042, 16052, 16063, 16074, 16085, 16096,
16107, 16118, 16129, 16140, 16148, 16156, 16164, 16172, 16180, 16188, 16197, 16206, 16215, 16224,
16234, 16244, 16254, 16264, 16272, 16280, 16293, 16306, 16318, 16330, 16338, 16346, 16353, 16360,
16368, 16376, 16384, 16392, 16404, 16416, 16427, 16438, 16448, 16458, 16468, 16478, 16488, 16498,
16508, 16518, 16531, 16544, 16557, 16570, 16583, 16596, 16609, 16622, 16635, 16648, 16660, 16672,
16688, 16704, 16719, 16734, 16744, 16754, 16764, 16774, 16784, 16794, 16804, 16814, 16827, 16840,
16853, 16866, 16879, 16892, 16905, 16918, 16931, 16944, 16956, 16968, 16984, 17000, 17015, 17030,
17039, 17048, 17057, 17066, 17075, 17084, 17093, 17102, 17114, 17125, 17137, 17148, 17161, 17173,
17186, 17198, 17210, 17221, 17233, 17244, 17260, 17276, 17288, 17299, 17311, 17322, 17335, 17347,
17360, 17372, 17384, 17395, 17407, 17418, 17427, 17436, 17445, 17454, 17463, 17472, 17482, 17492,
17507, 17521, 17536, 17550, 17560, 17570, 17579, 17588, 17597, 17606, 17615, 17624, 17633, 17642,
17651, 17660, 17669, 17678, 17687, 17696, 17705, 17714, 17723, 17732, 17741, 17750, 17759, 17768,
17777, 17786, 17797, 17808, 17819, 17830, 17841, 17852, 17863, 17874, 17885, 17896, 17907, 17918,
17929, 17940, 17951, 17962, 17973, 17984, 17995, 18006, 18017, 18028, 18039, 18050, 18061, 18070,
18079, 18093, 18106, 18120, 18133, 18143, 18153, 18162, 18171, 18180, 18193, 18202, 18215, 18224,
18233, 18243, 18253, 18260, 18269, 18278, 18285, 18294, 18303, 18310, 18319, 18328, 18339, 18350,
18361, 18372, 18383, 18394, 18399, 18405, 18411, 18419, 18427, 18435, 18443, 18451, 18459, 18465,
18471, 18483, 18494, 18505, 18516, 18525, 18534, 18546, 18557, 18569, 18580, 18589, 18598, 18608,
18618, 18628, 18638, 18650, 18661, 18673, 18684, 18696, 18707, 18719, 18730, 18742, 18753, 18765,
18776, 18785, 18793, 18801, 18809, 18817, 18825, 18833, 18841, 18849, 18857, 18865, 18873, 18881,
18889, 18897, 18905, 18914, 18922, 18930, 18938, 18946, 18954, 18962, 18970, 18978, 18986, 18994,
19002, 19010, 19018, 19026, 19034, 19043, 19052, 19061, 19070, 19080, 19090, 19100, 19110, 19118,
19126, 19134, 19142, 19154, 19166, 19178, 19190, 19203, 19216, 19228, 19240, 19252, 19264, 19276,
19288, 19301, 19314, 19326, 19338, 19346, 19356, 19366, 19376, 19386, 19395, 19403, 19413, 19423,
19433, 19443, 19452, 19460, 19470, 19480, 19486, 19493, 19502, 19511, 19520, 19529, 19538, 19547,
19556, 19563, 19570, 19578, 19587, 19595, 19603, 19612, 19620, 19628, 19637, 19645, 19653, 19662,
19670, 19678, 19687, 19695, 19703, 19712, 19720, 19727, 19735, 19742, 19749, 19757, 19764, 19771,
19782, 19789, 19800, 19807, 19818, 19825, 19836, 19844, 19853, 19861, 19869, 19878, 19886, 19894,
19903, 19911, 19919, 19928, 19936, 19944, 19953, 19961, 19969, 19978, 19986, 19993, 20001, 20008,
20015, 20023, 20030, 20036, 20042, 20048, 20055, 20068, 20078, 20088, 20098, 20108, 20119, 20129,
20139, 20149, 20159, 20163, 20168, 20176, 20185, 20193, 20201, 20210, 20218, 20226, 20235, 20243,
20251, 20260, 20268, 20276, 20285, 20293, 20301, 20310, 20318, 20325, 20333, 20340, 20347, 20355,
20362, 20370, 20379, 20387, 20395, 20404, 20412, 20420, 20429, 20437, 20445, 20454, 20462, 20470,
20479, 20487, 20495, 20504, 20512, 20519, 20527, 20534, 20541, 20549, 20556, 20569, 20582, 20595,
20608, 20621, 20634, 20647, 20660, 20664, 20673, 20686, 20695, 20708, 20717, 20730, 20739, 20752,
20757, 20765, 20774, 20782, 20790, 20799, 20807, 20815, 20824, 20832, 20840, 20849, 20857, 20865,
20874, 20882, 20890, 20899, 20907, 20914, 20922, 20929, 20936, 20944, 20951, 20960, 20968, 20977,
20985, 20993, 21002, 21010, 21018, 21030, 21039, 21047, 21056, 21064, 21072, 21081, 21089, 21097,
21109, 21118, 21128, 21137, 21145, 21155, 21164, 21172, 21180, 21192, 21199, 21206, 21213, 21220,
21227, 21234, 21245, 21252, 21259, 21266, 21272, 21279, 21286, 21292, 21298, 21305, 21312, 21322,
21332, 21342, 21351, 21357, 21363, 21369, 21375, 21382, 21389, 21395, 21401, 21408, 21415, 21421,
21427, 21434, 21441, 21448, 21455, 21462, 21469, 21476, 21483, 21489, 21495, 21501, 21507, 21513,
21519, 21526, 21532, 21540, 21549, 21557, 21565, 21574, 21582, 21590, 21599, 21607, 21615, 21624,
21632, 21640, 21649, 21657, 21665, 21674, 21682, 21689, 21697, 21704, 21711, 21719, 21726, 21737,
21748, 21759, 21770, 21781, 21792, 21803, 21814, 21825, 21836, 21847, 21858, 21866, 21875, 21883,
21891, 21900, 21908, 21916, 21925, 21933, 21941, 21950, 21958, 21966, 21975, 21983, 21991, 22000,
22008, 22015, 22023, 22030, 22037, 22045, 22052, 22063, 22074, 22085, 22096, 22107, 22118, 22129,
22140, 22151, 22162, 22173, 22184, 22194, 22204, 22214, 22224, 22230, 22236, 22245, 22254, 22263,
22271, 22279, 22287, 22295, 22303, 22311, 22319, 22327, 22335, 22347, 22355, 22367, 22375, 22387,
22395, 22407, 22415, 22427, 22435, 22447, 22455, 22467, 22475, 22487, 22494, 22504, 22514, 22524,
22534, 22538, 22542, 22546, 22554, 22560, 22566, 22572, 22577, 22582, 22590, 22598, 22607, 22616,
22625, 22633, 22642, 22651, 22662, 22673, 22684, 22694, 22704, 22716, 22726, 22738, 22750, 22757,
22766, 22774, 22783, 22791, 22799, 22808, 22816, 22824, 22836, 22845, 22853, 22862, 22870, 22878,
22887, 22895, 22903, 22915, 22924, 22934, 22943, 22951, 22961, 22970, 22978, 22986, 22998, 23005,
23012, 23019, 23026, 23033, 23040, 23051, 23059, 23067, 23075, 23083, 23093, 23103, 23114, 23125,
23137, 23148, 23159, 23170, 23183, 23196, 23209, 23223, 23237, 23251, 23265, 23279, 23293, 23304,
23312, 23324, 23332, 23344, 23352, 23364, 23372, 23384, 23393, 23402, 23412, 23422, 23433, 23443,
23452, 23462, 23471, 23481, 23493, 23502, 23514, 23526, 23539, 23552, 23565, 23578, 23591, 23604,
23614, 23621, 23629, 23638, 23646, 23656, 23663, 23672, 23681, 23690, 23701, 23712, 23725, 23736,
23749, 23759, 23768, 23777, 23786, 23795, 23805, 23814, 23823, 23832, 23841, 23851, 23862, 23873,
23882, 23891, 23899, 23907, 23915, 23923, 23931, 23942, 23953, 23958, 23964, 23973, 23982, 23991,
24001, 24011, 24021, 24031, 24041, 24050, 24060, 24069, 24081, 24093, 24105, 24116, 24127, 24138,
24146, 24157, 24168, 24179, 24190, 24201, 24212, 24223, 24234, 24256, 24262, 24268, 24274, 24280,
24287, 24296, 24305, 24314, 24323, 24334, 24345, 24356, 24367, 24376, 24388, 24400, 24412, 24424,
24431, 24437, 24444, 24457, 24462, 24469, 24480, 24497, 24508, 24514, 24523, 24532, 24541, 24550,
24559, 24568, 24576, 24584, 24593, 24602, 24611, 24620, 24629, 24638, 24647, 24656, 24665, 24673,
24681, 24687, 24692, 24701, 24709, 24718, 24726, 24734, 24743, 24751, 24759, 24771, 24780, 24788,
24797, 24805, 24813, 24822, 24830, 24838, 24850, 24859, 24869, 24878, 24886, 24896, 24905, 24913,
24921, 24933, 24940, 24947, 24954, 24961, 24968, 24975, 24986, 24994, 25002, 25010, 0
13797, 13806, 13816, 13825, 13834, 13843, 13852, 13863, 13874, 13885, 13896, 13909, 13919, 13933,
13945, 13954, 13967, 13977, 13991, 14001, 14015, 14024, 14036, 14048, 14060, 14073, 14085, 14094,
14100, 14106, 14114, 14122, 14130, 14142, 14154, 14165, 14176, 14187, 14198, 14209, 14220, 14228,
14236, 14244, 14250, 14261, 14273, 14284, 14296, 14308, 14319, 14331, 14342, 14354, 14366, 14377,
14389, 14401, 14412, 14421, 14434, 14443, 14456, 14465, 14474, 14487, 14496, 14509, 14518, 14531,
14544, 14560, 14576, 14589, 14602, 14613, 14625, 14636, 14648, 14665, 14682, 14694, 14705, 14717,
14728, 14740, 14754, 14766, 14777, 14790, 14802, 14816, 14828, 14839, 14852, 14863, 14874, 14885,
14896, 14907, 14918, 14929, 14940, 14951, 14962, 14973, 14980, 14987, 14994, 15001, 15008, 15015,
15021, 15027, 15035, 15043, 15051, 15059, 15067, 15079, 15087, 15099, 15107, 15119, 15127, 15139,
15148, 15157, 15167, 15177, 15188, 15198, 15207, 15217, 15226, 15236, 15248, 15257, 15269, 15281,
15294, 15307, 15320, 15333, 15346, 15359, 15369, 15375, 15382, 15389, 15396, 15403, 15410, 15417,
15423, 15429, 15434, 15440, 15446, 15453, 15460, 15467, 15474, 15481, 15488, 15494, 15500, 15508,
15515, 15523, 15530, 15537, 15545, 15552, 15559, 15570, 15578, 15585, 15593, 15600, 15607, 15615,
15622, 15629, 15640, 15648, 15657, 15665, 15672, 15681, 15689, 15696, 15703, 15714, 15720, 15726,
15732, 15738, 15744, 15750, 15760, 15767, 15774, 15781, 15788, 15796, 15804, 15812, 15820, 15827,
15834, 15840, 15846, 15852, 15863, 15873, 15884, 15894, 15905, 15915, 15926, 15936, 15947, 15957,
15968, 15978, 15989, 16000, 16011, 16022, 16033, 16044, 16055, 16066, 16074, 16082, 16090, 16098,
16106, 16114, 16123, 16132, 16141, 16150, 16160, 16170, 16180, 16190, 16198, 16206, 16219, 16232,
16244, 16256, 16264, 16272, 16279, 16286, 16294, 16302, 16310, 16318, 16330, 16342, 16353, 16364,
16374, 16384, 16394, 16404, 16414, 16424, 16434, 16444, 16457, 16470, 16483, 16496, 16509, 16522,
16535, 16548, 16561, 16574, 16586, 16598, 16614, 16630, 16645, 16660, 16670, 16680, 16690, 16700,
16710, 16720, 16730, 16740, 16753, 16766, 16779, 16792, 16805, 16818, 16831, 16844, 16857, 16870,
16882, 16894, 16910, 16926, 16941, 16956, 16965, 16974, 16983, 16992, 17001, 17010, 17019, 17028,
17040, 17051, 17063, 17074, 17087, 17099, 17112, 17124, 17136, 17147, 17159, 17170, 17186, 17202,
17214, 17225, 17237, 17248, 17261, 17273, 17286, 17298, 17310, 17321, 17333, 17344, 17353, 17362,
17371, 17380, 17389, 17398, 17408, 17418, 17433, 17447, 17462, 17476, 17486, 17496, 17505, 17514,
17523, 17532, 17541, 17550, 17559, 17568, 17577, 17586, 17595, 17604, 17613, 17622, 17631, 17640,
17649, 17658, 17667, 17676, 17685, 17694, 17703, 17712, 17723, 17734, 17745, 17756, 17767, 17778,
17789, 17800, 17811, 17822, 17833, 17844, 17855, 17866, 17877, 17888, 17899, 17910, 17921, 17932,
17943, 17954, 17965, 17976, 17987, 17996, 18005, 18019, 18032, 18046, 18059, 18069, 18079, 18088,
18097, 18106, 18119, 18128, 18141, 18150, 18159, 18169, 18179, 18186, 18195, 18204, 18211, 18220,
18229, 18236, 18245, 18254, 18265, 18276, 18287, 18298, 18309, 18320, 18325, 18331, 18337, 18345,
18353, 18361, 18369, 18377, 18385, 18391, 18397, 18409, 18420, 18431, 18442, 18451, 18460, 18472,
18483, 18495, 18506, 18515, 18524, 18534, 18544, 18554, 18564, 18576, 18587, 18599, 18610, 18622,
18633, 18645, 18656, 18668, 18679, 18691, 18702, 18711, 18719, 18727, 18735, 18743, 18751, 18759,
18767, 18775, 18783, 18791, 18799, 18807, 18815, 18823, 18831, 18840, 18848, 18856, 18864, 18872,
18880, 18888, 18896, 18904, 18912, 18920, 18928, 18936, 18944, 18952, 18960, 18969, 18978, 18987,
18996, 19006, 19016, 19026, 19036, 19044, 19052, 19060, 19068, 19080, 19092, 19104, 19116, 19129,
19142, 19154, 19166, 19178, 19190, 19202, 19214, 19227, 19240, 19252, 19264, 19272, 19282, 19292,
19302, 19312, 19321, 19329, 19339, 19349, 19359, 19369, 19378, 19386, 19396, 19406, 19412, 19419,
19428, 19437, 19446, 19455, 19464, 19473, 19482, 19489, 19496, 19504, 19513, 19521, 19529, 19538,
19546, 19554, 19563, 19571, 19579, 19588, 19596, 19604, 19613, 19621, 19629, 19638, 19646, 19653,
19661, 19668, 19675, 19683, 19690, 19697, 19708, 19715, 19726, 19733, 19744, 19751, 19762, 19770,
19779, 19787, 19795, 19804, 19812, 19820, 19829, 19837, 19845, 19854, 19862, 19870, 19879, 19887,
19895, 19904, 19912, 19919, 19927, 19934, 19941, 19949, 19956, 19962, 19968, 19974, 19981, 19994,
20004, 20014, 20024, 20034, 20045, 20055, 20065, 20075, 20085, 20089, 20094, 20102, 20111, 20119,
20127, 20136, 20144, 20152, 20161, 20169, 20177, 20186, 20194, 20202, 20211, 20219, 20227, 20236,
20244, 20251, 20259, 20266, 20273, 20281, 20288, 20296, 20305, 20313, 20321, 20330, 20338, 20346,
20355, 20363, 20371, 20380, 20388, 20396, 20405, 20413, 20421, 20430, 20438, 20445, 20453, 20460,
20467, 20475, 20482, 20495, 20508, 20521, 20534, 20547, 20560, 20573, 20586, 20590, 20599, 20612,
20621, 20634, 20643, 20656, 20665, 20678, 20683, 20691, 20700, 20708, 20716, 20725, 20733, 20741,
20750, 20758, 20766, 20775, 20783, 20791, 20800, 20808, 20816, 20825, 20833, 20840, 20848, 20855,
20862, 20870, 20877, 20886, 20894, 20903, 20911, 20919, 20928, 20936, 20944, 20956, 20965, 20973,
20982, 20990, 20998, 21007, 21015, 21023, 21035, 21044, 21054, 21063, 21071, 21081, 21090, 21098,
21106, 21118, 21125, 21132, 21139, 21146, 21153, 21160, 21171, 21178, 21185, 21192, 21198, 21205,
21212, 21218, 21224, 21231, 21238, 21248, 21258, 21268, 21277, 21283, 21289, 21295, 21301, 21308,
21315, 21321, 21327, 21334, 21341, 21347, 21353, 21360, 21367, 21374, 21381, 21388, 21395, 21402,
21409, 21415, 21421, 21427, 21433, 21439, 21445, 21452, 21458, 21466, 21475, 21483, 21491, 21500,
21508, 21516, 21525, 21533, 21541, 21550, 21558, 21566, 21575, 21583, 21591, 21600, 21608, 21615,
21623, 21630, 21637, 21645, 21652, 21663, 21674, 21685, 21696, 21707, 21718, 21729, 21740, 21751,
21762, 21773, 21784, 21792, 21801, 21809, 21817, 21826, 21834, 21842, 21851, 21859, 21867, 21876,
21884, 21892, 21901, 21909, 21917, 21926, 21934, 21941, 21949, 21956, 21963, 21971, 21978, 21989,
22000, 22011, 22022, 22033, 22044, 22055, 22066, 22077, 22088, 22099, 22110, 22120, 22130, 22140,
22150, 22156, 22162, 22171, 22180, 22189, 22197, 22205, 22213, 22221, 22229, 22237, 22245, 22253,
22261, 22273, 22281, 22293, 22301, 22313, 22321, 22333, 22341, 22353, 22361, 22373, 22381, 22393,
22401, 22413, 22420, 22430, 22440, 22450, 22460, 22464, 22468, 22472, 22480, 22486, 22492, 22498,
22503, 22508, 22516, 22524, 22533, 22542, 22551, 22559, 22568, 22577, 22588, 22599, 22610, 22620,
22630, 22642, 22652, 22664, 22676, 22683, 22692, 22700, 22709, 22717, 22725, 22734, 22742, 22750,
22762, 22771, 22779, 22788, 22796, 22804, 22813, 22821, 22829, 22841, 22850, 22860, 22869, 22877,
22887, 22896, 22904, 22912, 22924, 22931, 22938, 22945, 22952, 22959, 22966, 22977, 22985, 22993,
23001, 23009, 23019, 23029, 23040, 23051, 23063, 23074, 23085, 23096, 23109, 23122, 23135, 23149,
23163, 23177, 23191, 23205, 23219, 23230, 23238, 23250, 23258, 23270, 23278, 23290, 23298, 23310,
23319, 23328, 23338, 23348, 23359, 23369, 23378, 23388, 23397, 23407, 23419, 23428, 23440, 23452,
23465, 23478, 23491, 23504, 23517, 23530, 23540, 23547, 23555, 23564, 23572, 23582, 23589, 23598,
23607, 23616, 23627, 23638, 23651, 23662, 23675, 23685, 23694, 23703, 23712, 23721, 23731, 23740,
23749, 23758, 23767, 23777, 23788, 23799, 23808, 23817, 23825, 23833, 23841, 23849, 23857, 23868,
23879, 23884, 23890, 23899, 23908, 23917, 23927, 23937, 23947, 23957, 23967, 23976, 23986, 23995,
24007, 24019, 24031, 24042, 24053, 24064, 24072, 24083, 24094, 24105, 24116, 24127, 24138, 24149,
24160, 24182, 24188, 24194, 24200, 24206, 24213, 24222, 24231, 24240, 24249, 24260, 24271, 24282,
24293, 24302, 24314, 24326, 24338, 24350, 24357, 24363, 24370, 24383, 24388, 24395, 24406, 24423,
24434, 24440, 24449, 24458, 24467, 24476, 24485, 24494, 24502, 24510, 24519, 24528, 24537, 24546,
24555, 24564, 24573, 24582, 24591, 24599, 24607, 24613, 24618, 24627, 24635, 24644, 24652, 24660,
24669, 24677, 24685, 24697, 24706, 24714, 24723, 24731, 24739, 24748, 24756, 24764, 24776, 24785,
24795, 24804, 24812, 24822, 24831, 24839, 24847, 24859, 24866, 24873, 24880, 24887, 24894, 24901,
24912, 24920, 24928, 24936, 0
};
const char *Strs =
@ -3811,57 +3803,56 @@ const char *X86IntelInstPrinter::getInstructionName(unsigned Opcode) {
"DI2SSrm\000MOVDI2SSrr\000MOVDQAmr\000MOVDQArm\000MOVDQArr\000MOVDQUmr\000"
"MOVDQUmr_Int\000MOVDQUrm\000MOVDQUrm_Int\000MOVHLPSrr\000MOVHPDmr\000MO"
"VHPDrm\000MOVHPSmr\000MOVHPSrm\000MOVLHPSrr\000MOVLPDmr\000MOVLPDrm\000"
"MOVLPDrr\000MOVLPSmr\000MOVLPSrm\000MOVLPSrr\000MOVLQ128mr\000MOVLSD2PD"
"rr\000MOVLSS2PSrr\000MOVMSKPDrr\000MOVMSKPSrr\000MOVNTDQArm\000MOVNTDQm"
"r\000MOVNTImr\000MOVNTPDmr\000MOVNTPSmr\000MOVPC32r\000MOVPD2SDmr\000MO"
"VPD2SDrr\000MOVPDI2DImr\000MOVPDI2DIrr\000MOVPQI2QImr\000MOVPQIto64rr\000"
"MOVPS2SSmr\000MOVPS2SSrr\000MOVQI2PQIrm\000MOVQxrxr\000MOVSB\000MOVSD\000"
"MOVSD2PDrm\000MOVSD2PDrr\000MOVSDmr\000MOVSDrm\000MOVSDrr\000MOVSDto64m"
"r\000MOVSDto64rr\000MOVSHDUPrm\000MOVSHDUPrr\000MOVSLDUPrm\000MOVSLDUPr"
"r\000MOVSS2DImr\000MOVSS2DIrr\000MOVSS2PSrm\000MOVSS2PSrr\000MOVSSmr\000"
"MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16rm8\000MOVSX16rm8W\000MOVSX16rr8\000"
"MOVSX16rr8W\000MOVSX32rm16\000MOVSX32rm8\000MOVSX32rr16\000MOVSX32rr8\000"
"MOVSX64rm16\000MOVSX64rm32\000MOVSX64rm8\000MOVSX64rr16\000MOVSX64rr32\000"
"MOVSX64rr8\000MOVUPDmr\000MOVUPDmr_Int\000MOVUPDrm\000MOVUPDrm_Int\000M"
"OVUPDrr\000MOVUPSmr\000MOVUPSmr_Int\000MOVUPSrm\000MOVUPSrm_Int\000MOVU"
"PSrr\000MOVZDI2PDIrm\000MOVZDI2PDIrr\000MOVZPQILo2PQIrm\000MOVZPQILo2PQ"
"Irr\000MOVZQI2PQIrm\000MOVZQI2PQIrr\000MOVZSD2PDrm\000MOVZSS2PSrm\000MO"
"VZX16rm8\000MOVZX16rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX32_NOREXrm"
"8\000MOVZX32_NOREXrr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32rr16\000MO"
"VZX32rr8\000MOVZX64rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MOVZX64rm8\000"
"MOVZX64rm8_Q\000MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32\000MOVZX64r"
"r8\000MOVZX64rr8_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp3280\000MOV_Fp6"
"432\000MOV_Fp6464\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064\000MOV_Fp80"
"80\000MPSADBWrmi\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32m\000MUL32r\000"
"MUL64m\000MUL64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr\000MULPSrm\000"
"MULPSrr\000MULSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_Int\000MULSSrm\000"
"MULSSrm_Int\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000MUL_F64m\000MUL_FI"
"16m\000MUL_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp32\000MUL_Fp32m\000"
"MUL_Fp64\000MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000MUL_Fp80m32\000MUL_"
"Fp80m64\000MUL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16m80\000MUL_FpI32m32"
"\000MUL_FpI32m64\000MUL_FpI32m80\000MUL_FrST0\000MWAIT\000NEG16m\000NEG"
"16r\000NEG32m\000NEG32r\000NEG64m\000NEG64r\000NEG8m\000NEG8r\000NOOP\000"
"NOOPL\000NOOPW\000NOT16m\000NOT16r\000NOT32m\000NOT32r\000NOT64m\000NOT"
"64r\000NOT8m\000NOT8r\000OR16i16\000OR16mi\000OR16mi8\000OR16mr\000OR16"
"ri\000OR16ri8\000OR16rm\000OR16rr\000OR16rr_REV\000OR32i32\000OR32mi\000"
"OR32mi8\000OR32mr\000OR32ri\000OR32ri8\000OR32rm\000OR32rr\000OR32rr_RE"
"V\000OR64i32\000OR64mi32\000OR64mi8\000OR64mr\000OR64ri32\000OR64ri8\000"
"OR64rm\000OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000OR8mr\000OR8ri\000O"
"R8rm\000OR8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000ORPSrm\000ORPSrr\000O"
"UT16ir\000OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000OUT8rr\000OUTSB\000"
"OUTSD\000OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr128\000PABSBrr64\000"
"PABSDrm128\000PABSDrm64\000PABSDrr128\000PABSDrr64\000PABSWrm128\000PAB"
"SWrm64\000PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PACKSSDWrr\000PACKSS"
"WBrm\000PACKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACKUSWBrm\000PACKUSW"
"Brr\000PADDBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PADDQrm\000PADDQrr\000"
"PADDSBrm\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADDUSBrm\000PADDUSBrr\000"
"PADDUSWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000PALIGNR128rm\000PALIGNR"
"128rr\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000PANDNrr\000PANDrm\000"
"PANDrr\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr\000PBLENDVBrm0\000PB"
"LENDVBrr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm\000PCMPEQBrr\000PCMP"
"EQDrm\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PCMPEQWrm\000PCMPEQWrr\000"
"PCMPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000PCMPESTRICrr\000PCMPEST"
"RIOrm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPESTRISrr\000PCMPESTRIZrm\000"
"MOVLPSmr\000MOVLPSrm\000MOVLQ128mr\000MOVMSKPDrr\000MOVMSKPSrr\000MOVNT"
"DQArm\000MOVNTDQ_64mr\000MOVNTDQmr\000MOVNTDQmr_Int\000MOVNTI_64mr\000M"
"OVNTImr\000MOVNTImr_Int\000MOVNTPDmr\000MOVNTPDmr_Int\000MOVNTPSmr\000M"
"OVNTPSmr_Int\000MOVPC32r\000MOVPDI2DImr\000MOVPDI2DIrr\000MOVPQI2QImr\000"
"MOVPQIto64rr\000MOVQI2PQIrm\000MOVQxrxr\000MOVSB\000MOVSD\000MOVSDmr\000"
"MOVSDrm\000MOVSDrr\000MOVSDto64mr\000MOVSDto64rr\000MOVSHDUPrm\000MOVSH"
"DUPrr\000MOVSLDUPrm\000MOVSLDUPrr\000MOVSS2DImr\000MOVSS2DIrr\000MOVSSm"
"r\000MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16rm8\000MOVSX16rm8W\000MOVSX1"
"6rr8\000MOVSX16rr8W\000MOVSX32rm16\000MOVSX32rm8\000MOVSX32rr16\000MOVS"
"X32rr8\000MOVSX64rm16\000MOVSX64rm32\000MOVSX64rm8\000MOVSX64rr16\000MO"
"VSX64rr32\000MOVSX64rr8\000MOVUPDmr\000MOVUPDmr_Int\000MOVUPDrm\000MOVU"
"PDrm_Int\000MOVUPDrr\000MOVUPSmr\000MOVUPSmr_Int\000MOVUPSrm\000MOVUPSr"
"m_Int\000MOVUPSrr\000MOVZDI2PDIrm\000MOVZDI2PDIrr\000MOVZPQILo2PQIrm\000"
"MOVZPQILo2PQIrr\000MOVZQI2PQIrm\000MOVZQI2PQIrr\000MOVZX16rm8\000MOVZX1"
"6rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX32_NOREXrm8\000MOVZX32_NOREX"
"rr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32rr16\000MOVZX32rr8\000MOVZX6"
"4rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MOVZX64rm8\000MOVZX64rm8_Q\000"
"MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32\000MOVZX64rr8\000MOVZX64rr8"
"_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp3280\000MOV_Fp6432\000MOV_Fp646"
"4\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064\000MOV_Fp8080\000MPSADBWrmi"
"\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32m\000MUL32r\000MUL64m\000MUL"
"64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr\000MULPSrm\000MULPSrr\000MU"
"LSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_Int\000MULSSrm\000MULSSrm_In"
"t\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000MUL_F64m\000MUL_FI16m\000MUL"
"_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp32\000MUL_Fp32m\000MUL_Fp64\000"
"MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000MUL_Fp80m32\000MUL_Fp80m64\000M"
"UL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16m80\000MUL_FpI32m32\000MUL_FpI3"
"2m64\000MUL_FpI32m80\000MUL_FrST0\000MWAIT\000NEG16m\000NEG16r\000NEG32"
"m\000NEG32r\000NEG64m\000NEG64r\000NEG8m\000NEG8r\000NOOP\000NOOPL\000N"
"OOPW\000NOT16m\000NOT16r\000NOT32m\000NOT32r\000NOT64m\000NOT64r\000NOT"
"8m\000NOT8r\000OR16i16\000OR16mi\000OR16mi8\000OR16mr\000OR16ri\000OR16"
"ri8\000OR16rm\000OR16rr\000OR16rr_REV\000OR32i32\000OR32mi\000OR32mi8\000"
"OR32mr\000OR32ri\000OR32ri8\000OR32rm\000OR32rr\000OR32rr_REV\000OR64i3"
"2\000OR64mi32\000OR64mi8\000OR64mr\000OR64ri32\000OR64ri8\000OR64rm\000"
"OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000OR8mr\000OR8ri\000OR8rm\000OR"
"8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000ORPSrm\000ORPSrr\000OUT16ir\000"
"OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000OUT8rr\000OUTSB\000OUTSD\000"
"OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr128\000PABSBrr64\000PABSDrm1"
"28\000PABSDrm64\000PABSDrr128\000PABSDrr64\000PABSWrm128\000PABSWrm64\000"
"PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PACKSSDWrr\000PACKSSWBrm\000PA"
"CKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACKUSWBrm\000PACKUSWBrr\000PAD"
"DBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PADDQrm\000PADDQrr\000PADDSBrm"
"\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADDUSBrm\000PADDUSBrr\000PADDU"
"SWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000PALIGNR128rm\000PALIGNR128rr"
"\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000PANDNrr\000PANDrm\000PANDr"
"r\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr\000PBLENDVBrm0\000PBLENDV"
"Brr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm\000PCMPEQBrr\000PCMPEQDrm"
"\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PCMPEQWrm\000PCMPEQWrr\000PC"
"MPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000PCMPESTRICrr\000PCMPESTRI"
"Orm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPESTRISrr\000PCMPESTRIZrm\000"
"PCMPESTRIZrr\000PCMPESTRIrm\000PCMPESTRIrr\000PCMPESTRM128MEM\000PCMPES"
"TRM128REG\000PCMPESTRM128rm\000PCMPESTRM128rr\000PCMPGTBrm\000PCMPGTBrr"
"\000PCMPGTDrm\000PCMPGTDrr\000PCMPGTQrm\000PCMPGTQrr\000PCMPGTWrm\000PC"

92748
libclamav/c++/X86GenDAGISel.inc
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File diff suppressed because it is too large Load Diff

20
libclamav/c++/X86GenFastISel.inc
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@ -704,30 +704,10 @@ switch (RetVT.SimpleTy) {
}
}
unsigned FastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0) {
if (RetVT.SimpleTy != MVT::v4f32)
return 0;
if ((Subtarget->hasSSE1())) {
return FastEmitInst_r(X86::MOVSS2PSrr, X86::VR128RegisterClass, Op0);
}
return 0;
}
unsigned FastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(MVT RetVT, unsigned Op0) {
if (RetVT.SimpleTy != MVT::v2f64)
return 0;
if ((Subtarget->hasSSE2())) {
return FastEmitInst_r(X86::MOVSD2PDrr, X86::VR128RegisterClass, Op0);
}
return 0;
}
unsigned FastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0) {
switch (VT.SimpleTy) {
case MVT::i32: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0);
case MVT::i64: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(RetVT, Op0);
case MVT::f32: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0);
case MVT::f64: return FastEmit_ISD_SCALAR_TO_VECTOR_MVT_f64_r(RetVT, Op0);
default: return 0;
}
}

2432
libclamav/c++/X86GenInstrInfo.inc
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File diff suppressed because it is too large Load Diff

2352
libclamav/c++/X86GenInstrNames.inc
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File diff suppressed because it is too large Load Diff

512
libclamav/c++/X86GenRegisterInfo.inc
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File diff suppressed because it is too large Load Diff

0
libclamav/c++/llvm/docs/doxygen.cfg.in
Unescape View File

12
libclamav/c++/strip-llvm.sh
Unescape View File

@ -8,6 +8,7 @@ for i in llvm/bindings/ llvm/examples/ llvm/projects/ llvm/runtime/\
llvm/lib/Target/CellSPU/ llvm/lib/Target/CppBackend/ llvm/lib/Target/Mips\
llvm/lib/Target/MSIL llvm/lib/Target/MSP430/ llvm/lib/Target/PIC16\
llvm/lib/Target/Sparc/ llvm/lib/Target/SystemZ llvm/lib/Target/XCore\
llvm/lib/Target/MBlaze/ llvm/lib/Target/PIC16/ llvm/lib/Target/MSP430\
llvm/test/Archive/ llvm/test/Bindings/ llvm/test/Bitcode/ llvm/test/DebugInfo/\
llvm/test/FrontendAda/ llvm/test/FrontendC llvm/test/FrontendC++/\
llvm/test/FrontendFortran/ llvm/test/FrontendObjC\
@ -23,12 +24,13 @@ for i in llvm/bindings/ llvm/examples/ llvm/projects/ llvm/runtime/\
llvm/tools/llvm-extract llvm/tools/llvm-ld llvm/tools/llvm-link llvm/tools/llvm-mc\
llvm/tools/llvm-nm llvm/tools/llvm-prof llvm/tools/llvm-ranlib\
llvm/tools/llvm-stub llvm/tools/lto llvm/tools/opt llvm/lib/MC/MCParser\
llvm/tools/llvm-dis/Makefile
llvm/tools/llvm-dis/Makefile llvm/tools/edis/ llvm/tools/llvm-shlib\
llvm/docs
do
git rm -rf $i;
done
# LLVM's config.status depends on these files existing
mkdir -p llvm/lib/Target/PIC16/AsmPrinter llvm/lib/Target/MSP430/AsmPrinter
touch llvm/lib/Target/PIC16/AsmPrinter/Makefile llvm/lib/Target/MSP430/AsmPrinter/Makefile
git add -f llvm/lib/Target/PIC16/AsmPrinter/Makefile llvm/lib/Target/MSP430/AsmPrinter/Makefile
# config.status needs these
mkdir -p llvm/docs/doxygen
touch llvm/docs/doxygen.cfg.in
git add llvm/docs/doxygen.cfg.in
mv ../../.git/SQUASH_MSG ../../.git/MERGE_MSG

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