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Update autogenerated files after LLVM import.

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0.96
Török Edvin 15 years ago
parent 91a09b9436
commit f728ee7f09
20 changed files with 40514 additions and 38155 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 4200
      libclamav/c++/ARMGenAsmWriter.inc
  2. 182
      libclamav/c++/ARMGenCodeEmitter.inc
  3. 247
      libclamav/c++/ARMGenDAGISel.inc
  4. 3315
      libclamav/c++/ARMGenInstrInfo.inc
  5. 3019
      libclamav/c++/ARMGenInstrNames.inc
  6. 8
      libclamav/c++/ARMGenRegisterInfo.inc
  7. 22
      libclamav/c++/Makefile.am
  8. 287
      libclamav/c++/Makefile.in
  9. 1181
      libclamav/c++/PPCGenAsmWriter.inc
  10. 534
      libclamav/c++/PPCGenDAGISel.inc
  11. 2
      libclamav/c++/PPCGenInstrInfo.inc
  12. 2
      libclamav/c++/PPCGenInstrNames.inc
  13. 4293
      libclamav/c++/X86GenAsmMatcher.inc
  14. 5669
      libclamav/c++/X86GenAsmWriter.inc
  15. 5522
      libclamav/c++/X86GenAsmWriter1.inc
  16. 41920
      libclamav/c++/X86GenDAGISel.inc
  17. 4192
      libclamav/c++/X86GenInstrInfo.inc
  18. 4045
      libclamav/c++/X86GenInstrNames.inc
  19. 20
      libclamav/c++/X86GenRegisterInfo.inc
  20. 9
      libclamav/c++/llvm/include/llvm/Intrinsics.gen

4200
libclamav/c++/ARMGenAsmWriter.inc
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File diff suppressed because it is too large Load Diff

182
libclamav/c++/ARMGenCodeEmitter.inc
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@ -66,6 +66,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
62914560U, // BICri
29360128U, // BICrr
29360128U, // BICrs
18874480U, // BKPT
3942645760U, // BL
19922736U, // BLX
19922736U, // BLXr9
@ -77,9 +78,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
118550528U, // BR_JTm
27324416U, // BR_JTr
19922704U, // BX
18874400U, // BXJ
19922718U, // BX_RET
19922704U, // BXr9
167772160U, // Bcc
234881024U, // CDP
4261412864U, // CDP2
24055568U, // CLZ
57671680U, // CMNzri
24117248U, // CMNzrr
@ -91,6 +95,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
22020096U, // CMPzrr
22020096U, // CMPzrs
0U, // CONSTPOOL_ENTRY
4043309056U, // CPS
52429040U, // DBG
35651584U, // EORri
2097152U, // EORrr
2097152U, // EORrs
@ -106,6 +112,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
135266304U, // LDM_RET
84934656U, // LDR
89128960U, // LDRB
74448896U, // LDRBT
72351744U, // LDRB_POST
91226112U, // LDRB_PRE
16777424U, // LDRD
@ -122,11 +129,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
17826032U, // LDRSH
3145968U, // LDRSH_POST
19923184U, // LDRSH_PRE
70254592U, // LDRT
68157440U, // LDR_POST
87031808U, // LDR_PRE
84934656U, // LDRcp
0U, // LEApcrel
33554432U, // LEApcrelJT
234881040U, // MCR
4261412880U, // MCR2
205520896U, // MCRR
4232052736U, // MCRR2
2097296U, // MLA
6291600U, // MLS
60817408U, // MOVCCi
@ -142,10 +154,19 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
27262976U, // MOVs
27262976U, // MOVsra_flag
27262976U, // MOVsrl_flag
235929616U, // MRC
4262461456U, // MRC2
206569472U, // MRRC
4233101312U, // MRRC2
16777216U, // MRS
20971520U, // MRSsys
18874368U, // MSR
23068672U, // MSRsys
144U, // MUL
65011712U, // MVNi
31457280U, // MVNr
31457280U, // MVNs
52428800U, // NOP
58720256U, // ORRri
25165824U, // ORRrr
25165824U, // ORRrs
@ -160,6 +181,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
16777392U, // PICSTRH
109051920U, // PKHBT
109051984U, // PKHTB
16777296U, // QADD
102760464U, // QADD16
102760592U, // QADD8
102760496U, // QASX
20971600U, // QDADD
23068752U, // QDSUB
102760528U, // QSAX
18874448U, // QSUB
102760560U, // QSUB16
102760688U, // QSUB8
117378864U, // RBIT
113184560U, // REV
113184688U, // REV16
@ -179,9 +210,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
12582912U, // SBCrr
12582912U, // SBCrs
127926352U, // SBFX
4043375104U, // SETENDBE
4043374592U, // SETENDLE
52428804U, // SEV
16777344U, // SMLABB
16777408U, // SMLABT
14680208U, // SMLAL
20971648U, // SMLALBB
20971712U, // SMLALBT
20971680U, // SMLALTB
20971744U, // SMLALTT
16777376U, // SMLATB
16777440U, // SMLATT
18874496U, // SMLAWB
@ -199,6 +237,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
134217728U, // STM
83886080U, // STR
88080384U, // STRB
73400320U, // STRBT
71303168U, // STRB_POST
90177536U, // STRB_PRE
16777456U, // STRD
@ -209,6 +248,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
16777392U, // STRH
2097328U, // STRH_POST
18874544U, // STRH_PRE
69206016U, // STRT
67108864U, // STR_POST
85983232U, // STR_PRE
38797312U, // SUBSri
@ -217,6 +257,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
37748736U, // SUBri
4194304U, // SUBrr
4194304U, // SUBrs
251658240U, // SVC
16777360U, // SWP
20971664U, // SWPB
111149168U, // SXTABrr
111149168U, // SXTABrr_rot
112197744U, // SXTAHrr
@ -229,6 +272,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
19922944U, // TEQrr
19922944U, // TEQrs
184549376U, // TPsoft
133169392U, // TRAP
51380224U, // TSTri
17825792U, // TSTrr
17825792U, // TSTrs
@ -236,6 +280,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4194448U, // UMAAL
10485904U, // UMLAL
8388752U, // UMULL
106954768U, // UQADD16
106954896U, // UQADD8
106954800U, // UQASX
106954832U, // UQSAX
106954864U, // UQSUB16
106954992U, // UQSUB8
115343472U, // UXTABrr
115343472U, // UXTABrr_rot
116392048U, // UXTAHrr
@ -331,6 +381,10 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4060086608U, // VANDq
4061135120U, // VBICd
4061135184U, // VBICq
4080009488U, // VBIFd
4080009552U, // VBIFq
4078960912U, // VBITd
4078960976U, // VBITq
4077912336U, // VBSLd
4077912400U, // VBSLq
4060089856U, // VCEQfd
@ -381,14 +435,22 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4088923328U, // VCLZv4i32
4088661184U, // VCLZv8i16
4088398976U, // VCLZv8i8
246680384U, // VCMPD
246680512U, // VCMPED
246680256U, // VCMPES
246746048U, // VCMPEZD
246745792U, // VCMPEZS
246680128U, // VCMPS
246745920U, // VCMPZD
246745664U, // VCMPZS
4088399104U, // VCNTd
4088399168U, // VCNTq
246614592U, // VCVTBHS
246549056U, // VCVTBSH
246876864U, // VCVTDS
246877120U, // VCVTSD
246614720U, // VCVTTHS
246549184U, // VCVTTSH
4089120512U, // VCVTf2sd
4089120512U, // VCVTf2sd_sfp
4089120576U, // VCVTf2sq
@ -626,9 +688,11 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4088529408U, // VMOVNv8i8
4062183760U, // VMOVQ
206572304U, // VMOVRRD
206572048U, // VMOVRRS
235932176U, // VMOVRS
246417984U, // VMOVS
234883600U, // VMOVSR
205523472U, // VMOVSRR
246417984U, // VMOVScc
4068478544U, // VMOVv16i8
4068478512U, // VMOVv1i64
@ -638,6 +702,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4068474960U, // VMOVv4i32
4068477008U, // VMOVv8i16
4068478480U, // VMOVv8i8
250677776U, // VMRS
249629200U, // VMSR
236980992U, // VMULD
4068478464U, // VMULLp
4070574656U, // VMULLslsv2i32
@ -1040,6 +1106,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4087349328U, // VSHRuv4i32
4086300752U, // VSHRuv8i16
4085776400U, // VSHRuv8i8
247073600U, // VSHTOD
247073344U, // VSHTOS
246942656U, // VSITOD
246942400U, // VSITOS
4085777744U, // VSLIv16i8
@ -1050,6 +1118,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4087350608U, // VSLIv4i32
4086302032U, // VSLIv8i16
4085777680U, // VSLIv8i8
247073728U, // VSLTOD
247073472U, // VSLTOS
246483904U, // VSQRTD
246483648U, // VSQRTS
4068999504U, // VSRAsv16i8
@ -1175,10 +1245,22 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4088400192U, // VTBX2
4088400448U, // VTBX3
4088400704U, // VTBX4
247335744U, // VTOSHD
247335488U, // VTOSHS
247270208U, // VTOSIRD
247269952U, // VTOSIRS
247270336U, // VTOSIZD
247270080U, // VTOSIZS
247335872U, // VTOSLD
247335616U, // VTOSLS
247401280U, // VTOUHD
247401024U, // VTOUHS
247204672U, // VTOUIRD
247204416U, // VTOUIRS
247204800U, // VTOUIZD
247204544U, // VTOUIZS
247401408U, // VTOULD
247401152U, // VTOULS
4088791168U, // VTRNd16
4089053312U, // VTRNd32
4088529024U, // VTRNd8
@ -1191,8 +1273,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4062185552U, // VTSTv4i32
4061136976U, // VTSTv8i16
4060088336U, // VTSTv8i8
247139136U, // VUHTOD
247138880U, // VUHTOS
246942528U, // VUITOD
246942272U, // VUITOS
247139264U, // VULTOD
247139008U, // VULTOS
4088791296U, // VUZPd16
4089053440U, // VUZPd32
4088529152U, // VUZPd8
@ -1205,6 +1291,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4088791488U, // VZIPq16
4089053632U, // VZIPq32
4088529344U, // VZIPq8
52428802U, // WFE
52428803U, // WFI
52428801U, // YIELD
4048551936U, // t2ADCSri
3947888640U, // t2ADCSrr
3947888640U, // t2ADCSrs
@ -1228,6 +1317,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
4198559744U, // t2ASRrr
4026568704U, // t2B
4084137984U, // t2BFC
4083154944U, // t2BFI
4028628992U, // t2BICri
3927965696U, // t2BICrr
3927965696U, // t2BICrs
@ -1441,6 +1531,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
16640U, // tASRrr
57344U, // tB
17280U, // tBIC
48640U, // tBKPT
4026585088U, // tBL
4026580992U, // tBLXi
4026580992U, // tBLXi_r9
@ -1581,6 +1672,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::BICri:
case ARM::BICrr:
case ARM::BICrs:
case ARM::BKPT:
case ARM::BL:
case ARM::BLX:
case ARM::BLXr9:
@ -1592,9 +1684,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::BR_JTm:
case ARM::BR_JTr:
case ARM::BX:
case ARM::BXJ:
case ARM::BX_RET:
case ARM::BXr9:
case ARM::Bcc:
case ARM::CDP:
case ARM::CDP2:
case ARM::CLZ:
case ARM::CMNzri:
case ARM::CMNzrr:
@ -1606,6 +1701,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::CMPzrr:
case ARM::CMPzrs:
case ARM::CONSTPOOL_ENTRY:
case ARM::CPS:
case ARM::DBG:
case ARM::EORri:
case ARM::EORrr:
case ARM::EORrs:
@ -1621,6 +1718,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::LDM_RET:
case ARM::LDR:
case ARM::LDRB:
case ARM::LDRBT:
case ARM::LDRB_POST:
case ARM::LDRB_PRE:
case ARM::LDRD:
@ -1637,11 +1735,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::LDRSH:
case ARM::LDRSH_POST:
case ARM::LDRSH_PRE:
case ARM::LDRT:
case ARM::LDR_POST:
case ARM::LDR_PRE:
case ARM::LDRcp:
case ARM::LEApcrel:
case ARM::LEApcrelJT:
case ARM::MCR:
case ARM::MCR2:
case ARM::MCRR:
case ARM::MCRR2:
case ARM::MLA:
case ARM::MLS:
case ARM::MOVCCi:
@ -1657,10 +1760,19 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::MOVs:
case ARM::MOVsra_flag:
case ARM::MOVsrl_flag:
case ARM::MRC:
case ARM::MRC2:
case ARM::MRRC:
case ARM::MRRC2:
case ARM::MRS:
case ARM::MRSsys:
case ARM::MSR:
case ARM::MSRsys:
case ARM::MUL:
case ARM::MVNi:
case ARM::MVNr:
case ARM::MVNs:
case ARM::NOP:
case ARM::ORRri:
case ARM::ORRrr:
case ARM::ORRrs:
@ -1675,6 +1787,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::PICSTRH:
case ARM::PKHBT:
case ARM::PKHTB:
case ARM::QADD:
case ARM::QADD16:
case ARM::QADD8:
case ARM::QASX:
case ARM::QDADD:
case ARM::QDSUB:
case ARM::QSAX:
case ARM::QSUB:
case ARM::QSUB16:
case ARM::QSUB8:
case ARM::RBIT:
case ARM::REV:
case ARM::REV16:
@ -1694,9 +1816,16 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::SBCrr:
case ARM::SBCrs:
case ARM::SBFX:
case ARM::SETENDBE:
case ARM::SETENDLE:
case ARM::SEV:
case ARM::SMLABB:
case ARM::SMLABT:
case ARM::SMLAL:
case ARM::SMLALBB:
case ARM::SMLALBT:
case ARM::SMLALTB:
case ARM::SMLALTT:
case ARM::SMLATB:
case ARM::SMLATT:
case ARM::SMLAWB:
@ -1714,6 +1843,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::STM:
case ARM::STR:
case ARM::STRB:
case ARM::STRBT:
case ARM::STRB_POST:
case ARM::STRB_PRE:
case ARM::STRD:
@ -1724,6 +1854,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::STRH:
case ARM::STRH_POST:
case ARM::STRH_PRE:
case ARM::STRT:
case ARM::STR_POST:
case ARM::STR_PRE:
case ARM::SUBSri:
@ -1732,6 +1863,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::SUBri:
case ARM::SUBrr:
case ARM::SUBrs:
case ARM::SVC:
case ARM::SWP:
case ARM::SWPB:
case ARM::SXTABrr:
case ARM::SXTABrr_rot:
case ARM::SXTAHrr:
@ -1744,6 +1878,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::TEQrr:
case ARM::TEQrs:
case ARM::TPsoft:
case ARM::TRAP:
case ARM::TSTri:
case ARM::TSTrr:
case ARM::TSTrs:
@ -1751,6 +1886,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::UMAAL:
case ARM::UMLAL:
case ARM::UMULL:
case ARM::UQADD16:
case ARM::UQADD8:
case ARM::UQASX:
case ARM::UQSAX:
case ARM::UQSUB16:
case ARM::UQSUB8:
case ARM::UXTABrr:
case ARM::UXTABrr_rot:
case ARM::UXTAHrr:
@ -1846,6 +1987,10 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VANDq:
case ARM::VBICd:
case ARM::VBICq:
case ARM::VBIFd:
case ARM::VBIFq:
case ARM::VBITd:
case ARM::VBITq:
case ARM::VBSLd:
case ARM::VBSLq:
case ARM::VCEQfd:
@ -1896,14 +2041,22 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VCLZv4i32:
case ARM::VCLZv8i16:
case ARM::VCLZv8i8:
case ARM::VCMPD:
case ARM::VCMPED:
case ARM::VCMPES:
case ARM::VCMPEZD:
case ARM::VCMPEZS:
case ARM::VCMPS:
case ARM::VCMPZD:
case ARM::VCMPZS:
case ARM::VCNTd:
case ARM::VCNTq:
case ARM::VCVTBHS:
case ARM::VCVTBSH:
case ARM::VCVTDS:
case ARM::VCVTSD:
case ARM::VCVTTHS:
case ARM::VCVTTSH:
case ARM::VCVTf2sd:
case ARM::VCVTf2sd_sfp:
case ARM::VCVTf2sq:
@ -2141,9 +2294,11 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VMOVNv8i8:
case ARM::VMOVQ:
case ARM::VMOVRRD:
case ARM::VMOVRRS:
case ARM::VMOVRS:
case ARM::VMOVS:
case ARM::VMOVSR:
case ARM::VMOVSRR:
case ARM::VMOVScc:
case ARM::VMOVv16i8:
case ARM::VMOVv1i64:
@ -2153,6 +2308,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VMOVv4i32:
case ARM::VMOVv8i16:
case ARM::VMOVv8i8:
case ARM::VMRS:
case ARM::VMSR:
case ARM::VMULD:
case ARM::VMULLp:
case ARM::VMULLslsv2i32:
@ -2555,6 +2712,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VSHRuv4i32:
case ARM::VSHRuv8i16:
case ARM::VSHRuv8i8:
case ARM::VSHTOD:
case ARM::VSHTOS:
case ARM::VSITOD:
case ARM::VSITOS:
case ARM::VSLIv16i8:
@ -2565,6 +2724,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VSLIv4i32:
case ARM::VSLIv8i16:
case ARM::VSLIv8i8:
case ARM::VSLTOD:
case ARM::VSLTOS:
case ARM::VSQRTD:
case ARM::VSQRTS:
case ARM::VSRAsv16i8:
@ -2690,10 +2851,22 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VTBX2:
case ARM::VTBX3:
case ARM::VTBX4:
case ARM::VTOSHD:
case ARM::VTOSHS:
case ARM::VTOSIRD:
case ARM::VTOSIRS:
case ARM::VTOSIZD:
case ARM::VTOSIZS:
case ARM::VTOSLD:
case ARM::VTOSLS:
case ARM::VTOUHD:
case ARM::VTOUHS:
case ARM::VTOUIRD:
case ARM::VTOUIRS:
case ARM::VTOUIZD:
case ARM::VTOUIZS:
case ARM::VTOULD:
case ARM::VTOULS:
case ARM::VTRNd16:
case ARM::VTRNd32:
case ARM::VTRNd8:
@ -2706,8 +2879,12 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VTSTv4i32:
case ARM::VTSTv8i16:
case ARM::VTSTv8i8:
case ARM::VUHTOD:
case ARM::VUHTOS:
case ARM::VUITOD:
case ARM::VUITOS:
case ARM::VULTOD:
case ARM::VULTOS:
case ARM::VUZPd16:
case ARM::VUZPd32:
case ARM::VUZPd8:
@ -2720,6 +2897,9 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::VZIPq16:
case ARM::VZIPq32:
case ARM::VZIPq8:
case ARM::WFE:
case ARM::WFI:
case ARM::YIELD:
case ARM::t2ADCSri:
case ARM::t2ADCSrr:
case ARM::t2ADCSrs:
@ -2743,6 +2923,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::t2ASRrr:
case ARM::t2B:
case ARM::t2BFC:
case ARM::t2BFI:
case ARM::t2BICri:
case ARM::t2BICrr:
case ARM::t2BICrs:
@ -2956,6 +3137,7 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::tASRrr:
case ARM::tB:
case ARM::tBIC:
case ARM::tBKPT:
case ARM::tBL:
case ARM::tBLXi:
case ARM::tBLXi_r9:

247
libclamav/c++/ARMGenDAGISel.inc
Unescape View File

@ -2741,38 +2741,45 @@ SDNode *Select_ARMISD_CMPZ(SDNode *N) {
DISABLE_INLINE SDNode *Emit_29(SDNode *N, unsigned Opc0) {
SDValue N0 = N->getOperand(0);
return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0);
SDValue N1 = N->getOperand(1);
return CurDAG->SelectNodeTo(N, Opc0, MVT::i32, N0, N1);
}
SDNode *Select_ARMISD_EH_SJLJ_SETJMP_i32(SDNode *N) {
// Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src)
// Emits: (Int_eh_sjlj_setjmp:isVoid GPR:i32:$src)
// Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src, GPR:i32:$val)
// Emits: (Int_eh_sjlj_setjmp:isVoid GPR:i32:$src, GPR:i32:$val)
// Pattern complexity = 3 cost = 1 size = 0
if ((!Subtarget->isThumb())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32 &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_29(N, ARM::Int_eh_sjlj_setjmp);
return Result;
}
}
// Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src)
// Emits: (tInt_eh_sjlj_setjmp:isVoid GPR:i32:$src)
// Pattern: (ARMeh_sjlj_setjmp:i32 tGPR:i32:$src, tGPR:i32:$val)
// Emits: (tInt_eh_sjlj_setjmp:isVoid tGPR:i32:$src, tGPR:i32:$val)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32 &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_29(N, ARM::tInt_eh_sjlj_setjmp);
return Result;
}
}
// Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src)
// Emits: (t2Int_eh_sjlj_setjmp:isVoid GPR:i32:$src)
// Pattern: (ARMeh_sjlj_setjmp:i32 GPR:i32:$src, tGPR:i32:$val)
// Emits: (t2Int_eh_sjlj_setjmp:isVoid GPR:i32:$src, tGPR:i32:$val)
// Pattern complexity = 3 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDValue N1 = N->getOperand(1);
if (N0.getValueType() == MVT::i32 &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_29(N, ARM::t2Int_eh_sjlj_setjmp);
return Result;
}
@ -2848,7 +2855,7 @@ SDNode *Select_ARMISD_FTOSI_f32(SDNode *N) {
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTf2sd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VCVTf2sd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
}
@ -2887,7 +2894,7 @@ SDNode *Select_ARMISD_FTOUI_f32(SDNode *N) {
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTf2ud_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VCVTf2ud_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
}
@ -2969,54 +2976,52 @@ DISABLE_INLINE SDNode *Emit_37(SDNode *N, unsigned Opc0, MVT::SimpleValueType VT
return ResNode;
}
SDNode *Select_ARMISD_PIC_ADD_i32(SDNode *N) {
if (OptLevel != CodeGenOpt::None) {
// Pattern: (ARMpic_add:i32 (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$cp)
// Emits: (tLDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
// Pattern complexity = 16 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
if (N01.getNode()->getOpcode() == ARMISD::Wrapper) {
SDValue N010 = N01.getNode()->getOperand(0);
if (N010.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_37(N, ARM::tLDRpci_pic, MVT::i32);
return Result;
}
// Pattern: (ARMpic_add:i32 (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$cp)
// Emits: (tLDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
// Pattern complexity = 16 cost = 1 size = 0
if ((Subtarget->isThumb1Only())) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
if (N01.getNode()->getOpcode() == ARMISD::Wrapper) {
SDValue N010 = N01.getNode()->getOperand(0);
if (N010.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_37(N, ARM::tLDRpci_pic, MVT::i32);
return Result;
}
}
}
}
}
}
// Pattern: (ARMpic_add:i32 (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$cp)
// Emits: (t2LDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
// Pattern complexity = 16 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
if (N01.getNode()->getOpcode() == ARMISD::Wrapper) {
SDValue N010 = N01.getNode()->getOperand(0);
if (N010.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_37(N, ARM::t2LDRpci_pic, MVT::i32);
return Result;
}
// Pattern: (ARMpic_add:i32 (ld:i32 (ARMWrapper:iPTR (tconstpool:iPTR):$addr))<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i32):$cp)
// Emits: (t2LDRpci_pic:i32 (tconstpool:i32):$addr, (imm:i32):$cp)
// Pattern complexity = 16 cost = 1 size = 0
if ((Subtarget->isThumb2())) {
SDValue N0 = N->getOperand(0);
if (N0.getNode()->getOpcode() == ISD::LOAD &&
N0.hasOneUse() &&
IsLegalAndProfitableToFold(N0.getNode(), N, N)) {
SDValue Chain0 = N0.getNode()->getOperand(0);
if (Predicate_unindexedload(N0.getNode()) &&
Predicate_load(N0.getNode())) {
SDValue N01 = N0.getNode()->getOperand(1);
if (N01.getNode()->getOpcode() == ARMISD::Wrapper) {
SDValue N010 = N01.getNode()->getOperand(0);
if (N010.getNode()->getOpcode() == ISD::TargetConstantPool) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_37(N, ARM::t2LDRpci_pic, MVT::i32);
return Result;
}
}
}
@ -3163,7 +3168,7 @@ SDNode *Select_ARMISD_SITOF_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VCVTs2fd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2i32), SPR:f32:$a, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 4 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTs2fd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2i32, MVT::f64, MVT::f64, MVT::f32);
SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VCVTs2fd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2i32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@ -3322,7 +3327,7 @@ SDNode *Select_ARMISD_UITOF_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VCVTu2fd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2i32), SPR:f32:$a, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 4 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VCVTu2fd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2i32, MVT::f64, MVT::f64, MVT::f32);
SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VCVTu2fd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2i32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@ -4032,7 +4037,7 @@ SDNode *Select_ARMISD_VDUPLANE_v16i8(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_46(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLN8q, MVT::v8i8, MVT::v16i8);
SDNode *Result = Emit_46(N, TargetOpcode::EXTRACT_SUBREG, ARM::VDUPLN8q, MVT::v8i8, MVT::v16i8);
return Result;
}
@ -4089,7 +4094,7 @@ SDNode *Select_ARMISD_VDUPLANE_v8i16(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_47(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLN16q, MVT::v4i16, MVT::v8i16);
SDNode *Result = Emit_47(N, TargetOpcode::EXTRACT_SUBREG, ARM::VDUPLN16q, MVT::v4i16, MVT::v8i16);
return Result;
}
@ -4146,7 +4151,7 @@ SDNode *Select_ARMISD_VDUPLANE_v4i32(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_48(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLN32q, MVT::v2i32, MVT::v4i32);
SDNode *Result = Emit_48(N, TargetOpcode::EXTRACT_SUBREG, ARM::VDUPLN32q, MVT::v2i32, MVT::v4i32);
return Result;
}
@ -4168,7 +4173,7 @@ SDNode *Select_ARMISD_VDUPLANE_v2i64(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2i64) {
SDNode *Result = Emit_49(N, TargetInstrInfo::EXTRACT_SUBREG, TargetInstrInfo::INSERT_SUBREG, MVT::i64, MVT::v2i64);
SDNode *Result = Emit_49(N, TargetOpcode::EXTRACT_SUBREG, TargetOpcode::INSERT_SUBREG, MVT::i64, MVT::v2i64);
return Result;
}
@ -4213,7 +4218,7 @@ SDNode *Select_ARMISD_VDUPLANE_v4f32(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_48(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VDUPLNfq, MVT::v2f32, MVT::v4f32);
SDNode *Result = Emit_48(N, TargetOpcode::EXTRACT_SUBREG, ARM::VDUPLNfq, MVT::v2f32, MVT::v4f32);
return Result;
}
@ -4226,7 +4231,7 @@ SDNode *Select_ARMISD_VDUPLANE_v2f64(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2f64) {
SDNode *Result = Emit_49(N, TargetInstrInfo::EXTRACT_SUBREG, TargetInstrInfo::INSERT_SUBREG, MVT::f64, MVT::v2f64);
SDNode *Result = Emit_49(N, TargetOpcode::EXTRACT_SUBREG, TargetOpcode::INSERT_SUBREG, MVT::f64, MVT::v2f64);
return Result;
}
@ -4395,7 +4400,7 @@ SDNode *Select_ARMISD_VGETLANEs_i32(SDNode *N) {
// Emits: (VGETLNs8:i32 (EXTRACT_SUBREG:v8i8 QPR:v16i8:$src, (DSubReg_i8_reg:i32 (imm:i32):$lane)), (SubReg_i8_lane:i32 (imm:i32):$lane))
// Pattern complexity = 6 cost = 2 size = 0
if (N0.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_46(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNs8, MVT::v8i8, MVT::i32);
SDNode *Result = Emit_46(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNs8, MVT::v8i8, MVT::i32);
return Result;
}
@ -4403,7 +4408,7 @@ SDNode *Select_ARMISD_VGETLANEs_i32(SDNode *N) {
// Emits: (VGETLNs16:i32 (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 6 cost = 2 size = 0
if (N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_47(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNs16, MVT::v4i16, MVT::i32);
SDNode *Result = Emit_47(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNs16, MVT::v4i16, MVT::i32);
return Result;
}
}
@ -4443,7 +4448,7 @@ SDNode *Select_ARMISD_VGETLANEu_i32(SDNode *N) {
// Emits: (VGETLNu8:i32 (EXTRACT_SUBREG:v8i8 QPR:v16i8:$src, (DSubReg_i8_reg:i32 (imm:i32):$lane)), (SubReg_i8_lane:i32 (imm:i32):$lane))
// Pattern complexity = 6 cost = 2 size = 0
if (N0.getValueType() == MVT::v16i8) {
SDNode *Result = Emit_46(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNu8, MVT::v8i8, MVT::i32);
SDNode *Result = Emit_46(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNu8, MVT::v8i8, MVT::i32);
return Result;
}
@ -4451,7 +4456,7 @@ SDNode *Select_ARMISD_VGETLANEu_i32(SDNode *N) {
// Emits: (VGETLNu16:i32 (EXTRACT_SUBREG:v4i16 QPR:v16i8:$src, (DSubReg_i16_reg:i32 (imm:i32):$lane)), (SubReg_i16_lane:i32 (imm:i32):$lane))
// Pattern complexity = 6 cost = 2 size = 0
if (N0.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_47(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNu16, MVT::v4i16, MVT::i32);
SDNode *Result = Emit_47(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNu16, MVT::v4i16, MVT::i32);
return Result;
}
}
@ -11329,7 +11334,7 @@ SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_133(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
SDNode *Result = Emit_133(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@ -11344,7 +11349,7 @@ SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
if (N101.getNode()->getOpcode() == ISD::Constant) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_134(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
SDNode *Result = Emit_134(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@ -11365,7 +11370,7 @@ SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
if (N011.getNode()->getOpcode() == ISD::Constant) {
SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_135(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
SDNode *Result = Emit_135(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@ -11382,7 +11387,7 @@ SDNode *Select_ISD_ADD_v8i16(SDNode *N) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_136(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
SDNode *Result = Emit_136(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@ -11891,7 +11896,7 @@ SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
SDNode *Result = Emit_137(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@ -11906,7 +11911,7 @@ SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
if (N101.getNode()->getOpcode() == ISD::Constant) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
SDNode *Result = Emit_138(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@ -11927,7 +11932,7 @@ SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
if (N011.getNode()->getOpcode() == ISD::Constant) {
SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_139(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
SDNode *Result = Emit_139(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@ -11944,7 +11949,7 @@ SDNode *Select_ISD_ADD_v4i32(SDNode *N) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_140(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
SDNode *Result = Emit_140(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@ -15612,7 +15617,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_i32(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_48(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VGETLNi32, MVT::v2i32, MVT::i32);
SDNode *Result = Emit_48(N, TargetOpcode::EXTRACT_SUBREG, ARM::VGETLNi32, MVT::v2i32, MVT::i32);
return Result;
}
@ -15647,7 +15652,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (COPY_TO_REGCLASS:v2f32 DPR:v2f32:$src1, DPR_VFP2:f64), (SSubReg_f32_reg:i32 (imm:i32):$src2))
// Pattern complexity = 6 cost = 2 size = 0
if (N0.getValueType() == MVT::v2f32) {
SDNode *Result = Emit_202(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f32);
SDNode *Result = Emit_202(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f32);
return Result;
}
@ -15655,7 +15660,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (COPY_TO_REGCLASS:v4f32 QPR:v4f32:$src1, QPR_VFP2:v16i8), (SSubReg_f32_reg:i32 (imm:i32):$src2))
// Pattern complexity = 6 cost = 2 size = 0
if (N0.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_203(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::EXTRACT_SUBREG, MVT::v4f32, MVT::f32);
SDNode *Result = Emit_203(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::EXTRACT_SUBREG, MVT::v4f32, MVT::f32);
return Result;
}
}
@ -15676,7 +15681,7 @@ SDNode *Select_ISD_EXTRACT_VECTOR_ELT_f64(SDNode *N) {
SDValue N1 = N->getOperand(1);
if (N1.getNode()->getOpcode() == ISD::Constant &&
N0.getValueType() == MVT::v2f64) {
SDNode *Result = Emit_204(N, TargetInstrInfo::EXTRACT_SUBREG, MVT::f64);
SDNode *Result = Emit_204(N, TargetOpcode::EXTRACT_SUBREG, MVT::f64);
return Result;
}
@ -15698,7 +15703,7 @@ SDNode *Select_ISD_FABS_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VABSfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 4 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VABSfd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VABSfd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@ -15813,7 +15818,7 @@ SDNode *Select_ISD_FADD_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VADDfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32), (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$b, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 6 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
SDNode *Result = Emit_206(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VADDfd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
SDNode *Result = Emit_206(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VADDfd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@ -16085,7 +16090,7 @@ SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
SDNode *Result = Emit_137(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@ -16100,7 +16105,7 @@ SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
if (N101.getNode()->getOpcode() == ISD::Constant) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
SDNode *Result = Emit_138(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@ -16121,7 +16126,7 @@ SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
if (N011.getNode()->getOpcode() == ISD::Constant) {
SDValue N1 = N->getOperand(1);
if (N010.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_139(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
SDNode *Result = Emit_139(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@ -16138,7 +16143,7 @@ SDNode *Select_ISD_FADD_v4f32(SDNode *N) {
SDValue N01 = N0.getNode()->getOperand(1);
SDValue N1 = N->getOperand(1);
if (N000.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_140(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
SDNode *Result = Emit_140(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLAslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@ -16252,7 +16257,7 @@ SDNode *Select_ISD_FMUL_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VMULfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32), (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$b, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 6 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
SDNode *Result = Emit_206(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VMULfd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
SDNode *Result = Emit_206(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VMULfd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@ -16418,7 +16423,7 @@ SDNode *Select_ISD_FMUL_v4f32(SDNode *N) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_210(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
SDNode *Result = Emit_210(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@ -16433,7 +16438,7 @@ SDNode *Select_ISD_FMUL_v4f32(SDNode *N) {
if (N01.getNode()->getOpcode() == ISD::Constant) {
SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_211(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
SDNode *Result = Emit_211(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@ -16486,7 +16491,7 @@ SDNode *Select_ISD_FNEG_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VNEGf32d_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 4 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
SDNode *Result = Emit_32(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VNEGf32d_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
SDNode *Result = Emit_32(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VNEGf32d_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@ -16685,7 +16690,7 @@ SDNode *Select_ISD_FSUB_f32(SDNode *N) {
// Emits: (EXTRACT_SUBREG:f32 (VSUBfd_sfp:f64 (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$a, 1:i32), (INSERT_SUBREG:f64 (IMPLICIT_DEF:v2f32), SPR:f32:$b, 1:i32)), 1:i32)
// Pattern complexity = 3 cost = 6 size = 0
if ((Subtarget->hasNEON()) && (Subtarget->useNEONForSinglePrecisionFP())) {
SDNode *Result = Emit_206(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, ARM::VSUBfd_sfp, TargetInstrInfo::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
SDNode *Result = Emit_206(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, ARM::VSUBfd_sfp, TargetOpcode::EXTRACT_SUBREG, MVT::v2f32, MVT::f64, MVT::v2f32, MVT::f64, MVT::f64, MVT::f32);
return Result;
}
@ -16856,7 +16861,7 @@ SDNode *Select_ISD_FSUB_v4f32(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
SDNode *Result = Emit_137(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@ -16871,7 +16876,7 @@ SDNode *Select_ISD_FSUB_v4f32(SDNode *N) {
if (N101.getNode()->getOpcode() == ISD::Constant) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4f32) {
SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
SDNode *Result = Emit_138(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslfq, MVT::v2f32, MVT::v4f32);
return Result;
}
}
@ -16940,7 +16945,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v16i8(SDNode *N) {
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_213(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VSETLNi8, TargetInstrInfo::INSERT_SUBREG, MVT::v8i8, MVT::f64, MVT::v16i8);
SDNode *Result = Emit_213(N, TargetOpcode::EXTRACT_SUBREG, ARM::VSETLNi8, TargetOpcode::INSERT_SUBREG, MVT::v8i8, MVT::f64, MVT::v16i8);
return Result;
}
@ -16985,7 +16990,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v8i16(SDNode *N) {
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant &&
N1.getValueType() == MVT::i32) {
SDNode *Result = Emit_214(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VSETLNi16, TargetInstrInfo::INSERT_SUBREG, MVT::v4i16, MVT::f64, MVT::v8i16);
SDNode *Result = Emit_214(N, TargetOpcode::EXTRACT_SUBREG, ARM::VSETLNi16, TargetOpcode::INSERT_SUBREG, MVT::v4i16, MVT::f64, MVT::v8i16);
return Result;
}
@ -17028,7 +17033,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v4i32(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_215(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VSETLNi32, TargetInstrInfo::INSERT_SUBREG, MVT::v2i32, MVT::f64, MVT::v4i32);
SDNode *Result = Emit_215(N, TargetOpcode::EXTRACT_SUBREG, ARM::VSETLNi32, TargetOpcode::INSERT_SUBREG, MVT::v2i32, MVT::f64, MVT::v4i32);
return Result;
}
@ -17051,7 +17056,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f32(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_216(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
SDNode *Result = Emit_216(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
return Result;
}
@ -17074,7 +17079,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v4f32(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_217(N, TargetInstrInfo::COPY_TO_REGCLASS, TargetInstrInfo::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
SDNode *Result = Emit_217(N, TargetOpcode::COPY_TO_REGCLASS, TargetOpcode::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
return Result;
}
@ -17095,7 +17100,7 @@ SDNode *Select_ISD_INSERT_VECTOR_ELT_v2f64(SDNode *N) {
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
if (N2.getNode()->getOpcode() == ISD::Constant) {
SDNode *Result = Emit_218(N, TargetInstrInfo::INSERT_SUBREG, MVT::v2f64);
SDNode *Result = Emit_218(N, TargetOpcode::INSERT_SUBREG, MVT::v2f64);
return Result;
}
@ -19275,7 +19280,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16 &&
N20.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_228(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQDMULHslv8i16, MVT::v4i16, MVT::v8i16);
SDNode *Result = Emit_228(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQDMULHslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@ -19294,7 +19299,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
N1.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16 &&
N20.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_228(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQRDMULHslv8i16, MVT::v4i16, MVT::v8i16);
SDNode *Result = Emit_228(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQRDMULHslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@ -19313,7 +19318,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
if (N1.getValueType() == MVT::v8i16 &&
N10.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_231(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQDMULHslv8i16, MVT::v4i16, MVT::v8i16);
SDNode *Result = Emit_231(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQDMULHslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@ -19333,7 +19338,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v8i16(SDNode *N) {
if (N1.getValueType() == MVT::v8i16 &&
N10.getValueType() == MVT::v8i16 &&
N2.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_231(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQRDMULHslv8i16, MVT::v4i16, MVT::v8i16);
SDNode *Result = Emit_231(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQRDMULHslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@ -21518,7 +21523,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32 &&
N20.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_234(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQDMULHslv4i32, MVT::v2i32, MVT::v4i32);
SDNode *Result = Emit_234(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQDMULHslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@ -21537,7 +21542,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
N1.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32 &&
N20.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_234(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQRDMULHslv4i32, MVT::v2i32, MVT::v4i32);
SDNode *Result = Emit_234(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQRDMULHslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@ -21556,7 +21561,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
if (N1.getValueType() == MVT::v4i32 &&
N10.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_236(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQDMULHslv4i32, MVT::v2i32, MVT::v4i32);
SDNode *Result = Emit_236(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQDMULHslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@ -21576,7 +21581,7 @@ SDNode *Select_ISD_INTRINSIC_WO_CHAIN_v4i32(SDNode *N) {
if (N1.getValueType() == MVT::v4i32 &&
N10.getValueType() == MVT::v4i32 &&
N2.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_236(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VQRDMULHslv4i32, MVT::v2i32, MVT::v4i32);
SDNode *Result = Emit_236(N, TargetOpcode::EXTRACT_SUBREG, ARM::VQRDMULHslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@ -26551,7 +26556,7 @@ SDNode *Select_ISD_MUL_v8i16(SDNode *N) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_259(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
SDNode *Result = Emit_259(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@ -26566,7 +26571,7 @@ SDNode *Select_ISD_MUL_v8i16(SDNode *N) {
if (N01.getNode()->getOpcode() == ISD::Constant) {
SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_260(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
SDNode *Result = Emit_260(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@ -26681,7 +26686,7 @@ SDNode *Select_ISD_MUL_v4i32(SDNode *N) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N11.getNode()->getOpcode() == ISD::Constant &&
N10.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_210(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
SDNode *Result = Emit_210(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@ -26696,7 +26701,7 @@ SDNode *Select_ISD_MUL_v4i32(SDNode *N) {
if (N01.getNode()->getOpcode() == ISD::Constant) {
SDValue N1 = N->getOperand(1);
if (N00.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_211(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
SDNode *Result = Emit_211(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMULslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@ -33893,7 +33898,7 @@ DISABLE_INLINE SDNode *Emit_288(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::Si
SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i8(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_288(N, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi8, MVT::v8i8, MVT::v8i8);
SDNode *Result = Emit_288(N, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi8, MVT::v8i8, MVT::v8i8);
return Result;
}
@ -33916,7 +33921,7 @@ DISABLE_INLINE SDNode *Emit_289(SDNode *N, unsigned Opc0, unsigned Opc1, unsigne
SDNode *Select_ISD_SCALAR_TO_VECTOR_v16i8(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_289(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi8, TargetInstrInfo::INSERT_SUBREG, MVT::v16i8, MVT::v8i8, MVT::f64, MVT::v16i8);
SDNode *Result = Emit_289(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi8, TargetOpcode::INSERT_SUBREG, MVT::v16i8, MVT::v8i8, MVT::f64, MVT::v16i8);
return Result;
}
@ -33927,7 +33932,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v16i8(SDNode *N) {
SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i16(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_288(N, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi16, MVT::v4i16, MVT::v4i16);
SDNode *Result = Emit_288(N, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi16, MVT::v4i16, MVT::v4i16);
return Result;
}
@ -33938,7 +33943,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i16(SDNode *N) {
SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i16(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_289(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi16, TargetInstrInfo::INSERT_SUBREG, MVT::v8i16, MVT::v4i16, MVT::f64, MVT::v8i16);
SDNode *Result = Emit_289(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi16, TargetOpcode::INSERT_SUBREG, MVT::v8i16, MVT::v4i16, MVT::f64, MVT::v8i16);
return Result;
}
@ -33949,7 +33954,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v8i16(SDNode *N) {
SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_288(N, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi32, MVT::v2i32, MVT::v2i32);
SDNode *Result = Emit_288(N, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi32, MVT::v2i32, MVT::v2i32);
return Result;
}
@ -33960,7 +33965,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2i32(SDNode *N) {
SDNode *Select_ISD_SCALAR_TO_VECTOR_v4i32(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::i32) {
SDNode *Result = Emit_289(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::IMPLICIT_DEF, ARM::VSETLNi32, TargetInstrInfo::INSERT_SUBREG, MVT::v4i32, MVT::v2i32, MVT::f64, MVT::v4i32);
SDNode *Result = Emit_289(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::IMPLICIT_DEF, ARM::VSETLNi32, TargetOpcode::INSERT_SUBREG, MVT::v4i32, MVT::v2i32, MVT::f64, MVT::v4i32);
return Result;
}
@ -33977,7 +33982,7 @@ DISABLE_INLINE SDNode *Emit_290(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::Si
SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f32(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_290(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
SDNode *Result = Emit_290(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, MVT::v2f32, MVT::v2f32);
return Result;
}
@ -33988,7 +33993,7 @@ SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f32(SDNode *N) {
SDNode *Select_ISD_SCALAR_TO_VECTOR_v4f32(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f32) {
SDNode *Result = Emit_290(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
SDNode *Result = Emit_290(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, MVT::v4f32, MVT::v4f32);
return Result;
}
@ -34005,7 +34010,7 @@ DISABLE_INLINE SDNode *Emit_291(SDNode *N, unsigned Opc0, unsigned Opc1, MVT::Si
SDNode *Select_ISD_SCALAR_TO_VECTOR_v2f64(SDNode *N) {
SDValue N0 = N->getOperand(0);
if (N0.getValueType() == MVT::f64) {
SDNode *Result = Emit_291(N, TargetInstrInfo::IMPLICIT_DEF, TargetInstrInfo::INSERT_SUBREG, MVT::v2f64, MVT::v2f64);
SDNode *Result = Emit_291(N, TargetOpcode::IMPLICIT_DEF, TargetOpcode::INSERT_SUBREG, MVT::v2f64, MVT::v2f64);
return Result;
}
@ -36294,7 +36299,7 @@ SDNode *Select_ISD_SUB_v8i16(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_133(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
SDNode *Result = Emit_133(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@ -36309,7 +36314,7 @@ SDNode *Select_ISD_SUB_v8i16(SDNode *N) {
if (N101.getNode()->getOpcode() == ISD::Constant) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v8i16) {
SDNode *Result = Emit_134(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
SDNode *Result = Emit_134(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslv8i16, MVT::v4i16, MVT::v8i16);
return Result;
}
}
@ -36507,7 +36512,7 @@ SDNode *Select_ISD_SUB_v4i32(SDNode *N) {
SDValue N111 = N11.getNode()->getOperand(1);
if (N111.getNode()->getOpcode() == ISD::Constant &&
N110.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_137(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
SDNode *Result = Emit_137(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}
@ -36522,7 +36527,7 @@ SDNode *Select_ISD_SUB_v4i32(SDNode *N) {
if (N101.getNode()->getOpcode() == ISD::Constant) {
SDValue N11 = N1.getNode()->getOperand(1);
if (N100.getValueType() == MVT::v4i32) {
SDNode *Result = Emit_138(N, TargetInstrInfo::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
SDNode *Result = Emit_138(N, TargetOpcode::EXTRACT_SUBREG, ARM::VMLSslv4i32, MVT::v2i32, MVT::v4i32);
return Result;
}
}

3315
libclamav/c++/ARMGenInstrInfo.inc
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File diff suppressed because it is too large Load Diff

3019
libclamav/c++/ARMGenInstrNames.inc
View File

File diff suppressed because it is too large Load Diff

8
libclamav/c++/ARMGenRegisterInfo.inc
Unescape View File

@ -2648,7 +2648,7 @@ ARM::NoRegister, ARM::NoRegister };
const unsigned D10_AliasSet[] = { ARM::S20, ARM::S21, ARM::Q5, 0 };
const unsigned D11_AliasSet[] = { ARM::S22, ARM::S23, ARM::Q5, 0 };
const unsigned D12_AliasSet[] = { ARM::S24, ARM::S25, ARM::Q6, 0 };
const unsigned D13_AliasSet[] = { ARM::S27, ARM::S26, ARM::Q6, 0 };
const unsigned D13_AliasSet[] = { ARM::S26, ARM::S27, ARM::Q6, 0 };
const unsigned D14_AliasSet[] = { ARM::S28, ARM::S29, ARM::Q7, 0 };
const unsigned D15_AliasSet[] = { ARM::S30, ARM::S31, ARM::Q7, 0 };
const unsigned D16_AliasSet[] = { ARM::Q8, 0 };
@ -2690,7 +2690,7 @@ ARM::NoRegister, ARM::NoRegister };
const unsigned Q3_AliasSet[] = { ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::D6, ARM::D7, 0 };
const unsigned Q4_AliasSet[] = { ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::D8, ARM::D9, 0 };
const unsigned Q5_AliasSet[] = { ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::D10, ARM::D11, 0 };
const unsigned Q6_AliasSet[] = { ARM::S27, ARM::S24, ARM::S25, ARM::S26, ARM::D12, ARM::D13, 0 };
const unsigned Q6_AliasSet[] = { ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::D12, ARM::D13, 0 };
const unsigned Q7_AliasSet[] = { ARM::S28, ARM::S29, ARM::S30, ARM::S31, ARM::D14, ARM::D15, 0 };
const unsigned Q8_AliasSet[] = { ARM::D16, ARM::D17, 0 };
const unsigned Q9_AliasSet[] = { ARM::D18, ARM::D19, 0 };
@ -2751,7 +2751,7 @@ ARM::NoRegister, ARM::NoRegister };
const unsigned D10_SubRegsSet[] = { ARM::S20, ARM::S21, 0 };
const unsigned D11_SubRegsSet[] = { ARM::S22, ARM::S23, 0 };
const unsigned D12_SubRegsSet[] = { ARM::S24, ARM::S25, 0 };
const unsigned D13_SubRegsSet[] = { ARM::S27, ARM::S26, 0 };
const unsigned D13_SubRegsSet[] = { ARM::S26, ARM::S27, 0 };
const unsigned D14_SubRegsSet[] = { ARM::S28, ARM::S29, 0 };
const unsigned D15_SubRegsSet[] = { ARM::S30, ARM::S31, 0 };
const unsigned D16_SubRegsSet[] = { 0 };
@ -2793,7 +2793,7 @@ ARM::NoRegister, ARM::NoRegister };
const unsigned Q3_SubRegsSet[] = { ARM::S12, ARM::S13, ARM::D7, ARM::S14, ARM::S15, ARM::D6, 0 };
const unsigned Q4_SubRegsSet[] = { ARM::S16, ARM::S17, ARM::D9, ARM::S18, ARM::S19, ARM::D8, 0 };
const unsigned Q5_SubRegsSet[] = { ARM::S20, ARM::S21, ARM::D11, ARM::S22, ARM::S23, ARM::D10, 0 };
const unsigned Q6_SubRegsSet[] = { ARM::D13, ARM::S27, ARM::S24, ARM::S25, ARM::S26, ARM::D12, 0 };
const unsigned Q6_SubRegsSet[] = { ARM::S24, ARM::S25, ARM::D13, ARM::S26, ARM::S27, ARM::D12, 0 };
const unsigned Q7_SubRegsSet[] = { ARM::S28, ARM::S29, ARM::D15, ARM::S30, ARM::S31, ARM::D14, 0 };
const unsigned Q8_SubRegsSet[] = { ARM::D16, ARM::D17, 0 };
const unsigned Q9_SubRegsSet[] = { ARM::D18, ARM::D19, 0 };

22
libclamav/c++/Makefile.am
Unescape View File

@ -143,7 +143,6 @@ libllvmsupport_la_SOURCES=\
llvm/lib/Support/regexec.c\
llvm/lib/Support/regfree.c\
llvm/lib/Support/regstrlcpy.c
if MAINTAINER_MODE
BUILT_SOURCES+=$(TBLGENFILES)
noinst_PROGRAMS = tblgen
@ -157,14 +156,19 @@ tblgen_LDFLAGS=-pthread -Wl,--version-script,@top_srcdir@/llvm/autoconf/ExportMa
tblgen_SOURCES=\
llvm/utils/TableGen/AsmMatcherEmitter.cpp\
llvm/utils/TableGen/AsmWriterEmitter.cpp\
llvm/utils/TableGen/AsmWriterInst.cpp\
llvm/utils/TableGen/CallingConvEmitter.cpp\
llvm/utils/TableGen/ClangDiagnosticsEmitter.cpp\
llvm/utils/TableGen/CodeEmitterGen.cpp\
llvm/utils/TableGen/CodeGenDAGPatterns.cpp\
llvm/utils/TableGen/CodeGenInstruction.cpp\
llvm/utils/TableGen/CodeGenTarget.cpp\
llvm/utils/TableGen/DisassemblerEmitter.cpp\
llvm/utils/TableGen/DAGISelEmitter.cpp\
llvm/utils/TableGen/DAGISelMatcher.cpp\
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp\
llvm/utils/TableGen/DAGISelMatcherGen.cpp\
llvm/utils/TableGen/DisassemblerEmitter.cpp\
llvm/utils/TableGen/EDEmitter.cpp\
llvm/utils/TableGen/FastISelEmitter.cpp\
llvm/utils/TableGen/InstrEnumEmitter.cpp\
llvm/utils/TableGen/InstrInfoEmitter.cpp\
@ -359,7 +363,6 @@ endif
if BUILD_X86
libllvmx86codegen_la_CPPFLAGS=$(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/X86
libllvmx86codegen_la_SOURCES=\
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
llvm/lib/MC/MCAsmInfoCOFF.cpp\
llvm/lib/MC/MCCodeEmitter.cpp\
@ -376,6 +379,8 @@ libllvmx86codegen_la_SOURCES=\
llvm/lib/Target/X86/X86InstrInfo.cpp\
llvm/lib/Target/X86/X86JITInfo.cpp\
llvm/lib/Target/X86/X86MCAsmInfo.cpp\
llvm/lib/Target/X86/X86MCCodeEmitter.cpp\
llvm/lib/Target/X86/X86MCTargetExpr.cpp\
llvm/lib/Target/X86/X86RegisterInfo.cpp\
llvm/lib/Target/X86/X86Subtarget.cpp\
llvm/lib/Target/X86/X86TargetMachine.cpp\
@ -515,6 +520,7 @@ libllvmjit_la_SOURCES=\
llvm/lib/VMCore/Core.cpp\
llvm/lib/VMCore/Dominators.cpp\
llvm/lib/VMCore/Function.cpp\
llvm/lib/VMCore/GVMaterializer.cpp\
llvm/lib/VMCore/Globals.cpp\
llvm/lib/VMCore/IRBuilder.cpp\
llvm/lib/VMCore/InlineAsm.cpp\
@ -525,7 +531,6 @@ libllvmjit_la_SOURCES=\
llvm/lib/VMCore/LeakDetector.cpp\
llvm/lib/VMCore/Metadata.cpp\
llvm/lib/VMCore/Module.cpp\
llvm/lib/VMCore/ModuleProvider.cpp\
llvm/lib/VMCore/Pass.cpp\
llvm/lib/VMCore/PassManager.cpp\
llvm/lib/VMCore/PrintModulePass.cpp\
@ -561,6 +566,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/CalcSpillWeights.cpp\
llvm/lib/CodeGen/CodePlacementOpt.cpp\
llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp\
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
llvm/lib/CodeGen/DwarfEHPrepare.cpp\
llvm/lib/CodeGen/ExactHazardRecognizer.cpp\
llvm/lib/CodeGen/GCMetadata.cpp\
@ -572,7 +578,6 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/LiveStackAnalysis.cpp\
llvm/lib/CodeGen/LiveVariables.cpp\
llvm/lib/CodeGen/LowerSubregs.cpp\
llvm/lib/CodeGen/MachOWriter.cpp\
llvm/lib/CodeGen/MachineDominators.cpp\
llvm/lib/CodeGen/MachineLICM.cpp\
llvm/lib/CodeGen/MachineLoopInfo.cpp\
@ -581,6 +586,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/CodeGen/MachineSink.cpp\
llvm/lib/CodeGen/MachineVerifier.cpp\
llvm/lib/CodeGen/OptimizeExts.cpp\
llvm/lib/CodeGen/OptimizePHIs.cpp\
llvm/lib/CodeGen/PHIElimination.cpp\
llvm/lib/CodeGen/Passes.cpp\
llvm/lib/CodeGen/PostRASchedulerList.cpp\
@ -633,6 +639,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/MC/MCAssembler.cpp\
llvm/lib/MC/MCInst.cpp\
llvm/lib/MC/MCMachOStreamer.cpp\
llvm/lib/MC/MCNullStreamer.cpp\
llvm/lib/MC/MCStreamer.cpp\
llvm/lib/Target/TargetFrameInfo.cpp\
llvm/lib/Target/TargetSubtarget.cpp\
@ -656,6 +663,7 @@ libllvmcodegen_la_SOURCES=\
llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp
# Used only by make check
libllvmbitreader_la_SOURCES=\
@ -796,7 +804,6 @@ libllvmasmprinter_la_SOURCES+= llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
endif
libllvmfullcodegen_la_SOURCES=\
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
llvm/lib/CodeGen/GCMetadataPrinter.cpp\
llvm/lib/CodeGen/IfConversion.cpp\
llvm/lib/CodeGen/IntrinsicLowering.cpp\
@ -811,8 +818,7 @@ libllvmfullcodegen_la_SOURCES=\
llvm/lib/Target/Target.cpp\
llvm/lib/Target/TargetAsmLexer.cpp\
llvm/lib/Target/TargetELFWriterInfo.cpp\
llvm/lib/Target/TargetIntrinsicInfo.cpp\
llvm/lib/Target/TargetMachOWriterInfo.cpp
llvm/lib/Target/TargetIntrinsicInfo.cpp
lli_LDADD+=libllvmfullcodegen.la libllvmcodegen.la libllvmjit.la libllvmsupport.la libllvmsystem.la
lli_SOURCES=\

287
libclamav/c++/Makefile.in
Unescape View File

@ -229,14 +229,14 @@ am_libllvmcodegen_la_OBJECTS = AliasSetTracker.lo ConstantFolding.lo \
AggressiveAntiDepBreaker.lo AsmPrinter.lo DIE.lo DwarfDebug.lo \
DwarfException.lo DwarfLabel.lo DwarfPrinter.lo DwarfWriter.lo \
BranchFolding.lo CalcSpillWeights.lo CodePlacementOpt.lo \
CriticalAntiDepBreaker.lo DwarfEHPrepare.lo \
ExactHazardRecognizer.lo GCMetadata.lo GCStrategy.lo \
LLVMTargetMachine.lo LatencyPriorityQueue.lo LiveInterval.lo \
LiveIntervalAnalysis.lo LiveStackAnalysis.lo LiveVariables.lo \
LowerSubregs.lo MachOWriter.lo MachineDominators.lo \
CriticalAntiDepBreaker.lo DeadMachineInstructionElim.lo \
DwarfEHPrepare.lo ExactHazardRecognizer.lo GCMetadata.lo \
GCStrategy.lo LLVMTargetMachine.lo LatencyPriorityQueue.lo \
LiveInterval.lo LiveIntervalAnalysis.lo LiveStackAnalysis.lo \
LiveVariables.lo LowerSubregs.lo MachineDominators.lo \
MachineLICM.lo MachineLoopInfo.lo MachinePassRegistry.lo \
MachineSSAUpdater.lo MachineSink.lo MachineVerifier.lo \
OptimizeExts.lo PHIElimination.lo Passes.lo \
OptimizeExts.lo OptimizePHIs.lo PHIElimination.lo Passes.lo \
PostRASchedulerList.lo PreAllocSplitting.lo \
ProcessImplicitDefs.lo PrologEpilogInserter.lo \
RegAllocLinearScan.lo RegisterCoalescer.lo \
@ -256,22 +256,21 @@ am_libllvmcodegen_la_OBJECTS = AliasSetTracker.lo ConstantFolding.lo \
TwoAddressInstructionPass.lo UnreachableBlockElim.lo \
VirtRegMap.lo VirtRegRewriter.lo MCAsmInfoDarwin.lo \
MCAsmStreamer.lo MCAssembler.lo MCInst.lo MCMachOStreamer.lo \
MCStreamer.lo TargetFrameInfo.lo TargetSubtarget.lo \
CodeGenPrepare.lo GEPSplitter.lo GVN.lo LoopStrengthReduce.lo \
AddrModeMatcher.lo BasicBlockUtils.lo BreakCriticalEdges.lo \
DemoteRegToStack.lo LCSSA.lo Local.lo LoopSimplify.lo \
LowerInvoke.lo LowerSwitch.lo Mem2Reg.lo \
MCNullStreamer.lo MCStreamer.lo TargetFrameInfo.lo \
TargetSubtarget.lo CodeGenPrepare.lo GEPSplitter.lo GVN.lo \
LoopStrengthReduce.lo AddrModeMatcher.lo BasicBlockUtils.lo \
BreakCriticalEdges.lo DemoteRegToStack.lo LCSSA.lo Local.lo \
LoopSimplify.lo LowerInvoke.lo LowerSwitch.lo Mem2Reg.lo \
PromoteMemoryToRegister.lo SSAUpdater.lo SimplifyCFG.lo \
UnifyFunctionExitNodes.lo
libllvmcodegen_la_OBJECTS = $(am_libllvmcodegen_la_OBJECTS)
libllvmfullcodegen_la_LIBADD =
am_libllvmfullcodegen_la_OBJECTS = DeadMachineInstructionElim.lo \
GCMetadataPrinter.lo IfConversion.lo IntrinsicLowering.lo \
MachineModuleInfoImpls.lo OcamlGC.lo RegAllocLocal.lo \
RegAllocPBQP.lo ShadowStackGC.lo Execution.lo \
ExternalFunctions.lo Interpreter.lo Target.lo \
am_libllvmfullcodegen_la_OBJECTS = GCMetadataPrinter.lo \
IfConversion.lo IntrinsicLowering.lo MachineModuleInfoImpls.lo \
OcamlGC.lo RegAllocLocal.lo RegAllocPBQP.lo ShadowStackGC.lo \
Execution.lo ExternalFunctions.lo Interpreter.lo Target.lo \
TargetAsmLexer.lo TargetELFWriterInfo.lo \
TargetIntrinsicInfo.lo TargetMachOWriterInfo.lo
TargetIntrinsicInfo.lo
libllvmfullcodegen_la_OBJECTS = $(am_libllvmfullcodegen_la_OBJECTS)
libllvminterpreter_la_LIBADD =
am_libllvminterpreter_la_OBJECTS = Execution.lo ExternalFunctions.lo \
@ -302,11 +301,11 @@ am_libllvmjit_la_OBJECTS = AliasAnalysis.lo BasicAliasAnalysis.lo \
TargetLoweringObjectFile.lo TargetMachine.lo \
TargetRegisterInfo.lo AsmWriter.lo Attributes.lo \
AutoUpgrade.lo BasicBlock.lo ConstantFold.lo Constants.lo \
Core.lo Dominators.lo Function.lo Globals.lo IRBuilder.lo \
InlineAsm.lo Instruction.lo Instructions.lo IntrinsicInst.lo \
LLVMContext.lo LeakDetector.lo Metadata.lo Module.lo \
ModuleProvider.lo Pass.lo PassManager.lo PrintModulePass.lo \
Type.lo TypeSymbolTable.lo Use.lo Value.lo ValueSymbolTable.lo \
Core.lo Dominators.lo Function.lo GVMaterializer.lo Globals.lo \
IRBuilder.lo InlineAsm.lo Instruction.lo Instructions.lo \
IntrinsicInst.lo LLVMContext.lo LeakDetector.lo Metadata.lo \
Module.lo Pass.lo PassManager.lo PrintModulePass.lo Type.lo \
TypeSymbolTable.lo Use.lo Value.lo ValueSymbolTable.lo \
ValueTypes.lo Verifier.lo
libllvmjit_la_OBJECTS = $(am_libllvmjit_la_OBJECTS)
libllvmpowerpccodegen_la_LIBADD =
@ -371,7 +370,6 @@ libllvmsystem_la_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CXX \
$(LDFLAGS) -o $@
libllvmx86codegen_la_LIBADD =
am__libllvmx86codegen_la_SOURCES_DIST = \
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp \
llvm/lib/CodeGen/MachineModuleInfoImpls.cpp \
llvm/lib/MC/MCAsmInfoCOFF.cpp llvm/lib/MC/MCCodeEmitter.cpp \
llvm/lib/Target/TargetELFWriterInfo.cpp \
@ -387,12 +385,13 @@ am__libllvmx86codegen_la_SOURCES_DIST = \
llvm/lib/Target/X86/X86InstrInfo.cpp \
llvm/lib/Target/X86/X86JITInfo.cpp \
llvm/lib/Target/X86/X86MCAsmInfo.cpp \
llvm/lib/Target/X86/X86MCCodeEmitter.cpp \
llvm/lib/Target/X86/X86MCTargetExpr.cpp \
llvm/lib/Target/X86/X86RegisterInfo.cpp \
llvm/lib/Target/X86/X86Subtarget.cpp \
llvm/lib/Target/X86/X86TargetMachine.cpp \
llvm/lib/Target/X86/X86TargetObjectFile.cpp
@BUILD_X86_TRUE@am_libllvmx86codegen_la_OBJECTS = libllvmx86codegen_la-DeadMachineInstructionElim.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-MachineModuleInfoImpls.lo \
@BUILD_X86_TRUE@am_libllvmx86codegen_la_OBJECTS = libllvmx86codegen_la-MachineModuleInfoImpls.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-MCAsmInfoCOFF.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-MCCodeEmitter.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-TargetELFWriterInfo.lo \
@ -408,6 +407,8 @@ am__libllvmx86codegen_la_SOURCES_DIST = \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86InstrInfo.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86JITInfo.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86MCAsmInfo.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86MCCodeEmitter.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86MCTargetExpr.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86RegisterInfo.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86Subtarget.lo \
@BUILD_X86_TRUE@ libllvmx86codegen_la-X86TargetMachine.lo \
@ -511,14 +512,19 @@ not_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) \
$(CXXFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@
am__tblgen_SOURCES_DIST = llvm/utils/TableGen/AsmMatcherEmitter.cpp \
llvm/utils/TableGen/AsmWriterEmitter.cpp \
llvm/utils/TableGen/AsmWriterInst.cpp \
llvm/utils/TableGen/CallingConvEmitter.cpp \
llvm/utils/TableGen/ClangDiagnosticsEmitter.cpp \
llvm/utils/TableGen/CodeEmitterGen.cpp \
llvm/utils/TableGen/CodeGenDAGPatterns.cpp \
llvm/utils/TableGen/CodeGenInstruction.cpp \
llvm/utils/TableGen/CodeGenTarget.cpp \
llvm/utils/TableGen/DisassemblerEmitter.cpp \
llvm/utils/TableGen/DAGISelEmitter.cpp \
llvm/utils/TableGen/DAGISelMatcher.cpp \
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp \
llvm/utils/TableGen/DAGISelMatcherGen.cpp \
llvm/utils/TableGen/DisassemblerEmitter.cpp \
llvm/utils/TableGen/EDEmitter.cpp \
llvm/utils/TableGen/FastISelEmitter.cpp \
llvm/utils/TableGen/InstrEnumEmitter.cpp \
llvm/utils/TableGen/InstrInfoEmitter.cpp \
@ -578,14 +584,19 @@ am__tblgen_SOURCES_DIST = llvm/utils/TableGen/AsmMatcherEmitter.cpp \
@MAINTAINER_MODE_TRUE@am_tblgen_OBJECTS = \
@MAINTAINER_MODE_TRUE@ tblgen-AsmMatcherEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-AsmWriterEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-AsmWriterInst.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-CallingConvEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-ClangDiagnosticsEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-CodeEmitterGen.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-CodeGenDAGPatterns.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-CodeGenInstruction.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-CodeGenTarget.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DisassemblerEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DAGISelEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcher.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcherEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DAGISelMatcherGen.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-DisassemblerEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-EDEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-FastISelEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-InstrEnumEmitter.$(OBJEXT) \
@MAINTAINER_MODE_TRUE@ tblgen-InstrInfoEmitter.$(OBJEXT) \
@ -1011,14 +1022,19 @@ libllvmsupport_la_SOURCES = \
@MAINTAINER_MODE_TRUE@tblgen_SOURCES = \
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/AsmMatcherEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/AsmWriterEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/AsmWriterInst.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CallingConvEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/ClangDiagnosticsEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CodeEmitterGen.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CodeGenDAGPatterns.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CodeGenInstruction.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/CodeGenTarget.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DisassemblerEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcher.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcherEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DAGISelMatcherGen.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/DisassemblerEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/EDEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/FastISelEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/InstrEnumEmitter.cpp\
@MAINTAINER_MODE_TRUE@ llvm/utils/TableGen/InstrInfoEmitter.cpp\
@ -1111,7 +1127,6 @@ libllvmsupport_la_SOURCES = \
@MAINTAINER_MODE_TRUE@TBLGEN_FLAGS_ARM = $(TBLGEN_FLAGS) -I$(top_srcdir)/llvm/lib/Target/ARM
@BUILD_X86_TRUE@libllvmx86codegen_la_CPPFLAGS = $(LLVM_INCLUDES) $(LLVM_DEFS) -I$(top_builddir) -I$(top_srcdir)/llvm/lib/Target/X86
@BUILD_X86_TRUE@libllvmx86codegen_la_SOURCES = \
@BUILD_X86_TRUE@ llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
@BUILD_X86_TRUE@ llvm/lib/CodeGen/MachineModuleInfoImpls.cpp\
@BUILD_X86_TRUE@ llvm/lib/MC/MCAsmInfoCOFF.cpp\
@BUILD_X86_TRUE@ llvm/lib/MC/MCCodeEmitter.cpp\
@ -1128,6 +1143,8 @@ libllvmsupport_la_SOURCES = \
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86InstrInfo.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86JITInfo.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86MCAsmInfo.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86MCCodeEmitter.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86MCTargetExpr.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86RegisterInfo.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86Subtarget.cpp\
@BUILD_X86_TRUE@ llvm/lib/Target/X86/X86TargetMachine.cpp\
@ -1261,6 +1278,7 @@ libllvmjit_la_SOURCES = \
llvm/lib/VMCore/Core.cpp\
llvm/lib/VMCore/Dominators.cpp\
llvm/lib/VMCore/Function.cpp\
llvm/lib/VMCore/GVMaterializer.cpp\
llvm/lib/VMCore/Globals.cpp\
llvm/lib/VMCore/IRBuilder.cpp\
llvm/lib/VMCore/InlineAsm.cpp\
@ -1271,7 +1289,6 @@ libllvmjit_la_SOURCES = \
llvm/lib/VMCore/LeakDetector.cpp\
llvm/lib/VMCore/Metadata.cpp\
llvm/lib/VMCore/Module.cpp\
llvm/lib/VMCore/ModuleProvider.cpp\
llvm/lib/VMCore/Pass.cpp\
llvm/lib/VMCore/PassManager.cpp\
llvm/lib/VMCore/PrintModulePass.cpp\
@ -1307,6 +1324,7 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/CalcSpillWeights.cpp\
llvm/lib/CodeGen/CodePlacementOpt.cpp\
llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp\
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
llvm/lib/CodeGen/DwarfEHPrepare.cpp\
llvm/lib/CodeGen/ExactHazardRecognizer.cpp\
llvm/lib/CodeGen/GCMetadata.cpp\
@ -1318,7 +1336,6 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/LiveStackAnalysis.cpp\
llvm/lib/CodeGen/LiveVariables.cpp\
llvm/lib/CodeGen/LowerSubregs.cpp\
llvm/lib/CodeGen/MachOWriter.cpp\
llvm/lib/CodeGen/MachineDominators.cpp\
llvm/lib/CodeGen/MachineLICM.cpp\
llvm/lib/CodeGen/MachineLoopInfo.cpp\
@ -1327,6 +1344,7 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/CodeGen/MachineSink.cpp\
llvm/lib/CodeGen/MachineVerifier.cpp\
llvm/lib/CodeGen/OptimizeExts.cpp\
llvm/lib/CodeGen/OptimizePHIs.cpp\
llvm/lib/CodeGen/PHIElimination.cpp\
llvm/lib/CodeGen/Passes.cpp\
llvm/lib/CodeGen/PostRASchedulerList.cpp\
@ -1379,6 +1397,7 @@ libllvmcodegen_la_SOURCES = \
llvm/lib/MC/MCAssembler.cpp\
llvm/lib/MC/MCInst.cpp\
llvm/lib/MC/MCMachOStreamer.cpp\
llvm/lib/MC/MCNullStreamer.cpp\
llvm/lib/MC/MCStreamer.cpp\
llvm/lib/Target/TargetFrameInfo.cpp\
llvm/lib/Target/TargetSubtarget.cpp\
@ -1519,7 +1538,6 @@ libllvmasmprinter_la_SOURCES = \
llvm/lib/CodeGen/MachOWriter.cpp $(am__append_14) \
$(am__append_15) $(am__append_16)
libllvmfullcodegen_la_SOURCES = \
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp\
llvm/lib/CodeGen/GCMetadataPrinter.cpp\
llvm/lib/CodeGen/IfConversion.cpp\
llvm/lib/CodeGen/IntrinsicLowering.cpp\
@ -1534,8 +1552,7 @@ libllvmfullcodegen_la_SOURCES = \
llvm/lib/Target/Target.cpp\
llvm/lib/Target/TargetAsmLexer.cpp\
llvm/lib/Target/TargetELFWriterInfo.cpp\
llvm/lib/Target/TargetIntrinsicInfo.cpp\
llvm/lib/Target/TargetMachOWriterInfo.cpp
llvm/lib/Target/TargetIntrinsicInfo.cpp
lli_SOURCES = \
llvm/tools/lli/lli.cpp
@ -1799,6 +1816,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/GCMetadataPrinter.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/GCStrategy.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/GEPSplitter.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/GVMaterializer.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/GVN.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/Globals.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/GraphWriter.Plo@am__quote@
@ -1857,12 +1875,12 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MCExpr.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MCInst.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MCMachOStreamer.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MCNullStreamer.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MCSection.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MCSectionELF.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MCSectionMachO.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MCStreamer.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MCSymbol.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MachOWriter.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MachineBasicBlock.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MachineDominators.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MachineFunction.Plo@am__quote@
@ -1888,12 +1906,12 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/MemoryObject.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/Metadata.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/Module.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ModuleProvider.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/Mutex.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/OProfileJITEventListener.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ObjectCodeEmitter.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/OcamlGC.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/OptimizeExts.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/OptimizePHIs.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/PHIElimination.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/PHITransAddr.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/Parser.Plo@am__quote@
@ -1969,7 +1987,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetIntrinsicInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetLowering.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetLoweringObjectFile.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetMachOWriterInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetMachine.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetRegisterInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/TargetRegistry.Plo@am__quote@
@ -2059,7 +2076,6 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmpowerpccodegen_la-PPCTargetMachine.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmpowerpccodegen_la-PowerPCTargetInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmpowerpccodegen_la-TargetMachOWriterInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-DeadMachineInstructionElim.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-MCAsmInfoCOFF.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-MCCodeEmitter.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-MachineModuleInfoImpls.Plo@am__quote@
@ -2075,6 +2091,8 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-X86InstrInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-X86JITInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-X86MCAsmInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-X86MCCodeEmitter.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-X86MCTargetExpr.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-X86RegisterInfo.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-X86Subtarget.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libllvmx86codegen_la-X86TargetInfo.Plo@am__quote@
@ -2131,6 +2149,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-Allocator.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-AsmMatcherEmitter.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-AsmWriterEmitter.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-AsmWriterInst.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-Atomic.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-CallingConvEmitter.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-ClangDiagnosticsEmitter.Po@am__quote@
@ -2141,12 +2160,16 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-CommandLine.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-ConstantRange.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-DAGISelEmitter.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-DAGISelMatcher.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-DAGISelMatcherEmitter.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-DAGISelMatcherGen.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-Debug.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-DeltaAlgorithm.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-Disassembler.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-DisassemblerEmitter.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-Dwarf.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-DynamicLibrary.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-EDEmitter.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-Errno.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-ErrorHandling.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tblgen-FastISelEmitter.Po@am__quote@
@ -3028,6 +3051,14 @@ CriticalAntiDepBreaker.lo: llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o CriticalAntiDepBreaker.lo `test -f 'llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
DeadMachineInstructionElim.lo: llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT DeadMachineInstructionElim.lo -MD -MP -MF $(DEPDIR)/DeadMachineInstructionElim.Tpo -c -o DeadMachineInstructionElim.lo `test -f 'llvm/lib/CodeGen/DeadMachineInstructionElim.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/DeadMachineInstructionElim.Tpo $(DEPDIR)/DeadMachineInstructionElim.Plo
@am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/DeadMachineInstructionElim.cpp' object='DeadMachineInstructionElim.lo' libtool=yes @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o DeadMachineInstructionElim.lo `test -f 'llvm/lib/CodeGen/DeadMachineInstructionElim.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
DwarfEHPrepare.lo: llvm/lib/CodeGen/DwarfEHPrepare.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT DwarfEHPrepare.lo -MD -MP -MF $(DEPDIR)/DwarfEHPrepare.Tpo -c -o DwarfEHPrepare.lo `test -f 'llvm/lib/CodeGen/DwarfEHPrepare.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/DwarfEHPrepare.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/DwarfEHPrepare.Tpo $(DEPDIR)/DwarfEHPrepare.Plo
@ -3116,14 +3147,6 @@ LowerSubregs.lo: llvm/lib/CodeGen/LowerSubregs.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o LowerSubregs.lo `test -f 'llvm/lib/CodeGen/LowerSubregs.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/LowerSubregs.cpp
MachOWriter.lo: llvm/lib/CodeGen/MachOWriter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachOWriter.lo -MD -MP -MF $(DEPDIR)/MachOWriter.Tpo -c -o MachOWriter.lo `test -f 'llvm/lib/CodeGen/MachOWriter.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachOWriter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachOWriter.Tpo $(DEPDIR)/MachOWriter.Plo
@am__fastdepCXX_FALSE@ $(AM_V_CXX) @AM_BACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/lib/CodeGen/MachOWriter.cpp' object='MachOWriter.lo' libtool=yes @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -c -o MachOWriter.lo `test -f 'llvm/lib/CodeGen/MachOWriter.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachOWriter.cpp
MachineDominators.lo: llvm/lib/CodeGen/MachineDominators.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT MachineDominators.lo -MD -MP -MF $(DEPDIR)/MachineDominators.Tpo -c -o MachineDominators.lo `test -f 'llvm/lib/CodeGen/MachineDominators.cpp' || echo '$(srcdir)/'`llvm/lib/CodeGen/MachineDominators.cpp
@am__fastdepCXX_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/MachineDominators.Tpo $(DEPDIR)/MachineDominators.Plo
@ -3188,6 +3211,14 @@ OptimizeExts.lo: llvm/lib/CodeGen/OptimizeExts.cpp
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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OptimizePHIs.lo: llvm/lib/CodeGen/OptimizePHIs.cpp
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PHIElimination.lo: llvm/lib/CodeGen/PHIElimination.cpp
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@ -3604,6 +3635,14 @@ MCMachOStreamer.lo: llvm/lib/MC/MCMachOStreamer.cpp
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MCNullStreamer.lo: llvm/lib/MC/MCNullStreamer.cpp
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MCStreamer.lo: llvm/lib/MC/MCStreamer.cpp
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@ -3772,14 +3811,6 @@ UnifyFunctionExitNodes.lo: llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp
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DeadMachineInstructionElim.lo: llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
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GCMetadataPrinter.lo: llvm/lib/CodeGen/GCMetadataPrinter.cpp
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@ -3900,14 +3931,6 @@ TargetIntrinsicInfo.lo: llvm/lib/Target/TargetIntrinsicInfo.cpp
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TargetMachOWriterInfo.lo: llvm/lib/Target/TargetMachOWriterInfo.cpp
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AliasAnalysis.lo: llvm/lib/Analysis/AliasAnalysis.cpp
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@ -4540,6 +4563,14 @@ Function.lo: llvm/lib/VMCore/Function.cpp
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GVMaterializer.lo: llvm/lib/VMCore/GVMaterializer.cpp
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Globals.lo: llvm/lib/VMCore/Globals.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT Globals.lo -MD -MP -MF $(DEPDIR)/Globals.Tpo -c -o Globals.lo `test -f 'llvm/lib/VMCore/Globals.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/Globals.cpp
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@ -4620,14 +4651,6 @@ Module.lo: llvm/lib/VMCore/Module.cpp
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ModuleProvider.lo: llvm/lib/VMCore/ModuleProvider.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(LIBTOOL) $(AM_V_lt) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT ModuleProvider.lo -MD -MP -MF $(DEPDIR)/ModuleProvider.Tpo -c -o ModuleProvider.lo `test -f 'llvm/lib/VMCore/ModuleProvider.cpp' || echo '$(srcdir)/'`llvm/lib/VMCore/ModuleProvider.cpp
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Pass.lo: llvm/lib/VMCore/Pass.cpp
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@ -5052,14 +5075,6 @@ TimeValue.lo: llvm/lib/System/TimeValue.cpp
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libllvmx86codegen_la-DeadMachineInstructionElim.lo: llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
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libllvmx86codegen_la-MachineModuleInfoImpls.lo: llvm/lib/CodeGen/MachineModuleInfoImpls.cpp
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@ -5188,6 +5203,22 @@ libllvmx86codegen_la-X86MCAsmInfo.lo: llvm/lib/Target/X86/X86MCAsmInfo.cpp
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libllvmx86codegen_la-X86MCCodeEmitter.lo: llvm/lib/Target/X86/X86MCCodeEmitter.cpp
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libllvmx86codegen_la-X86MCTargetExpr.lo: llvm/lib/Target/X86/X86MCTargetExpr.cpp
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libllvmx86codegen_la-X86RegisterInfo.lo: llvm/lib/Target/X86/X86RegisterInfo.cpp
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@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='llvm/utils/TableGen/EDEmitter.cpp' object='tblgen-EDEmitter.obj' libtool=no @AMDEPBACKSLASH@
@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-DAGISelEmitter.obj `if test -f 'llvm/utils/TableGen/DAGISelEmitter.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/DAGISelEmitter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/DAGISelEmitter.cpp'; fi`
@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -c -o tblgen-EDEmitter.obj `if test -f 'llvm/utils/TableGen/EDEmitter.cpp'; then $(CYGPATH_W) 'llvm/utils/TableGen/EDEmitter.cpp'; else $(CYGPATH_W) '$(srcdir)/llvm/utils/TableGen/EDEmitter.cpp'; fi`
tblgen-FastISelEmitter.o: llvm/utils/TableGen/FastISelEmitter.cpp
@am__fastdepCXX_TRUE@ $(AM_V_CXX)$(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(tblgen_CXXFLAGS) $(CXXFLAGS) -MT tblgen-FastISelEmitter.o -MD -MP -MF $(DEPDIR)/tblgen-FastISelEmitter.Tpo -c -o tblgen-FastISelEmitter.o `test -f 'llvm/utils/TableGen/FastISelEmitter.cpp' || echo '$(srcdir)/'`llvm/utils/TableGen/FastISelEmitter.cpp

1181
libclamav/c++/PPCGenAsmWriter.inc
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534
libclamav/c++/PPCGenDAGISel.inc
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2
libclamav/c++/PPCGenInstrInfo.inc
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@ -132,7 +132,7 @@ static const TargetInstrDesc PPCInsts[] = {
{ 8, 1, 1, 52, "IMPLICIT_DEF", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo8 }, // Inst #8 = IMPLICIT_DEF
{ 9, 4, 1, 52, "SUBREG_TO_REG", 0, 0, NULL, NULL, NULL, OperandInfo24 }, // Inst #9 = SUBREG_TO_REG
{ 10, 3, 1, 52, "COPY_TO_REGCLASS", 0|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, OperandInfo20 }, // Inst #10 = COPY_TO_REGCLASS
{ 11, 0, 0, 52, "DEBUG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DEBUG_VALUE
{ 11, 0, 0, 52, "DBG_VALUE", 0|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::CheapAsAMove), 0, NULL, NULL, NULL, 0 }, // Inst #11 = DBG_VALUE
{ 12, 3, 1, 14, "ADD4", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo2 }, // Inst #12 = ADD4
{ 13, 3, 1, 14, "ADD8", 0, 0|(1<<3), NULL, NULL, NULL, OperandInfo3 }, // Inst #13 = ADD8
{ 14, 3, 1, 14, "ADDC", 0, 0|(1<<2)|(1<<3), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #14 = ADDC

2
libclamav/c++/PPCGenInstrNames.inc
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@ -21,7 +21,7 @@ namespace PPC {
IMPLICIT_DEF = 8,
SUBREG_TO_REG = 9,
COPY_TO_REGCLASS = 10,
DEBUG_VALUE = 11,
DBG_VALUE = 11,
ADD4 = 12,
ADD8 = 13,
ADDC = 14,

4293
libclamav/c++/X86GenAsmMatcher.inc
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5669
libclamav/c++/X86GenAsmWriter.inc
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5522
libclamav/c++/X86GenAsmWriter1.inc
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41920
libclamav/c++/X86GenDAGISel.inc
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4192
libclamav/c++/X86GenInstrInfo.inc
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4045
libclamav/c++/X86GenInstrNames.inc
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20
libclamav/c++/X86GenRegisterInfo.inc
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@ -121,7 +121,7 @@ namespace { // Register classes...
// GR8_NOREX Register Class...
static const unsigned GR8_NOREX[] = {
X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL,
X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
};
// RFP32 Register Class...
@ -1271,8 +1271,9 @@ GR8_ABCD_HClass::GR8_ABCD_HClass() : TargetRegisterClass(GR8_ABCD_HRegClassID,
GR8_ABCD_LClass::GR8_ABCD_LClass() : TargetRegisterClass(GR8_ABCD_LRegClassID, "GR8_ABCD_L", GR8_ABCD_LVTs, GR8_ABCD_LSubclasses, GR8_ABCD_LSuperclasses, GR8_ABCD_LSubRegClasses, GR8_ABCD_LSuperRegClasses, 1, 1, 1, GR8_ABCD_L, GR8_ABCD_L + 4) {}
// In 64-bit mode, it's not safe to blindly allocate H registers.
static const unsigned X86_GR8_NOREX_AO_64[] = {
X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, X86::BL, X86::BPL
X86::AL, X86::CL, X86::DL, X86::BL
};
GR8_NOREXClass::iterator
@ -1288,21 +1289,14 @@ GR8_ABCD_LClass::GR8_ABCD_LClass() : TargetRegisterClass(GR8_ABCD_LRegClassID,
GR8_NOREXClass::iterator
GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
// Does the function dedicate RBP / EBP to being a frame ptr?
if (!Subtarget.is64Bit())
// In 32-mode, none of the 8-bit registers aliases EBP or ESP.
return begin() + 8;
else if (RI->hasFP(MF))
// If so, don't allocate SPL or BPL.
return array_endof(X86_GR8_NOREX_AO_64) - 1;
else
// If not, just don't allocate SPL.
if (Subtarget.is64Bit())
return array_endof(X86_GR8_NOREX_AO_64);
else
return end();
}
GR8_NOREXClass::GR8_NOREXClass() : TargetRegisterClass(GR8_NOREXRegClassID, "GR8_NOREX", GR8_NOREXVTs, GR8_NOREXSubclasses, GR8_NOREXSuperclasses, GR8_NOREXSubRegClasses, GR8_NOREXSuperRegClasses, 1, 1, 1, GR8_NOREX, GR8_NOREX + 12) {}
GR8_NOREXClass::GR8_NOREXClass() : TargetRegisterClass(GR8_NOREXRegClassID, "GR8_NOREX", GR8_NOREXVTs, GR8_NOREXSubclasses, GR8_NOREXSuperclasses, GR8_NOREXSubRegClasses, GR8_NOREXSuperRegClasses, 1, 1, 1, GR8_NOREX, GR8_NOREX + 8) {}
RFP32Class::RFP32Class() : TargetRegisterClass(RFP32RegClassID, "RFP32", RFP32VTs, RFP32Subclasses, RFP32Superclasses, RFP32SubRegClasses, RFP32SuperRegClasses, 4, 4, 1, RFP32, RFP32 + 7) {}

9
libclamav/c++/llvm/include/llvm/Intrinsics.gen
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@ -166,6 +166,7 @@
eh_return_i32, // llvm.eh.return.i32
eh_return_i64, // llvm.eh.return.i64
eh_selector, // llvm.eh.selector
eh_sjlj_callsite, // llvm.eh.sjlj.callsite
eh_sjlj_longjmp, // llvm.eh.sjlj.longjmp
eh_sjlj_lsda, // llvm.eh.sjlj.lsda
eh_sjlj_setjmp, // llvm.eh.sjlj.setjmp
@ -926,6 +927,7 @@
"llvm.eh.return.i32",
"llvm.eh.return.i64",
"llvm.eh.selector",
"llvm.eh.sjlj.callsite",
"llvm.eh.sjlj.longjmp",
"llvm.eh.sjlj.lsda",
"llvm.eh.sjlj.setjmp",
@ -1691,6 +1693,7 @@
false,
false,
false,
false,
true,
true,
false,
@ -2457,6 +2460,7 @@
if (Len == 18 && !memcmp(Name, "llvm.eh.return.i32", 18)) return Intrinsic::eh_return_i32;
if (Len == 18 && !memcmp(Name, "llvm.eh.return.i64", 18)) return Intrinsic::eh_return_i64;
if (Len == 16 && !memcmp(Name, "llvm.eh.selector", 16)) return Intrinsic::eh_selector;
if (Len == 21 && !memcmp(Name, "llvm.eh.sjlj.callsite", 21)) return Intrinsic::eh_sjlj_callsite;
if (Len == 20 && !memcmp(Name, "llvm.eh.sjlj.longjmp", 20)) return Intrinsic::eh_sjlj_longjmp;
if (Len == 17 && !memcmp(Name, "llvm.eh.sjlj.lsda", 17)) return Intrinsic::eh_sjlj_lsda;
if (Len == 19 && !memcmp(Name, "llvm.eh.sjlj.setjmp", 19)) return Intrinsic::eh_sjlj_setjmp;
@ -4174,6 +4178,7 @@
case Intrinsic::memory_barrier: // llvm.memory.barrier
VerifyIntrinsicPrototype(ID, IF, 1, 5, MVT::isVoid, MVT::i1, MVT::i1, MVT::i1, MVT::i1, MVT::i1);
break;
case Intrinsic::eh_sjlj_callsite: // llvm.eh.sjlj.callsite
case Intrinsic::pcmarker: // llvm.pcmarker
case Intrinsic::ppc_altivec_dss: // llvm.ppc.altivec.dss
VerifyIntrinsicPrototype(ID, IF, 1, 1, MVT::isVoid, MVT::i32);
@ -5795,6 +5800,7 @@
ArgTys.push_back(IntegerType::get(Context, 1));
ArgTys.push_back(IntegerType::get(Context, 1));
break;
case Intrinsic::eh_sjlj_callsite: // llvm.eh.sjlj.callsite
case Intrinsic::pcmarker: // llvm.pcmarker
case Intrinsic::ppc_altivec_dss: // llvm.ppc.altivec.dss
ResultTy = Type::getVoidTy(Context);
@ -6147,6 +6153,7 @@ AttrListPtr Intrinsic::getAttributes(ID id) { // No intrinsic can throw excepti
case Intrinsic::cttz:
case Intrinsic::dbg_declare:
case Intrinsic::dbg_value:
case Intrinsic::eh_sjlj_callsite:
case Intrinsic::eh_sjlj_longjmp:
case Intrinsic::eh_sjlj_lsda:
case Intrinsic::eh_sjlj_setjmp:
@ -7077,6 +7084,8 @@ case Intrinsic::dbg_value:
return DoesNotAccessMemory;
case Intrinsic::eh_exception:
return OnlyReadsMemory;
case Intrinsic::eh_sjlj_callsite:
return DoesNotAccessMemory;
case Intrinsic::eh_sjlj_longjmp:
return DoesNotAccessMemory;
case Intrinsic::eh_sjlj_lsda:

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