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1531 lines
45 KiB
1531 lines
45 KiB
//===- TableGen'erated file -------------------------------------*- C++ -*-===//
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//
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// Assembly Writer Source Fragment
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//
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// Automatically generated file, do not edit!
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//
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//===----------------------------------------------------------------------===//
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/// printInstruction - This method is automatically generated by tablegen
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/// from the instruction set description.
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void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
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static const unsigned OpInfo[] = {
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0U, // PHI
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0U, // INLINEASM
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0U, // DBG_LABEL
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0U, // EH_LABEL
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0U, // GC_LABEL
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0U, // KILL
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0U, // EXTRACT_SUBREG
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0U, // INSERT_SUBREG
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0U, // IMPLICIT_DEF
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0U, // SUBREG_TO_REG
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0U, // COPY_TO_REGCLASS
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1U, // DBG_VALUE
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268435467U, // ADD4
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268435467U, // ADD8
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268435472U, // ADDC
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268435472U, // ADDC8
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268435478U, // ADDE
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268435478U, // ADDE8
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268439580U, // ADDI
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268439580U, // ADDI8
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268439586U, // ADDIC
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268439586U, // ADDIC8
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268439593U, // ADDICo
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268443697U, // ADDIS
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268443697U, // ADDIS8
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268468280U, // ADDME
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268468280U, // ADDME8
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268468287U, // ADDZE
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268468287U, // ADDZE8
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541065286U, // ADJCALLSTACKDOWN
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545259590U, // ADJCALLSTACKUP
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268435527U, // AND
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268435527U, // AND8
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268435532U, // ANDC
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268435532U, // ANDC8
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268447826U, // ANDISo
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268447826U, // ANDISo8
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268447834U, // ANDIo
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268447834U, // ANDIo8
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549453894U, // ATOMIC_CMP_SWAP_I16
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553648198U, // ATOMIC_CMP_SWAP_I32
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557842502U, // ATOMIC_CMP_SWAP_I64
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562036806U, // ATOMIC_CMP_SWAP_I8
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566231110U, // ATOMIC_LOAD_ADD_I16
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570425414U, // ATOMIC_LOAD_ADD_I32
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574619718U, // ATOMIC_LOAD_ADD_I64
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578814022U, // ATOMIC_LOAD_ADD_I8
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583008326U, // ATOMIC_LOAD_AND_I16
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587202630U, // ATOMIC_LOAD_AND_I32
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591396934U, // ATOMIC_LOAD_AND_I64
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595591238U, // ATOMIC_LOAD_AND_I8
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599785542U, // ATOMIC_LOAD_NAND_I16
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603979846U, // ATOMIC_LOAD_NAND_I32
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608174150U, // ATOMIC_LOAD_NAND_I64
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612368454U, // ATOMIC_LOAD_NAND_I8
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616562758U, // ATOMIC_LOAD_OR_I16
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620757062U, // ATOMIC_LOAD_OR_I32
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624951366U, // ATOMIC_LOAD_OR_I64
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629145670U, // ATOMIC_LOAD_OR_I8
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633339974U, // ATOMIC_LOAD_SUB_I16
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637534278U, // ATOMIC_LOAD_SUB_I32
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641728582U, // ATOMIC_LOAD_SUB_I64
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645922886U, // ATOMIC_LOAD_SUB_I8
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650117190U, // ATOMIC_LOAD_XOR_I16
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654311494U, // ATOMIC_LOAD_XOR_I32
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658505798U, // ATOMIC_LOAD_XOR_I64
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662700102U, // ATOMIC_LOAD_XOR_I8
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666894406U, // ATOMIC_SWAP_I16
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671088710U, // ATOMIC_SWAP_I32
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675283014U, // ATOMIC_SWAP_I64
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679477318U, // ATOMIC_SWAP_I8
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805306465U, // B
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1220804708U, // BCC
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102U, // BCTR
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107U, // BCTRL8_Darwin
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107U, // BCTRL8_ELF
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107U, // BCTRL_Darwin
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107U, // BCTRL_SVR4
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1493172337U, // BL8_Darwin
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1493172337U, // BL8_ELF
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1761607797U, // BLA8_Darwin
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1761607797U, // BLA8_ELF
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1761607797U, // BLA_Darwin
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1761607797U, // BLA_SVR4
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1228931172U, // BLR
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1493172337U, // BL_Darwin
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1493172337U, // BL_SVR4
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268435578U, // CMPD
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268439680U, // CMPDI
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268435591U, // CMPLD
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268447886U, // CMPLDI
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268435606U, // CMPLW
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268447901U, // CMPLWI
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268435621U, // CMPW
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268439723U, // CMPWI
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268468402U, // CNTLZD
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268468410U, // CNTLZW
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268435650U, // CREQV
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268435657U, // CROR
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268959938U, // CRSET
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1879048399U, // DCBA
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1879048405U, // DCBF
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1879048411U, // DCBI
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1879048417U, // DCBST
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1879048424U, // DCBT
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1879048430U, // DCBTST
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1879048438U, // DCBZ
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1879048444U, // DCBZL
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268435715U, // DIVD
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268435721U, // DIVDU
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268435728U, // DIVW
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268435734U, // DIVWU
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2147483933U, // DSS
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290U, // DSSALL
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2415919401U, // DST
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2415919401U, // DST64
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2415919406U, // DSTST
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2415919406U, // DSTST64
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2415919413U, // DSTSTT
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2415919413U, // DSTSTT64
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2415919421U, // DSTT
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2415919421U, // DSTT64
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696254534U, // DYNALLOC
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700448838U, // DYNALLOC8
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268435779U, // EQV
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268435779U, // EQV8
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268468552U, // EXTSB
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268468552U, // EXTSB8
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268468559U, // EXTSH
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268468559U, // EXTSH8
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268468566U, // EXTSW
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268468566U, // EXTSW_32
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268468566U, // EXTSW_32_64
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268468573U, // FABSD
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268468573U, // FABSS
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268435811U, // FADD
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268435817U, // FADDS
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268435811U, // FADDrtz
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268468592U, // FCFID
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268435831U, // FCMPUD
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268435831U, // FCMPUS
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268468606U, // FCTIDZ
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268468614U, // FCTIWZ
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268435854U, // FDIV
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268435860U, // FDIVS
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268435867U, // FMADD
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268435874U, // FMADDS
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268468650U, // FMR
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268468650U, // FMRSD
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268435887U, // FMSUB
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268435894U, // FMSUBS
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268435902U, // FMUL
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268435908U, // FMULS
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268468683U, // FNABSD
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268468683U, // FNABSS
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268468690U, // FNEGD
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268468690U, // FNEGS
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268435928U, // FNMADD
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268435936U, // FNMADDS
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268435945U, // FNMSUB
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268435953U, // FNMSUBS
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268468730U, // FRSP
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268435968U, // FSELD
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268435968U, // FSELS
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268468742U, // FSQRT
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268468749U, // FSQRTS
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268435989U, // FSUB
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268435995U, // FSUBS
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269287970U, // LA
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269484582U, // LBZ
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269484582U, // LBZ8
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269746731U, // LBZU
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269746731U, // LBZU8
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270008881U, // LBZX
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270008881U, // LBZX8
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270271031U, // LD
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270008891U, // LDARX
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270533186U, // LDU
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270008903U, // LDX
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436208204U, // LDinto_toc
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270795319U, // LDtoc
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597U, // LDtoc_restore
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269484641U, // LFD
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269746785U, // LFDU
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270008934U, // LFDX
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269484652U, // LFS
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269746796U, // LFSU
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270008945U, // LFSX
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269484663U, // LHA
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269484663U, // LHA8
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269746812U, // LHAU
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269320828U, // LHAU8
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270008962U, // LHAX
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270008962U, // LHAX8
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270008968U, // LHBRX
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269484687U, // LHZ
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269484687U, // LHZ8
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269746836U, // LHZU
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269746836U, // LHZU8
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270008986U, // LHZX
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270008986U, // LHZX8
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271057568U, // LI
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271057568U, // LI8
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271319716U, // LIS
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271319716U, // LIS8
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270009001U, // LVEBX
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270009008U, // LVEHX
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270009015U, // LVEWX
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270009022U, // LVSL
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270009028U, // LVSR
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270009034U, // LVX
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270009039U, // LVXL
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270271189U, // LWA
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270009050U, // LWARX
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270009057U, // LWAX
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270009063U, // LWBRX
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269484782U, // LWZ
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269484782U, // LWZ8
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269746931U, // LWZU
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269746931U, // LWZU8
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270009081U, // LWZX
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270009081U, // LWZX8
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268468991U, // MCRF
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419431173U, // MFCR
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419431179U, // MFCTR
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419431179U, // MFCTR8
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419431186U, // MFFS
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419431192U, // MFLR
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419431192U, // MFLR8
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271581957U, // MFOCRF
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440402718U, // MFVRSAVE
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419431205U, // MFVSCR
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2684355373U, // MTCRF
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419431220U, // MTCTR
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419431220U, // MTCTR8
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2952790843U, // MTFSB0
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2952790851U, // MTFSB1
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3397387083U, // MTFSF
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419431250U, // MTLR
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419431250U, // MTLR8
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419431256U, // MTVRSAVE
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419431268U, // MTVSCR
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268436332U, // MULHD
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268436339U, // MULHDU
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268436347U, // MULHW
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268436354U, // MULHWU
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268436362U, // MULLD
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268440465U, // MULLI
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268436376U, // MULLW
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3489661041U, // MovePCtoLR
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3489661041U, // MovePCtoLR8
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268436383U, // NAND
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268436383U, // NAND8
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268469157U, // NEG
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268469157U, // NEG8
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938U, // NOP
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268436398U, // NOR
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268436398U, // NOR8
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268436403U, // OR
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268436403U, // OR4To8
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268436403U, // OR8
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|
268436403U, // OR8To4
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268436407U, // ORC
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268436407U, // ORC8
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268448700U, // ORI
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268448700U, // ORI8
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268448705U, // ORIS
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268448705U, // ORIS8
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268436423U, // RLDCL
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268452814U, // RLDICL
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268452822U, // RLDICR
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271975390U, // RLDIMI
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272008166U, // RLWIMI
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268456942U, // RLWINM
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268456950U, // RLWINMo
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268436479U, // RLWNM
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717226054U, // SELECT_CC_F4
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717226054U, // SELECT_CC_F8
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717226054U, // SELECT_CC_I4
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717226054U, // SELECT_CC_I8
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717226054U, // SELECT_CC_VRRC
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268436486U, // SLD
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268436491U, // SLW
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721420358U, // SPILL_CR
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268436496U, // SRAD
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268452886U, // SRADI
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268436509U, // SRAW
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268456995U, // SRAWI
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268436522U, // SRD
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268436527U, // SRW
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269485108U, // STB
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269485108U, // STB8
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3409970233U, // STBU
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3409970233U, // STBU8
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270009407U, // STBX
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270009407U, // STBX8
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270271557U, // STD
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270009418U, // STDCX
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3414164562U, // STDU
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270009432U, // STDUX
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270009439U, // STDX
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270009439U, // STDX_32
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270271557U, // STD_32
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269485157U, // STFD
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3409970283U, // STFDU
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270009458U, // STFDX
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270009465U, // STFIWX
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269485185U, // STFS
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3409970311U, // STFSU
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270009486U, // STFSX
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269485205U, // STH
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269485205U, // STH8
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270009498U, // STHBRX
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3409970338U, // STHU
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3409970338U, // STHU8
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270009512U, // STHX
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270009512U, // STHX8
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270009518U, // STVEBX
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270009526U, // STVEHX
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270009534U, // STVEWX
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|
270009542U, // STVX
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|
270009548U, // STVXL
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|
269485267U, // STW
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|
269485267U, // STW8
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|
270009560U, // STWBRX
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|
270009568U, // STWCX
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|
3409970408U, // STWU
|
|
268436718U, // STWUX
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|
270009589U, // STWX
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|
270009589U, // STWX8
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|
268436731U, // SUBF
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|
268436731U, // SUBF8
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|
268436737U, // SUBFC
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|
268436737U, // SUBFC8
|
|
268436744U, // SUBFE
|
|
268436744U, // SUBFE8
|
|
268440847U, // SUBFIC
|
|
268440847U, // SUBFIC8
|
|
268469527U, // SUBFME
|
|
268469527U, // SUBFME8
|
|
268469535U, // SUBFZE
|
|
268469535U, // SUBFZE8
|
|
1319U, // SYNC
|
|
1493172321U, // TAILB
|
|
1493172321U, // TAILB8
|
|
1761609004U, // TAILBA
|
|
1761609004U, // TAILBA8
|
|
102U, // TAILBCTR
|
|
102U, // TAILBCTR8
|
|
1757447472U, // TCRETURNai
|
|
1757447485U, // TCRETURNai8
|
|
1489012043U, // TCRETURNdi
|
|
1489012056U, // TCRETURNdi8
|
|
415270246U, // TCRETURNri
|
|
415270259U, // TCRETURNri8
|
|
1409U, // TRAP
|
|
268469638U, // UPDATE_VRSAVE
|
|
268436885U, // VADDCUW
|
|
268436894U, // VADDFP
|
|
268436902U, // VADDSBS
|
|
268436911U, // VADDSHS
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|
268436920U, // VADDSWS
|
|
268436929U, // VADDUBM
|
|
268436938U, // VADDUBS
|
|
268436947U, // VADDUHM
|
|
268436956U, // VADDUHS
|
|
268436965U, // VADDUWM
|
|
268436974U, // VADDUWS
|
|
268436983U, // VAND
|
|
268436989U, // VANDC
|
|
268436996U, // VAVGSB
|
|
268437004U, // VAVGSH
|
|
268437012U, // VAVGSW
|
|
268437020U, // VAVGUB
|
|
268437028U, // VAVGUH
|
|
268437036U, // VAVGUW
|
|
272041524U, // VCFSX
|
|
272041531U, // VCFUX
|
|
268437058U, // VCMPBFP
|
|
268437067U, // VCMPBFPo
|
|
268437077U, // VCMPEQFP
|
|
268437087U, // VCMPEQFPo
|
|
268437098U, // VCMPEQUB
|
|
268437108U, // VCMPEQUBo
|
|
268437119U, // VCMPEQUH
|
|
268437129U, // VCMPEQUHo
|
|
268437140U, // VCMPEQUW
|
|
268437150U, // VCMPEQUWo
|
|
268437161U, // VCMPGEFP
|
|
268437171U, // VCMPGEFPo
|
|
268437182U, // VCMPGTFP
|
|
268437192U, // VCMPGTFPo
|
|
268437203U, // VCMPGTSB
|
|
268437213U, // VCMPGTSBo
|
|
268437224U, // VCMPGTSH
|
|
268437234U, // VCMPGTSHo
|
|
268437245U, // VCMPGTSW
|
|
268437255U, // VCMPGTSWo
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|
268437266U, // VCMPGTUB
|
|
268437276U, // VCMPGTUBo
|
|
268437287U, // VCMPGTUH
|
|
268437297U, // VCMPGTUHo
|
|
268437308U, // VCMPGTUW
|
|
268437318U, // VCMPGTUWo
|
|
272041809U, // VCTSXS
|
|
272041817U, // VCTUXS
|
|
268470113U, // VEXPTEFP
|
|
268470123U, // VLOGEFP
|
|
268437364U, // VMADDFP
|
|
268437373U, // VMAXFP
|
|
268437381U, // VMAXSB
|
|
268437389U, // VMAXSH
|
|
268437397U, // VMAXSW
|
|
268437405U, // VMAXUB
|
|
268437413U, // VMAXUH
|
|
268437421U, // VMAXUW
|
|
268437429U, // VMHADDSHS
|
|
268437440U, // VMHRADDSHS
|
|
268437452U, // VMINFP
|
|
268437460U, // VMINSB
|
|
268437468U, // VMINSH
|
|
268437476U, // VMINSW
|
|
268437484U, // VMINUB
|
|
268437492U, // VMINUH
|
|
268437500U, // VMINUW
|
|
268437508U, // VMLADDUHM
|
|
268437519U, // VMRGHB
|
|
268437527U, // VMRGHH
|
|
268437535U, // VMRGHW
|
|
268437543U, // VMRGLB
|
|
268437551U, // VMRGLH
|
|
268437559U, // VMRGLW
|
|
268437567U, // VMSUMMBM
|
|
268437577U, // VMSUMSHM
|
|
268437587U, // VMSUMSHS
|
|
268437597U, // VMSUMUBM
|
|
268437607U, // VMSUMUHM
|
|
268437617U, // VMSUMUHS
|
|
268437627U, // VMULESB
|
|
268437636U, // VMULESH
|
|
268437645U, // VMULEUB
|
|
268437654U, // VMULEUH
|
|
268437663U, // VMULOSB
|
|
268437672U, // VMULOSH
|
|
268437681U, // VMULOUB
|
|
268437690U, // VMULOUH
|
|
268437699U, // VNMSUBFP
|
|
268437709U, // VNOR
|
|
268437715U, // VOR
|
|
268437720U, // VPERM
|
|
268437727U, // VPKPX
|
|
268437734U, // VPKSHSS
|
|
268437743U, // VPKSHUS
|
|
268437752U, // VPKSWSS
|
|
268437761U, // VPKSWUS
|
|
268437770U, // VPKUHUM
|
|
268437779U, // VPKUHUS
|
|
268437788U, // VPKUWUM
|
|
268437797U, // VPKUWUS
|
|
268470574U, // VREFP
|
|
268470581U, // VRFIM
|
|
268470588U, // VRFIN
|
|
268470595U, // VRFIP
|
|
268470602U, // VRFIZ
|
|
268437841U, // VRLB
|
|
268437847U, // VRLH
|
|
268437853U, // VRLW
|
|
268470627U, // VRSQRTEFP
|
|
268437870U, // VSEL
|
|
268437876U, // VSL
|
|
268437881U, // VSLB
|
|
268437887U, // VSLDOI
|
|
268437895U, // VSLH
|
|
268437901U, // VSLO
|
|
268437907U, // VSLW
|
|
272042393U, // VSPLTB
|
|
272042401U, // VSPLTH
|
|
272107945U, // VSPLTISB
|
|
272107955U, // VSPLTISH
|
|
272107965U, // VSPLTISW
|
|
272042439U, // VSPLTW
|
|
268437967U, // VSR
|
|
268437972U, // VSRAB
|
|
268437979U, // VSRAH
|
|
268437986U, // VSRAW
|
|
268437993U, // VSRB
|
|
268437999U, // VSRH
|
|
268438005U, // VSRO
|
|
268438011U, // VSRW
|
|
268438017U, // VSUBCUW
|
|
268438026U, // VSUBFP
|
|
268438034U, // VSUBSBS
|
|
268438043U, // VSUBSHS
|
|
268438052U, // VSUBSWS
|
|
268438061U, // VSUBUBM
|
|
268438070U, // VSUBUBS
|
|
268438079U, // VSUBUHM
|
|
268438088U, // VSUBUHS
|
|
268438097U, // VSUBUWM
|
|
268438106U, // VSUBUWS
|
|
268438115U, // VSUM2SWS
|
|
268438125U, // VSUM4SBS
|
|
268438135U, // VSUM4SHS
|
|
268438145U, // VSUM4UBS
|
|
268438155U, // VSUMSWS
|
|
268470932U, // VUPKHPX
|
|
268470941U, // VUPKHSB
|
|
268470950U, // VUPKHSH
|
|
268470959U, // VUPKLPX
|
|
268470968U, // VUPKLSB
|
|
268470977U, // VUPKLSH
|
|
268438218U, // VXOR
|
|
268962506U, // V_SET0
|
|
268438224U, // XOR
|
|
268438224U, // XOR8
|
|
268450517U, // XORI
|
|
268450517U, // XORI8
|
|
268450523U, // XORIS
|
|
268450523U, // XORIS8
|
|
0U
|
|
};
|
|
|
|
const char *AsmStrs =
|
|
"DBG_VALUE\000add \000addc \000adde \000addi \000addic \000addic. \000ad"
|
|
"dis \000addme \000addze \000\000and \000andc \000andis. \000andi. \000b"
|
|
" \000b\000bctr\000bctrl\000bl \000bla \000cmpd \000cmpdi \000cmpld \000"
|
|
"cmpldi \000cmplw \000cmplwi \000cmpw \000cmpwi \000cntlzd \000cntlzw \000"
|
|
"creqv \000cror \000dcba \000dcbf \000dcbi \000dcbst \000dcbt \000dcbtst"
|
|
" \000dcbz \000dcbzl \000divd \000divdu \000divw \000divwu \000dss \000d"
|
|
"ssall\000dst \000dstst \000dststt \000dstt \000eqv \000extsb \000extsh "
|
|
"\000extsw \000fabs \000fadd \000fadds \000fcfid \000fcmpu \000fctidz \000"
|
|
"fctiwz \000fdiv \000fdivs \000fmadd \000fmadds \000fmr \000fmsub \000fm"
|
|
"subs \000fmul \000fmuls \000fnabs \000fneg \000fnmadd \000fnmadds \000f"
|
|
"nmsub \000fnmsubs \000frsp \000fsel \000fsqrt \000fsqrts \000fsub \000f"
|
|
"subs \000la \000lbz \000lbzu \000lbzx \000ld \000ldarx \000ldu \000ldx "
|
|
"\000ld 2, 8(\000ld 2, 40(1)\000lfd \000lfdx \000lfs \000lfsx \000lha \000"
|
|
"lhau \000lhax \000lhbrx \000lhz \000lhzu \000lhzx \000li \000lis \000lv"
|
|
"ebx \000lvehx \000lvewx \000lvsl \000lvsr \000lvx \000lvxl \000lwa \000"
|
|
"lwarx \000lwax \000lwbrx \000lwz \000lwzu \000lwzx \000mcrf \000mfcr \000"
|
|
"mfctr \000mffs \000mflr \000mfspr \000mfvscr \000mtcrf \000mtctr \000mt"
|
|
"fsb0 \000mtfsb1 \000mtfsf \000mtlr \000mtspr 256, \000mtvscr \000mulhd "
|
|
"\000mulhdu \000mulhw \000mulhwu \000mulld \000mulli \000mullw \000nand "
|
|
"\000neg \000nop\000nor \000or \000orc \000ori \000oris \000rldcl \000rl"
|
|
"dicl \000rldicr \000rldimi \000rlwimi \000rlwinm \000rlwinm. \000rlwnm "
|
|
"\000sld \000slw \000srad \000sradi \000sraw \000srawi \000srd \000srw \000"
|
|
"stb \000stbu \000stbx \000std \000stdcx. \000stdu \000stdux \000stdx \000"
|
|
"stfd \000stfdu \000stfdx \000stfiwx \000stfs \000stfsu \000stfsx \000st"
|
|
"h \000sthbrx \000sthu \000sthx \000stvebx \000stvehx \000stvewx \000stv"
|
|
"x \000stvxl \000stw \000stwbrx \000stwcx. \000stwu \000stwux \000stwx \000"
|
|
"subf \000subfc \000subfe \000subfic \000subfme \000subfze \000sync\000b"
|
|
"a \000#TC_RETURNa \000#TC_RETURNa8 \000#TC_RETURNd \000#TC_RETURNd8 \000"
|
|
"#TC_RETURNr \000#TC_RETURNr8 \000trap\000UPDATE_VRSAVE \000vaddcuw \000"
|
|
"vaddfp \000vaddsbs \000vaddshs \000vaddsws \000vaddubm \000vaddubs \000"
|
|
"vadduhm \000vadduhs \000vadduwm \000vadduws \000vand \000vandc \000vavg"
|
|
"sb \000vavgsh \000vavgsw \000vavgub \000vavguh \000vavguw \000vcfsx \000"
|
|
"vcfux \000vcmpbfp \000vcmpbfp. \000vcmpeqfp \000vcmpeqfp. \000vcmpequb "
|
|
"\000vcmpequb. \000vcmpequh \000vcmpequh. \000vcmpequw \000vcmpequw. \000"
|
|
"vcmpgefp \000vcmpgefp. \000vcmpgtfp \000vcmpgtfp. \000vcmpgtsb \000vcmp"
|
|
"gtsb. \000vcmpgtsh \000vcmpgtsh. \000vcmpgtsw \000vcmpgtsw. \000vcmpgtu"
|
|
"b \000vcmpgtub. \000vcmpgtuh \000vcmpgtuh. \000vcmpgtuw \000vcmpgtuw. \000"
|
|
"vctsxs \000vctuxs \000vexptefp \000vlogefp \000vmaddfp \000vmaxfp \000v"
|
|
"maxsb \000vmaxsh \000vmaxsw \000vmaxub \000vmaxuh \000vmaxuw \000vmhadd"
|
|
"shs \000vmhraddshs \000vminfp \000vminsb \000vminsh \000vminsw \000vmin"
|
|
"ub \000vminuh \000vminuw \000vmladduhm \000vmrghb \000vmrghh \000vmrghw"
|
|
" \000vmrglb \000vmrglh \000vmrglw \000vmsummbm \000vmsumshm \000vmsumsh"
|
|
"s \000vmsumubm \000vmsumuhm \000vmsumuhs \000vmulesb \000vmulesh \000vm"
|
|
"uleub \000vmuleuh \000vmulosb \000vmulosh \000vmuloub \000vmulouh \000v"
|
|
"nmsubfp \000vnor \000vor \000vperm \000vpkpx \000vpkshss \000vpkshus \000"
|
|
"vpkswss \000vpkswus \000vpkuhum \000vpkuhus \000vpkuwum \000vpkuwus \000"
|
|
"vrefp \000vrfim \000vrfin \000vrfip \000vrfiz \000vrlb \000vrlh \000vrl"
|
|
"w \000vrsqrtefp \000vsel \000vsl \000vslb \000vsldoi \000vslh \000vslo "
|
|
"\000vslw \000vspltb \000vsplth \000vspltisb \000vspltish \000vspltisw \000"
|
|
"vspltw \000vsr \000vsrab \000vsrah \000vsraw \000vsrb \000vsrh \000vsro"
|
|
" \000vsrw \000vsubcuw \000vsubfp \000vsubsbs \000vsubshs \000vsubsws \000"
|
|
"vsububm \000vsububs \000vsubuhm \000vsubuhs \000vsubuwm \000vsubuws \000"
|
|
"vsum2sws \000vsum4sbs \000vsum4shs \000vsum4ubs \000vsumsws \000vupkhpx"
|
|
" \000vupkhsb \000vupkhsh \000vupklpx \000vupklsb \000vupklsh \000vxor \000"
|
|
"xor \000xori \000xoris \000";
|
|
|
|
O << "\t";
|
|
|
|
// Emit the opcode for the instruction.
|
|
unsigned Bits = OpInfo[MI->getOpcode()];
|
|
assert(Bits != 0 && "Cannot print this instruction.");
|
|
O << AsmStrs+(Bits & 4095)-1;
|
|
|
|
|
|
// Fragment 0 encoded into 4 bits for 14 unique commands.
|
|
switch ((Bits >> 28) & 15) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// DBG_VALUE, BCTR, BCTRL8_Darwin, BCTRL8_ELF, BCTRL_Darwin, BCTRL_SVR4, ...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
|
|
printOperand(MI, 0);
|
|
break;
|
|
case 2:
|
|
// ADJCALLSTACKDOWN, ADJCALLSTACKUP, ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP...
|
|
PrintSpecial(MI, "comment");
|
|
break;
|
|
case 3:
|
|
// B
|
|
printBranchOperand(MI, 0);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// BCC, BLR
|
|
printPredicateOperand(MI, 0, "cc");
|
|
break;
|
|
case 5:
|
|
// BL8_Darwin, BL8_ELF, BL_Darwin, BL_SVR4, TAILB, TAILB8, TCRETURNdi, TC...
|
|
printCallOperand(MI, 0);
|
|
break;
|
|
case 6:
|
|
// BLA8_Darwin, BLA8_ELF, BLA_Darwin, BLA_SVR4, TAILBA, TAILBA8, TCRETURN...
|
|
printAbsAddrOperand(MI, 0);
|
|
break;
|
|
case 7:
|
|
// DCBA, DCBF, DCBI, DCBST, DCBT, DCBTST, DCBZ, DCBZL
|
|
printMemRegReg(MI, 0);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// DSS
|
|
printU5ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << ", ";
|
|
printU5ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// MTCRF
|
|
printcrbitm(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// MTFSB0, MTFSB1
|
|
printU5ImmOperand(MI, 0);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// MTFSF, STBU, STBU8, STDU, STFDU, STFSU, STHU, STHU8, STWU
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
break;
|
|
case 13:
|
|
// MovePCtoLR, MovePCtoLR8
|
|
printPICLabel(MI, 0);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 1 encoded into 6 bits for 47 unique commands.
|
|
switch ((Bits >> 22) & 63) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
|
|
O << ", ";
|
|
break;
|
|
case 1:
|
|
// ADJCALLSTACKDOWN
|
|
O << " ADJCALLSTACKDOWN";
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ADJCALLSTACKUP
|
|
O << " ADJCALLSTACKUP";
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ATOMIC_CMP_SWAP_I16
|
|
O << " ATOMIC_CMP_SWAP_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ATOMIC_CMP_SWAP_I32
|
|
O << " ATOMIC_CMP_SWAP_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 5:
|
|
// ATOMIC_CMP_SWAP_I64
|
|
O << " ATOMIC_CMP_SWAP_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 6:
|
|
// ATOMIC_CMP_SWAP_I8
|
|
O << " ATOMIC_CMP_SWAP_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 7:
|
|
// ATOMIC_LOAD_ADD_I16
|
|
O << " ATOMIC_LOAD_ADD_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 8:
|
|
// ATOMIC_LOAD_ADD_I32
|
|
O << " ATOMIC_LOAD_ADD_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 9:
|
|
// ATOMIC_LOAD_ADD_I64
|
|
O << " ATOMIC_LOAD_ADD_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 10:
|
|
// ATOMIC_LOAD_ADD_I8
|
|
O << " ATOMIC_LOAD_ADD_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 11:
|
|
// ATOMIC_LOAD_AND_I16
|
|
O << " ATOMIC_LOAD_AND_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 12:
|
|
// ATOMIC_LOAD_AND_I32
|
|
O << " ATOMIC_LOAD_AND_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 13:
|
|
// ATOMIC_LOAD_AND_I64
|
|
O << " ATOMIC_LOAD_AND_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 14:
|
|
// ATOMIC_LOAD_AND_I8
|
|
O << " ATOMIC_LOAD_AND_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 15:
|
|
// ATOMIC_LOAD_NAND_I16
|
|
O << " ATOMIC_LOAD_NAND_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 16:
|
|
// ATOMIC_LOAD_NAND_I32
|
|
O << " ATOMIC_LOAD_NAND_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 17:
|
|
// ATOMIC_LOAD_NAND_I64
|
|
O << " ATOMIC_LOAD_NAND_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 18:
|
|
// ATOMIC_LOAD_NAND_I8
|
|
O << " ATOMIC_LOAD_NAND_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 19:
|
|
// ATOMIC_LOAD_OR_I16
|
|
O << " ATOMIC_LOAD_OR_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 20:
|
|
// ATOMIC_LOAD_OR_I32
|
|
O << " ATOMIC_LOAD_OR_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 21:
|
|
// ATOMIC_LOAD_OR_I64
|
|
O << " ATOMIC_LOAD_OR_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 22:
|
|
// ATOMIC_LOAD_OR_I8
|
|
O << " ATOMIC_LOAD_OR_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 23:
|
|
// ATOMIC_LOAD_SUB_I16
|
|
O << " ATOMIC_LOAD_SUB_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 24:
|
|
// ATOMIC_LOAD_SUB_I32
|
|
O << " ATOMIC_LOAD_SUB_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 25:
|
|
// ATOMIC_LOAD_SUB_I64
|
|
O << " ATOMIC_LOAD_SUB_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 26:
|
|
// ATOMIC_LOAD_SUB_I8
|
|
O << " ATOMIC_LOAD_SUB_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 27:
|
|
// ATOMIC_LOAD_XOR_I16
|
|
O << " ATOMIC_LOAD_XOR_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 28:
|
|
// ATOMIC_LOAD_XOR_I32
|
|
O << " ATOMIC_LOAD_XOR_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 29:
|
|
// ATOMIC_LOAD_XOR_I64
|
|
O << " ATOMIC_LOAD_XOR_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 30:
|
|
// ATOMIC_LOAD_XOR_I8
|
|
O << " ATOMIC_LOAD_XOR_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 31:
|
|
// ATOMIC_SWAP_I16
|
|
O << " ATOMIC_SWAP_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 32:
|
|
// ATOMIC_SWAP_I32
|
|
O << " ATOMIC_SWAP_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 33:
|
|
// ATOMIC_SWAP_I64
|
|
O << " ATOMIC_SWAP_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 34:
|
|
// ATOMIC_SWAP_I8
|
|
O << " ATOMIC_SWAP_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 35:
|
|
// BCC, TCRETURNai, TCRETURNai8, TCRETURNdi, TCRETURNdi8, TCRETURNri, TCR...
|
|
O << ' ';
|
|
break;
|
|
case 36:
|
|
// BL8_Darwin, BL8_ELF, BLA8_Darwin, BLA8_ELF, BLA_Darwin, BLA_SVR4, BL_D...
|
|
return;
|
|
break;
|
|
case 37:
|
|
// BLR
|
|
O << "lr ";
|
|
printPredicateOperand(MI, 0, "reg");
|
|
return;
|
|
break;
|
|
case 38:
|
|
// DYNALLOC
|
|
O << " DYNALLOC ";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printMemRegImm(MI, 2);
|
|
return;
|
|
break;
|
|
case 39:
|
|
// DYNALLOC8
|
|
O << " DYNALLOC8 ";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printMemRegImm(MI, 2);
|
|
return;
|
|
break;
|
|
case 40:
|
|
// LDinto_toc
|
|
O << ')';
|
|
return;
|
|
break;
|
|
case 41:
|
|
// MFVRSAVE
|
|
O << ", 256";
|
|
return;
|
|
break;
|
|
case 42:
|
|
// MTFSF
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 43:
|
|
// SELECT_CC_F4, SELECT_CC_F8, SELECT_CC_I4, SELECT_CC_I8, SELECT_CC_VRRC
|
|
O << " SELECT_CC PSEUDO!";
|
|
return;
|
|
break;
|
|
case 44:
|
|
// SPILL_CR
|
|
O << " SPILL_CR ";
|
|
printOperand(MI, 0);
|
|
O << ' ';
|
|
printMemRegImm(MI, 1);
|
|
return;
|
|
break;
|
|
case 45:
|
|
// STBU, STBU8, STFDU, STFSU, STHU, STHU8, STWU
|
|
printSymbolLo(MI, 2);
|
|
O << '(';
|
|
printOperand(MI, 3);
|
|
O << ')';
|
|
return;
|
|
break;
|
|
case 46:
|
|
// STDU
|
|
printS16X4ImmOperand(MI, 2);
|
|
O << '(';
|
|
printOperand(MI, 3);
|
|
O << ')';
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 2 encoded into 4 bits for 15 unique commands.
|
|
switch ((Bits >> 18) & 15) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 1:
|
|
// BCC
|
|
printPredicateOperand(MI, 0, "reg");
|
|
O << ", ";
|
|
printBranchOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// CRSET, V_SET0
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 0);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// LA, LHAU8
|
|
printSymbolLo(MI, 2);
|
|
O << '(';
|
|
break;
|
|
case 4:
|
|
// LBZ, LBZ8, LFD, LFS, LHA, LHA8, LHZ, LHZ8, LWZ, LWZ8, STB, STB8, STFD,...
|
|
printMemRegImm(MI, 1);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// LBZU, LBZU8, LFDU, LFSU, LHAU, LHZU, LHZU8, LWZU, LWZU8
|
|
printMemRegImm(MI, 2);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// LBZX, LBZX8, LDARX, LDX, LFDX, LFSX, LHAX, LHAX8, LHBRX, LHZX, LHZX8, ...
|
|
printMemRegReg(MI, 1);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// LD, LWA, STD, STD_32
|
|
printMemRegImmShifted(MI, 1);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// LDU
|
|
printMemRegImmShifted(MI, 2);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// LDtoc
|
|
printTOCEntryLabel(MI, 1);
|
|
O << '(';
|
|
printOperand(MI, 2);
|
|
O << ')';
|
|
return;
|
|
break;
|
|
case 10:
|
|
// LI, LI8
|
|
printSymbolLo(MI, 1);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// LIS, LIS8
|
|
printSymbolHi(MI, 1);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// MFOCRF
|
|
printcrbitm(MI, 1);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// RLDIMI, RLWIMI, VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTH, VSPLTW
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
break;
|
|
case 14:
|
|
// VSPLTISB, VSPLTISH, VSPLTISW
|
|
printS5ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 3 encoded into 3 bits for 7 unique commands.
|
|
switch ((Bits >> 15) & 7) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
|
|
O << ", ";
|
|
break;
|
|
case 1:
|
|
// ADDME, ADDME8, ADDZE, ADDZE8, CNTLZD, CNTLZW, EXTSB, EXTSB8, EXTSH, EX...
|
|
return;
|
|
break;
|
|
case 2:
|
|
// LA
|
|
printOperand(MI, 1);
|
|
O << ')';
|
|
return;
|
|
break;
|
|
case 3:
|
|
// LHAU8
|
|
printOperand(MI, 3);
|
|
O << ')';
|
|
return;
|
|
break;
|
|
case 4:
|
|
// RLDIMI
|
|
printU6ImmOperand(MI, 3);
|
|
O << ", ";
|
|
printU6ImmOperand(MI, 4);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// RLWIMI
|
|
printU5ImmOperand(MI, 3);
|
|
O << ", ";
|
|
printU5ImmOperand(MI, 4);
|
|
O << ", ";
|
|
printU5ImmOperand(MI, 5);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTH, VSPLTW
|
|
printU5ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 4 encoded into 3 bits for 6 unique commands.
|
|
switch ((Bits >> 12) & 7) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, AND, AND8, ANDC, ANDC8, CMPD, CM...
|
|
printOperand(MI, 2);
|
|
break;
|
|
case 1:
|
|
// ADDI, ADDI8, ADDIC, ADDIC8, ADDICo, CMPDI, CMPWI, MULLI, SUBFIC, SUBFI...
|
|
printS16ImmOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ADDIS, ADDIS8
|
|
printSymbolHi(MI, 2);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ANDISo, ANDISo8, ANDIo, ANDIo8, CMPLDI, CMPLWI, ORI, ORI8, ORIS, ORIS8...
|
|
printU16ImmOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// RLDICL, RLDICR, SRADI
|
|
printU6ImmOperand(MI, 2);
|
|
break;
|
|
case 5:
|
|
// RLWINM, RLWINMo, SRAWI
|
|
printU5ImmOperand(MI, 2);
|
|
break;
|
|
}
|
|
|
|
switch (MI->getOpcode()) {
|
|
case PPC::ADD4:
|
|
case PPC::ADD8:
|
|
case PPC::ADDC:
|
|
case PPC::ADDC8:
|
|
case PPC::ADDE:
|
|
case PPC::ADDE8:
|
|
case PPC::AND:
|
|
case PPC::AND8:
|
|
case PPC::ANDC:
|
|
case PPC::ANDC8:
|
|
case PPC::CMPD:
|
|
case PPC::CMPLD:
|
|
case PPC::CMPLW:
|
|
case PPC::CMPW:
|
|
case PPC::CREQV:
|
|
case PPC::CROR:
|
|
case PPC::DIVD:
|
|
case PPC::DIVDU:
|
|
case PPC::DIVW:
|
|
case PPC::DIVWU:
|
|
case PPC::EQV:
|
|
case PPC::EQV8:
|
|
case PPC::FADD:
|
|
case PPC::FADDS:
|
|
case PPC::FADDrtz:
|
|
case PPC::FCMPUD:
|
|
case PPC::FCMPUS:
|
|
case PPC::FDIV:
|
|
case PPC::FDIVS:
|
|
case PPC::FMUL:
|
|
case PPC::FMULS:
|
|
case PPC::FSUB:
|
|
case PPC::FSUBS:
|
|
case PPC::MULHD:
|
|
case PPC::MULHDU:
|
|
case PPC::MULHW:
|
|
case PPC::MULHWU:
|
|
case PPC::MULLD:
|
|
case PPC::MULLW:
|
|
case PPC::NAND:
|
|
case PPC::NAND8:
|
|
case PPC::NOR:
|
|
case PPC::NOR8:
|
|
case PPC::OR:
|
|
case PPC::OR4To8:
|
|
case PPC::OR8:
|
|
case PPC::OR8To4:
|
|
case PPC::ORC:
|
|
case PPC::ORC8:
|
|
case PPC::SLD:
|
|
case PPC::SLW:
|
|
case PPC::SRAD:
|
|
case PPC::SRADI:
|
|
case PPC::SRAW:
|
|
case PPC::SRAWI:
|
|
case PPC::SRD:
|
|
case PPC::SRW:
|
|
case PPC::STWUX:
|
|
case PPC::SUBF:
|
|
case PPC::SUBF8:
|
|
case PPC::SUBFC:
|
|
case PPC::SUBFC8:
|
|
case PPC::SUBFE:
|
|
case PPC::SUBFE8:
|
|
case PPC::VADDCUW:
|
|
case PPC::VADDFP:
|
|
case PPC::VADDSBS:
|
|
case PPC::VADDSHS:
|
|
case PPC::VADDSWS:
|
|
case PPC::VADDUBM:
|
|
case PPC::VADDUBS:
|
|
case PPC::VADDUHM:
|
|
case PPC::VADDUHS:
|
|
case PPC::VADDUWM:
|
|
case PPC::VADDUWS:
|
|
case PPC::VAND:
|
|
case PPC::VANDC:
|
|
case PPC::VAVGSB:
|
|
case PPC::VAVGSH:
|
|
case PPC::VAVGSW:
|
|
case PPC::VAVGUB:
|
|
case PPC::VAVGUH:
|
|
case PPC::VAVGUW:
|
|
case PPC::VCMPBFP:
|
|
case PPC::VCMPBFPo:
|
|
case PPC::VCMPEQFP:
|
|
case PPC::VCMPEQFPo:
|
|
case PPC::VCMPEQUB:
|
|
case PPC::VCMPEQUBo:
|
|
case PPC::VCMPEQUH:
|
|
case PPC::VCMPEQUHo:
|
|
case PPC::VCMPEQUW:
|
|
case PPC::VCMPEQUWo:
|
|
case PPC::VCMPGEFP:
|
|
case PPC::VCMPGEFPo:
|
|
case PPC::VCMPGTFP:
|
|
case PPC::VCMPGTFPo:
|
|
case PPC::VCMPGTSB:
|
|
case PPC::VCMPGTSBo:
|
|
case PPC::VCMPGTSH:
|
|
case PPC::VCMPGTSHo:
|
|
case PPC::VCMPGTSW:
|
|
case PPC::VCMPGTSWo:
|
|
case PPC::VCMPGTUB:
|
|
case PPC::VCMPGTUBo:
|
|
case PPC::VCMPGTUH:
|
|
case PPC::VCMPGTUHo:
|
|
case PPC::VCMPGTUW:
|
|
case PPC::VCMPGTUWo:
|
|
case PPC::VMAXFP:
|
|
case PPC::VMAXSB:
|
|
case PPC::VMAXSH:
|
|
case PPC::VMAXSW:
|
|
case PPC::VMAXUB:
|
|
case PPC::VMAXUH:
|
|
case PPC::VMAXUW:
|
|
case PPC::VMINFP:
|
|
case PPC::VMINSB:
|
|
case PPC::VMINSH:
|
|
case PPC::VMINSW:
|
|
case PPC::VMINUB:
|
|
case PPC::VMINUH:
|
|
case PPC::VMINUW:
|
|
case PPC::VMRGHB:
|
|
case PPC::VMRGHH:
|
|
case PPC::VMRGHW:
|
|
case PPC::VMRGLB:
|
|
case PPC::VMRGLH:
|
|
case PPC::VMRGLW:
|
|
case PPC::VMULESB:
|
|
case PPC::VMULESH:
|
|
case PPC::VMULEUB:
|
|
case PPC::VMULEUH:
|
|
case PPC::VMULOSB:
|
|
case PPC::VMULOSH:
|
|
case PPC::VMULOUB:
|
|
case PPC::VMULOUH:
|
|
case PPC::VNOR:
|
|
case PPC::VOR:
|
|
case PPC::VPKPX:
|
|
case PPC::VPKSHSS:
|
|
case PPC::VPKSHUS:
|
|
case PPC::VPKSWSS:
|
|
case PPC::VPKSWUS:
|
|
case PPC::VPKUHUM:
|
|
case PPC::VPKUHUS:
|
|
case PPC::VPKUWUM:
|
|
case PPC::VPKUWUS:
|
|
case PPC::VRLB:
|
|
case PPC::VRLH:
|
|
case PPC::VRLW:
|
|
case PPC::VSL:
|
|
case PPC::VSLB:
|
|
case PPC::VSLH:
|
|
case PPC::VSLO:
|
|
case PPC::VSLW:
|
|
case PPC::VSR:
|
|
case PPC::VSRAB:
|
|
case PPC::VSRAH:
|
|
case PPC::VSRAW:
|
|
case PPC::VSRB:
|
|
case PPC::VSRH:
|
|
case PPC::VSRO:
|
|
case PPC::VSRW:
|
|
case PPC::VSUBCUW:
|
|
case PPC::VSUBFP:
|
|
case PPC::VSUBSBS:
|
|
case PPC::VSUBSHS:
|
|
case PPC::VSUBSWS:
|
|
case PPC::VSUBUBM:
|
|
case PPC::VSUBUBS:
|
|
case PPC::VSUBUHM:
|
|
case PPC::VSUBUHS:
|
|
case PPC::VSUBUWM:
|
|
case PPC::VSUBUWS:
|
|
case PPC::VSUM2SWS:
|
|
case PPC::VSUM4SBS:
|
|
case PPC::VSUM4SHS:
|
|
case PPC::VSUM4UBS:
|
|
case PPC::VSUMSWS:
|
|
case PPC::VXOR:
|
|
case PPC::XOR:
|
|
case PPC::XOR8:
|
|
return;
|
|
break;
|
|
case PPC::FMADD:
|
|
case PPC::FMADDS:
|
|
case PPC::FMSUB:
|
|
case PPC::FMSUBS:
|
|
case PPC::FNMADD:
|
|
case PPC::FNMADDS:
|
|
case PPC::FNMSUB:
|
|
case PPC::FNMSUBS:
|
|
case PPC::FSELD:
|
|
case PPC::FSELS:
|
|
case PPC::RLDCL:
|
|
case PPC::RLDICL:
|
|
case PPC::RLDICR:
|
|
case PPC::VMADDFP:
|
|
case PPC::VMHADDSHS:
|
|
case PPC::VMHRADDSHS:
|
|
case PPC::VMLADDUHM:
|
|
case PPC::VMSUMMBM:
|
|
case PPC::VMSUMSHM:
|
|
case PPC::VMSUMSHS:
|
|
case PPC::VMSUMUBM:
|
|
case PPC::VMSUMUHM:
|
|
case PPC::VMSUMUHS:
|
|
case PPC::VNMSUBFP:
|
|
case PPC::VPERM:
|
|
case PPC::VSEL:
|
|
case PPC::VSLDOI:
|
|
O << ", ";
|
|
switch (MI->getOpcode()) {
|
|
case PPC::FMADD:
|
|
case PPC::FMADDS:
|
|
case PPC::FMSUB:
|
|
case PPC::FMSUBS:
|
|
case PPC::FNMADD:
|
|
case PPC::FNMADDS:
|
|
case PPC::FNMSUB:
|
|
case PPC::FNMSUBS:
|
|
case PPC::FSELD:
|
|
case PPC::FSELS:
|
|
case PPC::VMADDFP:
|
|
case PPC::VMHADDSHS:
|
|
case PPC::VMHRADDSHS:
|
|
case PPC::VMLADDUHM:
|
|
case PPC::VMSUMMBM:
|
|
case PPC::VMSUMSHM:
|
|
case PPC::VMSUMSHS:
|
|
case PPC::VMSUMUBM:
|
|
case PPC::VMSUMUHM:
|
|
case PPC::VMSUMUHS:
|
|
case PPC::VNMSUBFP:
|
|
case PPC::VPERM:
|
|
case PPC::VSEL: printOperand(MI, 3); break;
|
|
case PPC::RLDCL:
|
|
case PPC::RLDICL:
|
|
case PPC::RLDICR: printU6ImmOperand(MI, 3); break;
|
|
case PPC::VSLDOI: printU5ImmOperand(MI, 3); break;
|
|
}
|
|
return;
|
|
break;
|
|
case PPC::RLWINM:
|
|
case PPC::RLWINMo:
|
|
case PPC::RLWNM:
|
|
O << ", ";
|
|
printU5ImmOperand(MI, 3);
|
|
O << ", ";
|
|
printU5ImmOperand(MI, 4);
|
|
return;
|
|
break;
|
|
}
|
|
return;
|
|
}
|
|
|
|
|
|
/// getRegisterName - This method is automatically generated by tblgen
|
|
/// from the register set description. This returns the assembler name
|
|
/// for the specified register.
|
|
const char *PPCAsmPrinter::getRegisterName(unsigned RegNo) {
|
|
assert(RegNo && RegNo < 176 && "Invalid register number!");
|
|
|
|
static const unsigned RegAsmOffset[] = {
|
|
0, 3, 7, 9, 11, 13, 15, 19, 21, 23, 25, 27, 31, 34,
|
|
36, 38, 41, 45, 48, 51, 54, 57, 61, 64, 67, 70, 73, 77,
|
|
80, 83, 86, 89, 93, 96, 99, 102, 105, 109, 112, 115, 118, 121,
|
|
121, 125, 128, 131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171,
|
|
174, 178, 182, 186, 190, 194, 198, 202, 206, 210, 214, 217, 221, 225,
|
|
228, 231, 234, 237, 240, 243, 243, 246, 249, 252, 256, 260, 264, 268,
|
|
272, 276, 280, 284, 288, 292, 295, 299, 303, 307, 311, 315, 319, 323,
|
|
327, 331, 335, 338, 342, 346, 349, 352, 355, 358, 361, 364, 382, 385,
|
|
388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 431, 435, 439,
|
|
443, 447, 451, 455, 459, 463, 467, 471, 474, 478, 482, 485, 488, 491,
|
|
494, 497, 500, 246, 249, 252, 256, 260, 264, 268, 272, 276, 280, 284,
|
|
288, 292, 295, 299, 303, 307, 311, 315, 319, 323, 327, 331, 335, 338,
|
|
342, 346, 349, 352, 355, 358, 361, 0
|
|
};
|
|
|
|
const char *AsmStrs =
|
|
"ca\000cr0\0002\0001\0000\0003\000cr1\0006\0005\0004\0007\000cr2\00010\000"
|
|
"9\0008\00011\000cr3\00014\00013\00012\00015\000cr4\00018\00017\00016\000"
|
|
"19\000cr5\00022\00021\00020\00023\000cr6\00026\00025\00024\00027\000cr7"
|
|
"\00030\00029\00028\00031\000ctr\000f0\000f1\000f10\000f11\000f12\000f13"
|
|
"\000f14\000f15\000f16\000f17\000f18\000f19\000f2\000f20\000f21\000f22\000"
|
|
"f23\000f24\000f25\000f26\000f27\000f28\000f29\000f3\000f30\000f31\000f4"
|
|
"\000f5\000f6\000f7\000f8\000f9\000lr\000r0\000r1\000r10\000r11\000r12\000"
|
|
"r13\000r14\000r15\000r16\000r17\000r18\000r19\000r2\000r20\000r21\000r2"
|
|
"2\000r23\000r24\000r25\000r26\000r27\000r28\000r29\000r3\000r30\000r31\000"
|
|
"r4\000r5\000r6\000r7\000r8\000r9\000**ROUNDING MODE**\000v0\000v1\000v1"
|
|
"0\000v11\000v12\000v13\000v14\000v15\000v16\000v17\000v18\000v19\000v2\000"
|
|
"v20\000v21\000v22\000v23\000v24\000v25\000v26\000v27\000v28\000v29\000v"
|
|
"3\000v30\000v31\000v4\000v5\000v6\000v7\000v8\000v9\000VRsave\000";
|
|
return AsmStrs+RegAsmOffset[RegNo-1];
|
|
}
|
|
|
|
|
|
#ifdef GET_INSTRUCTION_NAME
|
|
#undef GET_INSTRUCTION_NAME
|
|
|
|
/// getInstructionName: This method is automatically generated by tblgen
|
|
/// from the instruction set description. This returns the enum name of the
|
|
/// specified instruction.
|
|
const char *PPCAsmPrinter::getInstructionName(unsigned Opcode) {
|
|
assert(Opcode < 519 && "Invalid instruction number!");
|
|
|
|
static const unsigned InstAsmOffset[] = {
|
|
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 135,
|
|
140, 145, 151, 156, 162, 167, 173, 179, 186, 193, 199, 206, 212, 219,
|
|
225, 232, 249, 264, 268, 273, 278, 284, 291, 299, 305, 312, 332, 352,
|
|
372, 391, 411, 431, 451, 470, 490, 510, 530, 549, 570, 591, 612, 632,
|
|
651, 670, 689, 707, 727, 747, 767, 786, 806, 826, 846, 865, 881, 897,
|
|
913, 928, 930, 934, 939, 953, 964, 977, 988, 999, 1007, 1019, 1028, 1039,
|
|
1048, 1052, 1062, 1070, 1075, 1081, 1087, 1094, 1100, 1107, 1112, 1118, 1125, 1132,
|
|
1138, 1143, 1149, 1154, 1159, 1164, 1170, 1175, 1182, 1187, 1193, 1198, 1204, 1209,
|
|
1215, 1219, 1226, 1230, 1236, 1242, 1250, 1257, 1266, 1271, 1278, 1287, 1297, 1301,
|
|
1306, 1312, 1319, 1325, 1332, 1338, 1347, 1359, 1365, 1371, 1376, 1382, 1390, 1396,
|
|
1403, 1410, 1417, 1424, 1429, 1435, 1441, 1448, 1452, 1458, 1464, 1471, 1476, 1482,
|
|
1489, 1496, 1502, 1508, 1515, 1523, 1530, 1538, 1543, 1549, 1555, 1561, 1568, 1573,
|
|
1579, 1582, 1586, 1591, 1596, 1602, 1607, 1613, 1616, 1622, 1626, 1630, 1641, 1647,
|
|
1661, 1665, 1670, 1675, 1679, 1684, 1689, 1693, 1698, 1703, 1709, 1714, 1720, 1726,
|
|
1730, 1735, 1740, 1746, 1751, 1757, 1760, 1764, 1768, 1773, 1779, 1785, 1791, 1796,
|
|
1801, 1805, 1810, 1814, 1820, 1825, 1831, 1835, 1840, 1845, 1851, 1856, 1862, 1867,
|
|
1872, 1878, 1885, 1890, 1895, 1901, 1908, 1917, 1924, 1930, 1936, 1943, 1950, 1957,
|
|
1963, 1968, 1974, 1983, 1990, 1996, 2003, 2009, 2016, 2022, 2028, 2034, 2045, 2057,
|
|
2062, 2068, 2072, 2077, 2081, 2085, 2090, 2093, 2100, 2104, 2111, 2115, 2120, 2124,
|
|
2129, 2134, 2140, 2146, 2153, 2160, 2167, 2174, 2181, 2189, 2195, 2208, 2221, 2234,
|
|
2247, 2262, 2266, 2270, 2279, 2284, 2290, 2295, 2301, 2305, 2309, 2313, 2318, 2323,
|
|
2329, 2334, 2340, 2344, 2350, 2355, 2361, 2366, 2374, 2381, 2386, 2392, 2398, 2405,
|
|
2410, 2416, 2422, 2426, 2431, 2438, 2443, 2449, 2454, 2460, 2467, 2474, 2481, 2486,
|
|
2492, 2496, 2501, 2508, 2514, 2519, 2525, 2530, 2536, 2541, 2547, 2553, 2560, 2566,
|
|
2573, 2580, 2588, 2595, 2603, 2610, 2618, 2623, 2629, 2636, 2643, 2651, 2660, 2670,
|
|
2681, 2693, 2704, 2716, 2727, 2739, 2744, 2758, 2766, 2773, 2781, 2789, 2797, 2805,
|
|
2813, 2821, 2829, 2837, 2845, 2850, 2856, 2863, 2870, 2877, 2884, 2891, 2898, 2904,
|
|
2910, 2918, 2927, 2936, 2946, 2955, 2965, 2974, 2984, 2993, 3003, 3012, 3022, 3031,
|
|
3041, 3050, 3060, 3069, 3079, 3088, 3098, 3107, 3117, 3126, 3136, 3145, 3155, 3162,
|
|
3169, 3178, 3186, 3194, 3201, 3208, 3215, 3222, 3229, 3236, 3243, 3253, 3264, 3271,
|
|
3278, 3285, 3292, 3299, 3306, 3313, 3323, 3330, 3337, 3344, 3351, 3358, 3365, 3374,
|
|
3383, 3392, 3401, 3410, 3419, 3427, 3435, 3443, 3451, 3459, 3467, 3475, 3483, 3492,
|
|
3497, 3501, 3507, 3513, 3521, 3529, 3537, 3545, 3553, 3561, 3569, 3577, 3583, 3589,
|
|
3595, 3601, 3607, 3612, 3617, 3622, 3632, 3637, 3641, 3646, 3653, 3658, 3663, 3668,
|
|
3675, 3682, 3691, 3700, 3709, 3716, 3720, 3726, 3732, 3738, 3743, 3748, 3753, 3758,
|
|
3766, 3773, 3781, 3789, 3797, 3805, 3813, 3821, 3829, 3837, 3845, 3854, 3863, 3872,
|
|
3881, 3889, 3897, 3905, 3913, 3921, 3929, 3937, 3942, 3949, 3953, 3958, 3963, 3969,
|
|
3975, 0
|
|
};
|
|
|
|
const char *Strs =
|
|
"PHI\000INLINEASM\000DBG_LABEL\000EH_LABEL\000GC_LABEL\000KILL\000EXTRAC"
|
|
"T_SUBREG\000INSERT_SUBREG\000IMPLICIT_DEF\000SUBREG_TO_REG\000COPY_TO_R"
|
|
"EGCLASS\000DBG_VALUE\000ADD4\000ADD8\000ADDC\000ADDC8\000ADDE\000ADDE8\000"
|
|
"ADDI\000ADDI8\000ADDIC\000ADDIC8\000ADDICo\000ADDIS\000ADDIS8\000ADDME\000"
|
|
"ADDME8\000ADDZE\000ADDZE8\000ADJCALLSTACKDOWN\000ADJCALLSTACKUP\000AND\000"
|
|
"AND8\000ANDC\000ANDC8\000ANDISo\000ANDISo8\000ANDIo\000ANDIo8\000ATOMIC"
|
|
"_CMP_SWAP_I16\000ATOMIC_CMP_SWAP_I32\000ATOMIC_CMP_SWAP_I64\000ATOMIC_C"
|
|
"MP_SWAP_I8\000ATOMIC_LOAD_ADD_I16\000ATOMIC_LOAD_ADD_I32\000ATOMIC_LOAD"
|
|
"_ADD_I64\000ATOMIC_LOAD_ADD_I8\000ATOMIC_LOAD_AND_I16\000ATOMIC_LOAD_AN"
|
|
"D_I32\000ATOMIC_LOAD_AND_I64\000ATOMIC_LOAD_AND_I8\000ATOMIC_LOAD_NAND_"
|
|
"I16\000ATOMIC_LOAD_NAND_I32\000ATOMIC_LOAD_NAND_I64\000ATOMIC_LOAD_NAND"
|
|
"_I8\000ATOMIC_LOAD_OR_I16\000ATOMIC_LOAD_OR_I32\000ATOMIC_LOAD_OR_I64\000"
|
|
"ATOMIC_LOAD_OR_I8\000ATOMIC_LOAD_SUB_I16\000ATOMIC_LOAD_SUB_I32\000ATOM"
|
|
"IC_LOAD_SUB_I64\000ATOMIC_LOAD_SUB_I8\000ATOMIC_LOAD_XOR_I16\000ATOMIC_"
|
|
"LOAD_XOR_I32\000ATOMIC_LOAD_XOR_I64\000ATOMIC_LOAD_XOR_I8\000ATOMIC_SWA"
|
|
"P_I16\000ATOMIC_SWAP_I32\000ATOMIC_SWAP_I64\000ATOMIC_SWAP_I8\000B\000B"
|
|
"CC\000BCTR\000BCTRL8_Darwin\000BCTRL8_ELF\000BCTRL_Darwin\000BCTRL_SVR4"
|
|
"\000BL8_Darwin\000BL8_ELF\000BLA8_Darwin\000BLA8_ELF\000BLA_Darwin\000B"
|
|
"LA_SVR4\000BLR\000BL_Darwin\000BL_SVR4\000CMPD\000CMPDI\000CMPLD\000CMP"
|
|
"LDI\000CMPLW\000CMPLWI\000CMPW\000CMPWI\000CNTLZD\000CNTLZW\000CREQV\000"
|
|
"CROR\000CRSET\000DCBA\000DCBF\000DCBI\000DCBST\000DCBT\000DCBTST\000DCB"
|
|
"Z\000DCBZL\000DIVD\000DIVDU\000DIVW\000DIVWU\000DSS\000DSSALL\000DST\000"
|
|
"DST64\000DSTST\000DSTST64\000DSTSTT\000DSTSTT64\000DSTT\000DSTT64\000DY"
|
|
"NALLOC\000DYNALLOC8\000EQV\000EQV8\000EXTSB\000EXTSB8\000EXTSH\000EXTSH"
|
|
"8\000EXTSW\000EXTSW_32\000EXTSW_32_64\000FABSD\000FABSS\000FADD\000FADD"
|
|
"S\000FADDrtz\000FCFID\000FCMPUD\000FCMPUS\000FCTIDZ\000FCTIWZ\000FDIV\000"
|
|
"FDIVS\000FMADD\000FMADDS\000FMR\000FMRSD\000FMSUB\000FMSUBS\000FMUL\000"
|
|
"FMULS\000FNABSD\000FNABSS\000FNEGD\000FNEGS\000FNMADD\000FNMADDS\000FNM"
|
|
"SUB\000FNMSUBS\000FRSP\000FSELD\000FSELS\000FSQRT\000FSQRTS\000FSUB\000"
|
|
"FSUBS\000LA\000LBZ\000LBZ8\000LBZU\000LBZU8\000LBZX\000LBZX8\000LD\000L"
|
|
"DARX\000LDU\000LDX\000LDinto_toc\000LDtoc\000LDtoc_restore\000LFD\000LF"
|
|
"DU\000LFDX\000LFS\000LFSU\000LFSX\000LHA\000LHA8\000LHAU\000LHAU8\000LH"
|
|
"AX\000LHAX8\000LHBRX\000LHZ\000LHZ8\000LHZU\000LHZU8\000LHZX\000LHZX8\000"
|
|
"LI\000LI8\000LIS\000LIS8\000LVEBX\000LVEHX\000LVEWX\000LVSL\000LVSR\000"
|
|
"LVX\000LVXL\000LWA\000LWARX\000LWAX\000LWBRX\000LWZ\000LWZ8\000LWZU\000"
|
|
"LWZU8\000LWZX\000LWZX8\000MCRF\000MFCR\000MFCTR\000MFCTR8\000MFFS\000MF"
|
|
"LR\000MFLR8\000MFOCRF\000MFVRSAVE\000MFVSCR\000MTCRF\000MTCTR\000MTCTR8"
|
|
"\000MTFSB0\000MTFSB1\000MTFSF\000MTLR\000MTLR8\000MTVRSAVE\000MTVSCR\000"
|
|
"MULHD\000MULHDU\000MULHW\000MULHWU\000MULLD\000MULLI\000MULLW\000MovePC"
|
|
"toLR\000MovePCtoLR8\000NAND\000NAND8\000NEG\000NEG8\000NOP\000NOR\000NO"
|
|
"R8\000OR\000OR4To8\000OR8\000OR8To4\000ORC\000ORC8\000ORI\000ORI8\000OR"
|
|
"IS\000ORIS8\000RLDCL\000RLDICL\000RLDICR\000RLDIMI\000RLWIMI\000RLWINM\000"
|
|
"RLWINMo\000RLWNM\000SELECT_CC_F4\000SELECT_CC_F8\000SELECT_CC_I4\000SEL"
|
|
"ECT_CC_I8\000SELECT_CC_VRRC\000SLD\000SLW\000SPILL_CR\000SRAD\000SRADI\000"
|
|
"SRAW\000SRAWI\000SRD\000SRW\000STB\000STB8\000STBU\000STBU8\000STBX\000"
|
|
"STBX8\000STD\000STDCX\000STDU\000STDUX\000STDX\000STDX_32\000STD_32\000"
|
|
"STFD\000STFDU\000STFDX\000STFIWX\000STFS\000STFSU\000STFSX\000STH\000ST"
|
|
"H8\000STHBRX\000STHU\000STHU8\000STHX\000STHX8\000STVEBX\000STVEHX\000S"
|
|
"TVEWX\000STVX\000STVXL\000STW\000STW8\000STWBRX\000STWCX\000STWU\000STW"
|
|
"UX\000STWX\000STWX8\000SUBF\000SUBF8\000SUBFC\000SUBFC8\000SUBFE\000SUB"
|
|
"FE8\000SUBFIC\000SUBFIC8\000SUBFME\000SUBFME8\000SUBFZE\000SUBFZE8\000S"
|
|
"YNC\000TAILB\000TAILB8\000TAILBA\000TAILBA8\000TAILBCTR\000TAILBCTR8\000"
|
|
"TCRETURNai\000TCRETURNai8\000TCRETURNdi\000TCRETURNdi8\000TCRETURNri\000"
|
|
"TCRETURNri8\000TRAP\000UPDATE_VRSAVE\000VADDCUW\000VADDFP\000VADDSBS\000"
|
|
"VADDSHS\000VADDSWS\000VADDUBM\000VADDUBS\000VADDUHM\000VADDUHS\000VADDU"
|
|
"WM\000VADDUWS\000VAND\000VANDC\000VAVGSB\000VAVGSH\000VAVGSW\000VAVGUB\000"
|
|
"VAVGUH\000VAVGUW\000VCFSX\000VCFUX\000VCMPBFP\000VCMPBFPo\000VCMPEQFP\000"
|
|
"VCMPEQFPo\000VCMPEQUB\000VCMPEQUBo\000VCMPEQUH\000VCMPEQUHo\000VCMPEQUW"
|
|
"\000VCMPEQUWo\000VCMPGEFP\000VCMPGEFPo\000VCMPGTFP\000VCMPGTFPo\000VCMP"
|
|
"GTSB\000VCMPGTSBo\000VCMPGTSH\000VCMPGTSHo\000VCMPGTSW\000VCMPGTSWo\000"
|
|
"VCMPGTUB\000VCMPGTUBo\000VCMPGTUH\000VCMPGTUHo\000VCMPGTUW\000VCMPGTUWo"
|
|
"\000VCTSXS\000VCTUXS\000VEXPTEFP\000VLOGEFP\000VMADDFP\000VMAXFP\000VMA"
|
|
"XSB\000VMAXSH\000VMAXSW\000VMAXUB\000VMAXUH\000VMAXUW\000VMHADDSHS\000V"
|
|
"MHRADDSHS\000VMINFP\000VMINSB\000VMINSH\000VMINSW\000VMINUB\000VMINUH\000"
|
|
"VMINUW\000VMLADDUHM\000VMRGHB\000VMRGHH\000VMRGHW\000VMRGLB\000VMRGLH\000"
|
|
"VMRGLW\000VMSUMMBM\000VMSUMSHM\000VMSUMSHS\000VMSUMUBM\000VMSUMUHM\000V"
|
|
"MSUMUHS\000VMULESB\000VMULESH\000VMULEUB\000VMULEUH\000VMULOSB\000VMULO"
|
|
"SH\000VMULOUB\000VMULOUH\000VNMSUBFP\000VNOR\000VOR\000VPERM\000VPKPX\000"
|
|
"VPKSHSS\000VPKSHUS\000VPKSWSS\000VPKSWUS\000VPKUHUM\000VPKUHUS\000VPKUW"
|
|
"UM\000VPKUWUS\000VREFP\000VRFIM\000VRFIN\000VRFIP\000VRFIZ\000VRLB\000V"
|
|
"RLH\000VRLW\000VRSQRTEFP\000VSEL\000VSL\000VSLB\000VSLDOI\000VSLH\000VS"
|
|
"LO\000VSLW\000VSPLTB\000VSPLTH\000VSPLTISB\000VSPLTISH\000VSPLTISW\000V"
|
|
"SPLTW\000VSR\000VSRAB\000VSRAH\000VSRAW\000VSRB\000VSRH\000VSRO\000VSRW"
|
|
"\000VSUBCUW\000VSUBFP\000VSUBSBS\000VSUBSHS\000VSUBSWS\000VSUBUBM\000VS"
|
|
"UBUBS\000VSUBUHM\000VSUBUHS\000VSUBUWM\000VSUBUWS\000VSUM2SWS\000VSUM4S"
|
|
"BS\000VSUM4SHS\000VSUM4UBS\000VSUMSWS\000VUPKHPX\000VUPKHSB\000VUPKHSH\000"
|
|
"VUPKLPX\000VUPKLSB\000VUPKLSH\000VXOR\000V_SET0\000XOR\000XOR8\000XORI\000"
|
|
"XORI8\000XORIS\000XORIS8\000";
|
|
return Strs+InstAsmOffset[Opcode];
|
|
}
|
|
|
|
#endif
|
|
|