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7124 lines
204 KiB
7124 lines
204 KiB
//===- TableGen'erated file -------------------------------------*- C++ -*-===//
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//
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// Assembly Writer Source Fragment
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//
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// Automatically generated file, do not edit!
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//
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//===----------------------------------------------------------------------===//
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/// printInstruction - This method is automatically generated by tablegen
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/// from the instruction set description.
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void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
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static const unsigned OpInfo[] = {
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0U, // PHI
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0U, // INLINEASM
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0U, // DBG_LABEL
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0U, // EH_LABEL
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0U, // GC_LABEL
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0U, // KILL
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0U, // EXTRACT_SUBREG
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0U, // INSERT_SUBREG
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0U, // IMPLICIT_DEF
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0U, // SUBREG_TO_REG
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0U, // COPY_TO_REGCLASS
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1U, // DBG_VALUE
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67108875U, // ADCSSri
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67108875U, // ADCSSrr
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67108875U, // ADCSSrs
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134750225U, // ADCri
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134758417U, // ADCrr
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202375185U, // ADCrs
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135815189U, // ADDSri
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135815189U, // ADDSrr
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202924053U, // ADDSrs
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134750234U, // ADDri
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134758426U, // ADDrr
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202375194U, // ADDrs
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69206046U, // ADJCALLSTACKDOWN
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69206066U, // ADJCALLSTACKUP
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134750276U, // ANDri
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134758468U, // ANDrr
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202375236U, // ANDrs
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271056968U, // ATOMIC_CMP_SWAP_I16
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271581256U, // ATOMIC_CMP_SWAP_I32
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272105544U, // ATOMIC_CMP_SWAP_I8
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272629832U, // ATOMIC_LOAD_ADD_I16
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273154120U, // ATOMIC_LOAD_ADD_I32
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273678408U, // ATOMIC_LOAD_ADD_I8
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274202696U, // ATOMIC_LOAD_AND_I16
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274726984U, // ATOMIC_LOAD_AND_I32
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275251272U, // ATOMIC_LOAD_AND_I8
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275775560U, // ATOMIC_LOAD_NAND_I16
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276299848U, // ATOMIC_LOAD_NAND_I32
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276824136U, // ATOMIC_LOAD_NAND_I8
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277348424U, // ATOMIC_LOAD_OR_I16
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277872712U, // ATOMIC_LOAD_OR_I32
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278397000U, // ATOMIC_LOAD_OR_I8
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278921288U, // ATOMIC_LOAD_SUB_I16
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279445576U, // ATOMIC_LOAD_SUB_I32
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279969864U, // ATOMIC_LOAD_SUB_I8
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280494152U, // ATOMIC_LOAD_XOR_I16
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281018440U, // ATOMIC_LOAD_XOR_I32
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281542728U, // ATOMIC_LOAD_XOR_I8
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282067016U, // ATOMIC_SWAP_I16
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282591304U, // ATOMIC_SWAP_I32
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283115592U, // ATOMIC_SWAP_I8
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69206089U, // B
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135815244U, // BFC
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135815248U, // BFI
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134750292U, // BICri
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134758484U, // BICrr
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202375252U, // BICrs
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337141848U, // BKPT
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402653277U, // BL
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69206113U, // BLX
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69206113U, // BLXr9
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337150054U, // BL_pred
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402653277U, // BLr9
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337150054U, // BLr9_pred
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69206121U, // BRIND
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67108973U, // BR_JTadd
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485007478U, // BR_JTm
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82362495U, // BR_JTr
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69206152U, // BX
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337141912U, // BXJ
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552599708U, // BX_RET
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69206152U, // BXr9
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337141919U, // Bcc
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620290209U, // CDP
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687866021U, // CDP2
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172U, // CLREX
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739795122U, // CLZ
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739795126U, // CMNzri
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739795126U, // CMNzrr
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806903990U, // CMNzrs
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739795130U, // CMPri
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739795130U, // CMPrr
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806903994U, // CMPrs
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739795130U, // CMPzri
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739795130U, // CMPzrr
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806903994U, // CMPzrs
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872415304U, // CONSTPOOL_ENTRY
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939524286U, // CPS
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337141954U, // DBG
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198U, // DMBish
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206U, // DMBishst
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216U, // DMBnsh
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224U, // DMBnshst
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234U, // DMBosh
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242U, // DMBoshst
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252U, // DMBst
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259U, // DSBish
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267U, // DSBishst
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277U, // DSBnsh
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285U, // DSBnshst
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295U, // DSBosh
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303U, // DSBoshst
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313U, // DSBst
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134750528U, // EORri
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134758720U, // EORrr
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202375488U, // EORrs
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755556676U, // FCONSTD
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756080964U, // FCONSTS
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555221321U, // FMSTAT
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334U, // ISBsy
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85983570U, // Int_MemBarrierV6
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351U, // Int_MemBarrierV7
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86507858U, // Int_SyncBarrierV6
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355U, // Int_SyncBarrierV7
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87032167U, // Int_eh_sjlj_setjmp
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221831537U, // LDC2L_OFFSET
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825819505U, // LDC2L_OPTION
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221839729U, // LDC2L_POST
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221831537U, // LDC2L_PRE
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217653617U, // LDC2_OFFSET
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821633393U, // LDC2_OPTION
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217653617U, // LDC2_POST
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217653617U, // LDC2_PRE
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221831542U, // LDCL_OFFSET
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825819510U, // LDCL_OPTION
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221839734U, // LDCL_POST
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221831542U, // LDCL_PRE
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217653622U, // LDC_OFFSET
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821633398U, // LDC_OPTION
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217653622U, // LDC_POST
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217653622U, // LDC_PRE
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1027686778U, // LDM
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1027686778U, // LDM_RET
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806904190U, // LDR
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806904194U, // LDRB
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202924423U, // LDRBT
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202924418U, // LDRB_POST
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202924418U, // LDRB_PRE
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202924429U, // LDRD
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605577613U, // LDRD_POST
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605577613U, // LDRD_PRE
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739795346U, // LDREX
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739795352U, // LDREXB
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135815583U, // LDREXD
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739795366U, // LDREXH
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806904237U, // LDRH
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202924466U, // LDRHT
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202924461U, // LDRH_POST
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202924461U, // LDRH_PRE
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806904248U, // LDRSB
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202924478U, // LDRSBT
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202924472U, // LDRSB_POST
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202924472U, // LDRSB_PRE
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806904261U, // LDRSH
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202924491U, // LDRSHT
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202924485U, // LDRSH_POST
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202924485U, // LDRSH_PRE
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202924498U, // LDRT
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202924414U, // LDR_POST
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202924414U, // LDR_PRE
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806904190U, // LDRcp
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1095238103U, // LEApcrel
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1095762391U, // LEApcrelJT
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620290525U, // MCR
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671105505U, // MCR2
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217637352U, // MCRR
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671105517U, // MCRR2
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827851253U, // MLA
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806904313U, // MLS
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135815677U, // MOVCCi
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135815677U, // MOVCCr
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202924541U, // MOVCCs
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135815681U, // MOVTi16
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761356797U, // MOVi
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739795462U, // MOVi16
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739795453U, // MOVi2pieces
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739795462U, // MOVi32imm
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761266685U, // MOVr
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761266685U, // MOVrx
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827949565U, // MOVs
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739795467U, // MOVsra_flag
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739795467U, // MOVsrl_flag
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620290576U, // MRC
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671105556U, // MRC2
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217637403U, // MRRC
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671105568U, // MRRC2
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337142312U, // MRS
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337142312U, // MRSsys
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359162412U, // MSR
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359244332U, // MSRi
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359686700U, // MSRsys
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359768620U, // MSRsysi
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134758960U, // MUL
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761356852U, // MVNi
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761266740U, // MVNr
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827949620U, // MVNs
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538968632U, // NOP
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134750780U, // ORRri
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134758972U, // ORRrr
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202375740U, // ORRrs
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1165492800U, // PICADD
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1233125952U, // PICLDR
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1233650240U, // PICLDRB
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1234174528U, // PICLDRH
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1234698816U, // PICLDRSB
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1235223104U, // PICLDRSH
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1235747392U, // PICSTR
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1236271680U, // PICSTRB
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1236795968U, // PICSTRH
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806904386U, // PKHBT
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806904392U, // PKHTB
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67109454U, // PLDWi
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471859797U, // PLDWr
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67109467U, // PLDi
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471859809U, // PLDr
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67109478U, // PLIi
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471859820U, // PLIr
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135815793U, // QADD
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135815798U, // QADD16
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135815805U, // QADD8
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135815811U, // QASX
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135815816U, // QDADD
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135815822U, // QDSUB
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135815828U, // QSAX
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135815833U, // QSUB
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135815838U, // QSUB16
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135815845U, // QSUB8
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739795627U, // RBIT
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739795632U, // REV
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739795636U, // REV16
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739795642U, // REVSH
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1008222912U, // RFE
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1008222912U, // RFEW
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135815876U, // RSBSri
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202924740U, // RSBSrs
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134750921U, // RSBri
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202375881U, // RSBrs
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67109581U, // RSCSri
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67109581U, // RSCSrs
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134750931U, // RSCri
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202375891U, // RSCrs
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135815895U, // SADD16
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135815902U, // SADD8
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135815908U, // SASX
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67109609U, // SBCSSri
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67109609U, // SBCSSrr
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67109609U, // SBCSSrs
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134750959U, // SBCri
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134759151U, // SBCrr
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202375919U, // SBCrs
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806904563U, // SBFX
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135815928U, // SEL
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764U, // SETENDBE
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774U, // SETENDLE
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538968848U, // SEV
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135815956U, // SHADD16
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135815964U, // SHADD8
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135815971U, // SHASX
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135815977U, // SHSAX
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135815983U, // SHSUB16
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135815991U, // SHSUB8
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337142590U, // SMC
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806904642U, // SMLABB
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806904649U, // SMLABT
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806904656U, // SMLAD
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806904662U, // SMLADX
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827851613U, // SMLAL
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806904675U, // SMLALBB
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806904683U, // SMLALBT
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806904691U, // SMLALD
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806904698U, // SMLALDX
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806904706U, // SMLALTB
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806904714U, // SMLALTT
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806904722U, // SMLATB
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806904729U, // SMLATT
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806904736U, // SMLAWB
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806904743U, // SMLAWT
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806904750U, // SMLSD
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806904756U, // SMLSDX
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806904763U, // SMLSLD
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806904770U, // SMLSLDX
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806904778U, // SMMLA
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806904784U, // SMMLAR
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806904791U, // SMMLS
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806904797U, // SMMLSR
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135816164U, // SMMUL
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135816170U, // SMMULR
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135816177U, // SMUAD
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135816183U, // SMUADX
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135816190U, // SMULBB
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135816197U, // SMULBT
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827851788U, // SMULL
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135816210U, // SMULTB
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135816217U, // SMULTT
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135816224U, // SMULWB
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135816231U, // SMULWT
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135816238U, // SMUSD
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135816244U, // SMUSDX
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1036010555U, // SRS
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1036534843U, // SRSW
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135816255U, // SSAT16
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806904902U, // SSATasr
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806904902U, // SSATlsl
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135816267U, // SSAX
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135816272U, // SSUB16
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135816279U, // SSUB8
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221832285U, // STC2L_OFFSET
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825820253U, // STC2L_OPTION
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221840477U, // STC2L_POST
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221832285U, // STC2L_PRE
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217654365U, // STC2_OFFSET
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821634141U, // STC2_OPTION
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217654365U, // STC2_POST
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217654365U, // STC2_PRE
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221832290U, // STCL_OFFSET
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825820258U, // STCL_OPTION
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221840482U, // STCL_POST
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221832290U, // STCL_PRE
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217654370U, // STC_OFFSET
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821634146U, // STC_OPTION
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217654370U, // STC_POST
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|
217654370U, // STC_PRE
|
|
1027687526U, // STM
|
|
806904938U, // STR
|
|
806904942U, // STRB
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|
202900595U, // STRBT
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|
202900590U, // STRB_POST
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|
202900590U, // STRB_PRE
|
|
202925177U, // STRD
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|
605553785U, // STRD_POST
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|
605553785U, // STRD_PRE
|
|
135816318U, // STREX
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|
135816324U, // STREXB
|
|
806904971U, // STREXD
|
|
135816338U, // STREXH
|
|
806904985U, // STRH
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|
202900638U, // STRHT
|
|
202900633U, // STRH_POST
|
|
202900633U, // STRH_PRE
|
|
202900644U, // STRT
|
|
202900586U, // STR_POST
|
|
202900586U, // STR_PRE
|
|
135816361U, // SUBSri
|
|
135816361U, // SUBSrr
|
|
202925225U, // SUBSrs
|
|
134751406U, // SUBri
|
|
134759598U, // SUBrr
|
|
202376366U, // SUBrs
|
|
337142962U, // SVC
|
|
135816374U, // SWP
|
|
135816378U, // SWPB
|
|
135816383U, // SXTAB16rr
|
|
806905023U, // SXTAB16rr_rot
|
|
135816391U, // SXTABrr
|
|
806905031U, // SXTABrr_rot
|
|
135816397U, // SXTAHrr
|
|
806905037U, // SXTAHrr_rot
|
|
739796179U, // SXTB16r
|
|
135816403U, // SXTB16r_rot
|
|
739796186U, // SXTBr
|
|
135816410U, // SXTBr_rot
|
|
739796191U, // SXTHr
|
|
135816415U, // SXTHr_rot
|
|
739796196U, // TEQri
|
|
739796196U, // TEQrr
|
|
806905060U, // TEQrs
|
|
1256U, // TPsoft
|
|
538969339U, // TRAP
|
|
739796224U, // TSTri
|
|
739796224U, // TSTrr
|
|
806905088U, // TSTrs
|
|
135816452U, // UADD16
|
|
135816459U, // UADD8
|
|
135816465U, // UASX
|
|
806905110U, // UBFX
|
|
135816475U, // UHADD16
|
|
135816483U, // UHADD8
|
|
135816490U, // UHASX
|
|
135816496U, // UHSAX
|
|
135816502U, // UHSUB16
|
|
135816510U, // UHSUB8
|
|
806905157U, // UMAAL
|
|
827852107U, // UMLAL
|
|
827852113U, // UMULL
|
|
135816535U, // UQADD16
|
|
135816543U, // UQADD8
|
|
135816550U, // UQASX
|
|
135816556U, // UQSAX
|
|
135816562U, // UQSUB16
|
|
135816570U, // UQSUB8
|
|
135816577U, // USAD8
|
|
806905223U, // USADA8
|
|
135816590U, // USAT16
|
|
806905237U, // USATasr
|
|
806905237U, // USATlsl
|
|
135816602U, // USAX
|
|
135816607U, // USUB16
|
|
135816614U, // USUB8
|
|
135816620U, // UXTAB16rr
|
|
806905260U, // UXTAB16rr_rot
|
|
135816628U, // UXTABrr
|
|
806905268U, // UXTABrr_rot
|
|
135816634U, // UXTAHrr
|
|
806905274U, // UXTAHrr_rot
|
|
739796416U, // UXTB16r
|
|
135816640U, // UXTB16r_rot
|
|
739796423U, // UXTBr
|
|
135816647U, // UXTBr_rot
|
|
739796428U, // UXTHr
|
|
135816652U, // UXTHr_rot
|
|
835732945U, // VABALsv2i64
|
|
836257233U, // VABALsv4i32
|
|
836781521U, // VABALsv8i16
|
|
837305809U, // VABALuv2i64
|
|
837830097U, // VABALuv4i32
|
|
838354385U, // VABALuv8i16
|
|
836781527U, // VABAsv16i8
|
|
835732951U, // VABAsv2i32
|
|
836257239U, // VABAsv4i16
|
|
835732951U, // VABAsv4i32
|
|
836257239U, // VABAsv8i16
|
|
836781527U, // VABAsv8i8
|
|
838354391U, // VABAuv16i8
|
|
837305815U, // VABAuv2i32
|
|
837830103U, // VABAuv4i16
|
|
837305815U, // VABAuv4i32
|
|
837830103U, // VABAuv8i16
|
|
838354391U, // VABAuv8i8
|
|
164627932U, // VABDLsv2i64
|
|
165152220U, // VABDLsv4i32
|
|
165676508U, // VABDLsv8i16
|
|
166200796U, // VABDLuv2i64
|
|
166725084U, // VABDLuv4i32
|
|
167249372U, // VABDLuv8i16
|
|
152102370U, // VABDfd
|
|
152102370U, // VABDfq
|
|
165676514U, // VABDsv16i8
|
|
164627938U, // VABDsv2i32
|
|
165152226U, // VABDsv4i16
|
|
164627938U, // VABDsv4i32
|
|
165152226U, // VABDsv8i16
|
|
165676514U, // VABDsv8i8
|
|
167249378U, // VABDuv16i8
|
|
166200802U, // VABDuv2i32
|
|
166725090U, // VABDuv4i16
|
|
166200802U, // VABDuv4i32
|
|
166725090U, // VABDuv8i16
|
|
167249378U, // VABDuv8i8
|
|
755557863U, // VABSD
|
|
756082151U, // VABSS
|
|
756082151U, // VABSfd
|
|
756082151U, // VABSfd_sfp
|
|
756082151U, // VABSfq
|
|
769656295U, // VABSv16i8
|
|
768607719U, // VABSv2i32
|
|
769132007U, // VABSv4i16
|
|
768607719U, // VABSv4i32
|
|
769132007U, // VABSv8i16
|
|
769656295U, // VABSv8i8
|
|
152102380U, // VACGEd
|
|
152102380U, // VACGEq
|
|
152102386U, // VACGTd
|
|
152102386U, // VACGTq
|
|
151578104U, // VADDD
|
|
167773693U, // VADDHNv2i32
|
|
168297981U, // VADDHNv4i16
|
|
168822269U, // VADDHNv8i8
|
|
164627972U, // VADDLsv2i64
|
|
165152260U, // VADDLsv4i32
|
|
165676548U, // VADDLsv8i16
|
|
166200836U, // VADDLuv2i64
|
|
166725124U, // VADDLuv4i32
|
|
167249412U, // VADDLuv8i16
|
|
152102392U, // VADDS
|
|
164627978U, // VADDWsv2i64
|
|
165152266U, // VADDWsv4i32
|
|
165676554U, // VADDWsv8i16
|
|
166200842U, // VADDWuv2i64
|
|
166725130U, // VADDWuv4i32
|
|
167249418U, // VADDWuv8i16
|
|
152102392U, // VADDfd
|
|
152102392U, // VADDfd_sfp
|
|
152102392U, // VADDfq
|
|
169346552U, // VADDv16i8
|
|
167773688U, // VADDv1i64
|
|
168297976U, // VADDv2i32
|
|
167773688U, // VADDv2i64
|
|
168822264U, // VADDv4i16
|
|
168297976U, // VADDv4i32
|
|
168822264U, // VADDv8i16
|
|
169346552U, // VADDv8i8
|
|
135816720U, // VANDd
|
|
135816720U, // VANDq
|
|
135816725U, // VBICd
|
|
135816725U, // VBICq
|
|
806905370U, // VBIFd
|
|
806905370U, // VBIFq
|
|
806905375U, // VBITd
|
|
806905375U, // VBITq
|
|
806905380U, // VBSLd
|
|
806905380U, // VBSLq
|
|
152102441U, // VCEQfd
|
|
152102441U, // VCEQfq
|
|
169346601U, // VCEQv16i8
|
|
168298025U, // VCEQv2i32
|
|
168822313U, // VCEQv4i16
|
|
168298025U, // VCEQv4i32
|
|
168822313U, // VCEQv8i16
|
|
169346601U, // VCEQv8i8
|
|
773326377U, // VCEQzv16i8
|
|
756082217U, // VCEQzv2f32
|
|
772277801U, // VCEQzv2i32
|
|
756082217U, // VCEQzv4f32
|
|
772802089U, // VCEQzv4i16
|
|
772277801U, // VCEQzv4i32
|
|
772802089U, // VCEQzv8i16
|
|
773326377U, // VCEQzv8i8
|
|
152102446U, // VCGEfd
|
|
152102446U, // VCGEfq
|
|
165676590U, // VCGEsv16i8
|
|
164628014U, // VCGEsv2i32
|
|
165152302U, // VCGEsv4i16
|
|
164628014U, // VCGEsv4i32
|
|
165152302U, // VCGEsv8i16
|
|
165676590U, // VCGEsv8i8
|
|
167249454U, // VCGEuv16i8
|
|
166200878U, // VCGEuv2i32
|
|
166725166U, // VCGEuv4i16
|
|
166200878U, // VCGEuv4i32
|
|
166725166U, // VCGEuv8i16
|
|
167249454U, // VCGEuv8i8
|
|
769656366U, // VCGEzv16i8
|
|
756082222U, // VCGEzv2f32
|
|
768607790U, // VCGEzv2i32
|
|
756082222U, // VCGEzv4f32
|
|
769132078U, // VCGEzv4i16
|
|
768607790U, // VCGEzv4i32
|
|
769132078U, // VCGEzv8i16
|
|
769656366U, // VCGEzv8i8
|
|
152102451U, // VCGTfd
|
|
152102451U, // VCGTfq
|
|
165676595U, // VCGTsv16i8
|
|
164628019U, // VCGTsv2i32
|
|
165152307U, // VCGTsv4i16
|
|
164628019U, // VCGTsv4i32
|
|
165152307U, // VCGTsv8i16
|
|
165676595U, // VCGTsv8i8
|
|
167249459U, // VCGTuv16i8
|
|
166200883U, // VCGTuv2i32
|
|
166725171U, // VCGTuv4i16
|
|
166200883U, // VCGTuv4i32
|
|
166725171U, // VCGTuv8i16
|
|
167249459U, // VCGTuv8i8
|
|
769656371U, // VCGTzv16i8
|
|
756082227U, // VCGTzv2f32
|
|
768607795U, // VCGTzv2i32
|
|
756082227U, // VCGTzv4f32
|
|
769132083U, // VCGTzv4i16
|
|
768607795U, // VCGTzv4i32
|
|
769132083U, // VCGTzv8i16
|
|
769656371U, // VCGTzv8i8
|
|
769656376U, // VCLEzv16i8
|
|
756082232U, // VCLEzv2f32
|
|
768607800U, // VCLEzv2i32
|
|
756082232U, // VCLEzv4f32
|
|
769132088U, // VCLEzv4i16
|
|
768607800U, // VCLEzv4i32
|
|
769132088U, // VCLEzv8i16
|
|
769656376U, // VCLEzv8i8
|
|
769656381U, // VCLSv16i8
|
|
768607805U, // VCLSv2i32
|
|
769132093U, // VCLSv4i16
|
|
768607805U, // VCLSv4i32
|
|
769132093U, // VCLSv8i16
|
|
769656381U, // VCLSv8i8
|
|
769656386U, // VCLTzv16i8
|
|
756082242U, // VCLTzv2f32
|
|
768607810U, // VCLTzv2i32
|
|
756082242U, // VCLTzv4f32
|
|
769132098U, // VCLTzv4i16
|
|
768607810U, // VCLTzv4i32
|
|
769132098U, // VCLTzv8i16
|
|
769656386U, // VCLTzv8i8
|
|
773326407U, // VCLZv16i8
|
|
772277831U, // VCLZv2i32
|
|
772802119U, // VCLZv4i16
|
|
772277831U, // VCLZv4i32
|
|
772802119U, // VCLZv8i16
|
|
773326407U, // VCLZv8i8
|
|
755557964U, // VCMPD
|
|
755557969U, // VCMPED
|
|
756082257U, // VCMPES
|
|
352962129U, // VCMPEZD
|
|
353486417U, // VCMPEZS
|
|
756082252U, // VCMPS
|
|
352962124U, // VCMPZD
|
|
353486412U, // VCMPZS
|
|
773875287U, // VCNTd
|
|
773875287U, // VCNTq
|
|
774375004U, // VCVTBHS
|
|
774899292U, // VCVTBSH
|
|
775423586U, // VCVTDS
|
|
775947874U, // VCVTSD
|
|
774375015U, // VCVTTHS
|
|
774899303U, // VCVTTSH
|
|
776595042U, // VCVTf2sd
|
|
776595042U, // VCVTf2sd_sfp
|
|
776595042U, // VCVTf2sq
|
|
777119330U, // VCVTf2ud
|
|
777119330U, // VCVTf2ud_sfp
|
|
777119330U, // VCVTf2uq
|
|
172549730U, // VCVTf2xsd
|
|
172549730U, // VCVTf2xsq
|
|
173074018U, // VCVTf2xud
|
|
173074018U, // VCVTf2xuq
|
|
777643618U, // VCVTs2fd
|
|
777643618U, // VCVTs2fd_sfp
|
|
777643618U, // VCVTs2fq
|
|
778167906U, // VCVTu2fd
|
|
778167906U, // VCVTu2fd_sfp
|
|
778167906U, // VCVTu2fq
|
|
173598306U, // VCVTxs2fd
|
|
173598306U, // VCVTxs2fq
|
|
174122594U, // VCVTxu2fd
|
|
174122594U, // VCVTxu2fq
|
|
151578221U, // VDIVD
|
|
152102509U, // VDIVS
|
|
778593906U, // VDUP16d
|
|
778593906U, // VDUP16q
|
|
779118194U, // VDUP32d
|
|
779118194U, // VDUP32q
|
|
773875314U, // VDUP8d
|
|
773875314U, // VDUP8q
|
|
174614130U, // VDUPLN16d
|
|
174614130U, // VDUPLN16q
|
|
175138418U, // VDUPLN32d
|
|
175138418U, // VDUPLN32q
|
|
169895538U, // VDUPLN8d
|
|
169895538U, // VDUPLN8q
|
|
175138418U, // VDUPLNfd
|
|
175138418U, // VDUPLNfq
|
|
779118194U, // VDUPfd
|
|
779118194U, // VDUPfdf
|
|
779118194U, // VDUPfq
|
|
779118194U, // VDUPfqf
|
|
135816823U, // VEORd
|
|
135816823U, // VEORq
|
|
845702780U, // VEXTd16
|
|
846227068U, // VEXTd32
|
|
840984188U, // VEXTd8
|
|
846227068U, // VEXTdf
|
|
845702780U, // VEXTq16
|
|
846227068U, // VEXTq32
|
|
840984188U, // VEXTq8
|
|
846227068U, // VEXTqf
|
|
175137092U, // VGETLNi32
|
|
165151044U, // VGETLNs16
|
|
165675332U, // VGETLNs8
|
|
166723908U, // VGETLNu16
|
|
167248196U, // VGETLNu8
|
|
165676673U, // VHADDsv16i8
|
|
164628097U, // VHADDsv2i32
|
|
165152385U, // VHADDsv4i16
|
|
164628097U, // VHADDsv4i32
|
|
165152385U, // VHADDsv8i16
|
|
165676673U, // VHADDsv8i8
|
|
167249537U, // VHADDuv16i8
|
|
166200961U, // VHADDuv2i32
|
|
166725249U, // VHADDuv4i16
|
|
166200961U, // VHADDuv4i32
|
|
166725249U, // VHADDuv8i16
|
|
167249537U, // VHADDuv8i8
|
|
165676679U, // VHSUBsv16i8
|
|
164628103U, // VHSUBsv2i32
|
|
165152391U, // VHSUBsv4i16
|
|
164628103U, // VHSUBsv4i32
|
|
165152391U, // VHSUBsv8i16
|
|
165676679U, // VHSUBsv8i8
|
|
167249543U, // VHSUBuv16i8
|
|
166200967U, // VHSUBuv2i32
|
|
166725255U, // VHSUBuv4i16
|
|
166200967U, // VHSUBuv4i32
|
|
166725255U, // VHSUBuv8i16
|
|
167249543U, // VHSUBuv8i8
|
|
242771597U, // VLD1d16
|
|
1316513421U, // VLD1d16Q
|
|
1383622285U, // VLD1d16T
|
|
243295885U, // VLD1d32
|
|
1317037709U, // VLD1d32Q
|
|
1384146573U, // VLD1d32T
|
|
243820173U, // VLD1d64
|
|
244344461U, // VLD1d8
|
|
1318086285U, // VLD1d8Q
|
|
1385195149U, // VLD1d8T
|
|
243295885U, // VLD1df
|
|
241829517U, // VLD1q16
|
|
242353805U, // VLD1q32
|
|
244975245U, // VLD1q64
|
|
237110925U, // VLD1q8
|
|
242353805U, // VLD1qf
|
|
1450731154U, // VLD2LNd16
|
|
1451255442U, // VLD2LNd32
|
|
1452304018U, // VLD2LNd8
|
|
1450731154U, // VLD2LNq16a
|
|
1450731154U, // VLD2LNq16b
|
|
1451255442U, // VLD2LNq32a
|
|
1451255442U, // VLD2LNq32b
|
|
645424786U, // VLD2d16
|
|
645424786U, // VLD2d16D
|
|
645949074U, // VLD2d32
|
|
645949074U, // VLD2d32D
|
|
646473357U, // VLD2d64
|
|
646997650U, // VLD2d8
|
|
646997650U, // VLD2d8D
|
|
1316513426U, // VLD2q16
|
|
1317037714U, // VLD2q32
|
|
1318086290U, // VLD2q8
|
|
1517840023U, // VLD3LNd16
|
|
1518364311U, // VLD3LNd32
|
|
1519412887U, // VLD3LNd8
|
|
1517840023U, // VLD3LNq16a
|
|
1517840023U, // VLD3LNq16b
|
|
1518364311U, // VLD3LNq32a
|
|
1518364311U, // VLD3LNq32b
|
|
1383622295U, // VLD3d16
|
|
1384146583U, // VLD3d32
|
|
1384670861U, // VLD3d64
|
|
1385195159U, // VLD3d8
|
|
1316513431U, // VLD3q16a
|
|
1316513431U, // VLD3q16b
|
|
1317037719U, // VLD3q32a
|
|
1317037719U, // VLD3q32b
|
|
1318086295U, // VLD3q8a
|
|
1318086295U, // VLD3q8b
|
|
1584948892U, // VLD4LNd16
|
|
1585473180U, // VLD4LNd32
|
|
1586521756U, // VLD4LNd8
|
|
1584948892U, // VLD4LNq16a
|
|
1584948892U, // VLD4LNq16b
|
|
1585473180U, // VLD4LNq32a
|
|
1585473180U, // VLD4LNq32b
|
|
1316513436U, // VLD4d16
|
|
1317037724U, // VLD4d32
|
|
1317561997U, // VLD4d64
|
|
1318086300U, // VLD4d8
|
|
1450731164U, // VLD4q16a
|
|
1450731164U, // VLD4q16b
|
|
1451255452U, // VLD4q32a
|
|
1451255452U, // VLD4q32b
|
|
1452304028U, // VLD4q8a
|
|
1452304028U, // VLD4q8b
|
|
1610614433U, // VLDMD
|
|
1610614433U, // VLDMS
|
|
177759910U, // VLDRD
|
|
135931563U, // VLDRQ
|
|
175138470U, // VLDRS
|
|
152102578U, // VMAXfd
|
|
152102578U, // VMAXfd_sfp
|
|
152102578U, // VMAXfq
|
|
165676722U, // VMAXsv16i8
|
|
164628146U, // VMAXsv2i32
|
|
165152434U, // VMAXsv4i16
|
|
164628146U, // VMAXsv4i32
|
|
165152434U, // VMAXsv8i16
|
|
165676722U, // VMAXsv8i8
|
|
167249586U, // VMAXuv16i8
|
|
166201010U, // VMAXuv2i32
|
|
166725298U, // VMAXuv4i16
|
|
166201010U, // VMAXuv4i32
|
|
166725298U, // VMAXuv8i16
|
|
167249586U, // VMAXuv8i8
|
|
152102583U, // VMINfd
|
|
152102583U, // VMINfd_sfp
|
|
152102583U, // VMINfq
|
|
165676727U, // VMINsv16i8
|
|
164628151U, // VMINsv2i32
|
|
165152439U, // VMINsv4i16
|
|
164628151U, // VMINsv4i32
|
|
165152439U, // VMINsv8i16
|
|
165676727U, // VMINsv8i8
|
|
167249591U, // VMINuv16i8
|
|
166201015U, // VMINuv2i32
|
|
166725303U, // VMINuv4i16
|
|
166201015U, // VMINuv4i32
|
|
166725303U, // VMINuv8i16
|
|
167249591U, // VMINuv8i8
|
|
822666940U, // VMLAD
|
|
231753409U, // VMLALslsv2i32
|
|
232277697U, // VMLALslsv4i16
|
|
233326273U, // VMLALsluv2i32
|
|
233850561U, // VMLALsluv4i16
|
|
835733185U, // VMLALsv2i64
|
|
836257473U, // VMLALsv4i32
|
|
836781761U, // VMLALsv8i16
|
|
837306049U, // VMLALuv2i64
|
|
837830337U, // VMLALuv4i32
|
|
838354625U, // VMLALuv8i16
|
|
823191228U, // VMLAS
|
|
823191228U, // VMLAfd
|
|
823191228U, // VMLAfq
|
|
219211452U, // VMLAslfd
|
|
219211452U, // VMLAslfq
|
|
235423420U, // VMLAslv2i32
|
|
235947708U, // VMLAslv4i16
|
|
235423420U, // VMLAslv4i32
|
|
235947708U, // VMLAslv8i16
|
|
840451772U, // VMLAv16i8
|
|
839403196U, // VMLAv2i32
|
|
839927484U, // VMLAv4i16
|
|
839403196U, // VMLAv4i32
|
|
839927484U, // VMLAv8i16
|
|
840451772U, // VMLAv8i8
|
|
822666951U, // VMLSD
|
|
231753420U, // VMLSLslsv2i32
|
|
232277708U, // VMLSLslsv4i16
|
|
233326284U, // VMLSLsluv2i32
|
|
233850572U, // VMLSLsluv4i16
|
|
835733196U, // VMLSLsv2i64
|
|
836257484U, // VMLSLsv4i32
|
|
836781772U, // VMLSLsv8i16
|
|
837306060U, // VMLSLuv2i64
|
|
837830348U, // VMLSLuv4i32
|
|
838354636U, // VMLSLuv8i16
|
|
823191239U, // VMLSS
|
|
823191239U, // VMLSfd
|
|
823191239U, // VMLSfq
|
|
219211463U, // VMLSslfd
|
|
219211463U, // VMLSslfq
|
|
235423431U, // VMLSslv2i32
|
|
235947719U, // VMLSslv4i16
|
|
235423431U, // VMLSslv4i32
|
|
235947719U, // VMLSslv8i16
|
|
840451783U, // VMLSv16i8
|
|
839403207U, // VMLSv2i32
|
|
839927495U, // VMLSv4i16
|
|
839403207U, // VMLSv4i32
|
|
839927495U, // VMLSv8i16
|
|
840451783U, // VMLSv8i8
|
|
755556676U, // VMOVD
|
|
135815492U, // VMOVDRR
|
|
151576900U, // VMOVDcc
|
|
739795268U, // VMOVDneon
|
|
768607954U, // VMOVLsv2i64
|
|
769132242U, // VMOVLsv4i32
|
|
769656530U, // VMOVLsv8i16
|
|
770180818U, // VMOVLuv2i64
|
|
770705106U, // VMOVLuv4i32
|
|
771229394U, // VMOVLuv8i16
|
|
771753688U, // VMOVNv2i32
|
|
772277976U, // VMOVNv4i16
|
|
772802264U, // VMOVNv8i8
|
|
739795268U, // VMOVQ
|
|
135815492U, // VMOVRRD
|
|
806904132U, // VMOVRRS
|
|
739795268U, // VMOVRS
|
|
756080964U, // VMOVS
|
|
739795268U, // VMOVSR
|
|
806904132U, // VMOVSRR
|
|
152101188U, // VMOVScc
|
|
773472580U, // VMOVv16i8
|
|
771907908U, // VMOVv1i64
|
|
772440388U, // VMOVv2i32
|
|
771907908U, // VMOVv2i64
|
|
772972868U, // VMOVv4i16
|
|
772440388U, // VMOVv4i32
|
|
772972868U, // VMOVv8i16
|
|
773472580U, // VMOVv8i8
|
|
337142089U, // VMRS
|
|
379586270U, // VMSR
|
|
151578339U, // VMULD
|
|
178783976U, // VMULLp
|
|
835716840U, // VMULLslsv2i32
|
|
836241128U, // VMULLslsv4i16
|
|
837289704U, // VMULLsluv2i32
|
|
837813992U, // VMULLsluv4i16
|
|
164628200U, // VMULLsv2i64
|
|
165152488U, // VMULLsv4i32
|
|
165676776U, // VMULLsv8i16
|
|
166201064U, // VMULLuv2i64
|
|
166725352U, // VMULLuv4i32
|
|
167249640U, // VMULLuv8i16
|
|
152102627U, // VMULS
|
|
152102627U, // VMULfd
|
|
152102627U, // VMULfd_sfp
|
|
152102627U, // VMULfq
|
|
178783971U, // VMULpd
|
|
178783971U, // VMULpq
|
|
823191267U, // VMULslfd
|
|
823191267U, // VMULslfq
|
|
839386851U, // VMULslv2i32
|
|
839911139U, // VMULslv4i16
|
|
839386851U, // VMULslv4i32
|
|
839911139U, // VMULslv8i16
|
|
169346787U, // VMULv16i8
|
|
168298211U, // VMULv2i32
|
|
168822499U, // VMULv4i16
|
|
168298211U, // VMULv4i32
|
|
168822499U, // VMULv8i16
|
|
169346787U, // VMULv8i8
|
|
739796718U, // VMVNd
|
|
739796718U, // VMVNq
|
|
755558131U, // VNEGD
|
|
151578355U, // VNEGDcc
|
|
756082419U, // VNEGS
|
|
152102643U, // VNEGScc
|
|
756082419U, // VNEGf32q
|
|
756082419U, // VNEGfd
|
|
756082419U, // VNEGfd_sfp
|
|
769132275U, // VNEGs16d
|
|
769132275U, // VNEGs16q
|
|
768607987U, // VNEGs32d
|
|
768607987U, // VNEGs32q
|
|
769656563U, // VNEGs8d
|
|
769656563U, // VNEGs8q
|
|
822667000U, // VNMLAD
|
|
823191288U, // VNMLAS
|
|
822667006U, // VNMLSD
|
|
823191294U, // VNMLSS
|
|
151578372U, // VNMULD
|
|
152102660U, // VNMULS
|
|
135816970U, // VORNd
|
|
135816970U, // VORNq
|
|
135816975U, // VORRd
|
|
135816975U, // VORRq
|
|
165693204U, // VPADALsv16i8
|
|
164644628U, // VPADALsv2i32
|
|
165168916U, // VPADALsv4i16
|
|
164644628U, // VPADALsv4i32
|
|
165168916U, // VPADALsv8i16
|
|
165693204U, // VPADALsv8i8
|
|
167266068U, // VPADALuv16i8
|
|
166217492U, // VPADALuv2i32
|
|
166741780U, // VPADALuv4i16
|
|
166217492U, // VPADALuv4i32
|
|
166741780U, // VPADALuv8i16
|
|
167266068U, // VPADALuv8i8
|
|
769656603U, // VPADDLsv16i8
|
|
768608027U, // VPADDLsv2i32
|
|
769132315U, // VPADDLsv4i16
|
|
768608027U, // VPADDLsv4i32
|
|
769132315U, // VPADDLsv8i16
|
|
769656603U, // VPADDLsv8i8
|
|
771229467U, // VPADDLuv16i8
|
|
770180891U, // VPADDLuv2i32
|
|
770705179U, // VPADDLuv4i16
|
|
770180891U, // VPADDLuv4i32
|
|
770705179U, // VPADDLuv8i16
|
|
771229467U, // VPADDLuv8i8
|
|
152102690U, // VPADDf
|
|
168822562U, // VPADDi16
|
|
168298274U, // VPADDi32
|
|
169346850U, // VPADDi8
|
|
152102696U, // VPMAXf
|
|
165152552U, // VPMAXs16
|
|
164628264U, // VPMAXs32
|
|
165676840U, // VPMAXs8
|
|
166725416U, // VPMAXu16
|
|
166201128U, // VPMAXu32
|
|
167249704U, // VPMAXu8
|
|
152102702U, // VPMINf
|
|
165152558U, // VPMINs16
|
|
164628270U, // VPMINs32
|
|
165676846U, // VPMINs8
|
|
166725422U, // VPMINu16
|
|
166201134U, // VPMINu32
|
|
167249710U, // VPMINu8
|
|
769656628U, // VQABSv16i8
|
|
768608052U, // VQABSv2i32
|
|
769132340U, // VQABSv4i16
|
|
768608052U, // VQABSv4i32
|
|
769132340U, // VQABSv8i16
|
|
769656628U, // VQABSv8i8
|
|
165676858U, // VQADDsv16i8
|
|
179308346U, // VQADDsv1i64
|
|
164628282U, // VQADDsv2i32
|
|
179308346U, // VQADDsv2i64
|
|
165152570U, // VQADDsv4i16
|
|
164628282U, // VQADDsv4i32
|
|
165152570U, // VQADDsv8i16
|
|
165676858U, // VQADDsv8i8
|
|
167249722U, // VQADDuv16i8
|
|
179832634U, // VQADDuv1i64
|
|
166201146U, // VQADDuv2i32
|
|
179832634U, // VQADDuv2i64
|
|
166725434U, // VQADDuv4i16
|
|
166201146U, // VQADDuv4i32
|
|
166725434U, // VQADDuv8i16
|
|
167249722U, // VQADDuv8i8
|
|
231753536U, // VQDMLALslv2i32
|
|
232277824U, // VQDMLALslv4i16
|
|
835733312U, // VQDMLALv2i64
|
|
836257600U, // VQDMLALv4i32
|
|
231753544U, // VQDMLSLslv2i32
|
|
232277832U, // VQDMLSLslv4i16
|
|
835733320U, // VQDMLSLv2i64
|
|
836257608U, // VQDMLSLv4i32
|
|
835716944U, // VQDMULHslv2i32
|
|
836241232U, // VQDMULHslv4i16
|
|
835716944U, // VQDMULHslv4i32
|
|
836241232U, // VQDMULHslv8i16
|
|
164628304U, // VQDMULHv2i32
|
|
165152592U, // VQDMULHv4i16
|
|
164628304U, // VQDMULHv4i32
|
|
165152592U, // VQDMULHv8i16
|
|
835716952U, // VQDMULLslv2i32
|
|
836241240U, // VQDMULLslv4i16
|
|
164628312U, // VQDMULLv2i64
|
|
165152600U, // VQDMULLv4i32
|
|
783288160U, // VQMOVNsuv2i32
|
|
768608096U, // VQMOVNsuv4i16
|
|
769132384U, // VQMOVNsuv8i8
|
|
783288168U, // VQMOVNsv2i32
|
|
768608104U, // VQMOVNsv4i16
|
|
769132392U, // VQMOVNsv8i8
|
|
783812456U, // VQMOVNuv2i32
|
|
770180968U, // VQMOVNuv4i16
|
|
770705256U, // VQMOVNuv8i8
|
|
769656687U, // VQNEGv16i8
|
|
768608111U, // VQNEGv2i32
|
|
769132399U, // VQNEGv4i16
|
|
768608111U, // VQNEGv4i32
|
|
769132399U, // VQNEGv8i16
|
|
769656687U, // VQNEGv8i8
|
|
835716981U, // VQRDMULHslv2i32
|
|
836241269U, // VQRDMULHslv4i16
|
|
835716981U, // VQRDMULHslv4i32
|
|
836241269U, // VQRDMULHslv8i16
|
|
164628341U, // VQRDMULHv2i32
|
|
165152629U, // VQRDMULHv4i16
|
|
164628341U, // VQRDMULHv4i32
|
|
165152629U, // VQRDMULHv8i16
|
|
165676926U, // VQRSHLsv16i8
|
|
179308414U, // VQRSHLsv1i64
|
|
164628350U, // VQRSHLsv2i32
|
|
179308414U, // VQRSHLsv2i64
|
|
165152638U, // VQRSHLsv4i16
|
|
164628350U, // VQRSHLsv4i32
|
|
165152638U, // VQRSHLsv8i16
|
|
165676926U, // VQRSHLsv8i8
|
|
167249790U, // VQRSHLuv16i8
|
|
179832702U, // VQRSHLuv1i64
|
|
166201214U, // VQRSHLuv2i32
|
|
179832702U, // VQRSHLuv2i64
|
|
166725502U, // VQRSHLuv4i16
|
|
166201214U, // VQRSHLuv4i32
|
|
166725502U, // VQRSHLuv8i16
|
|
167249790U, // VQRSHLuv8i8
|
|
179308421U, // VQRSHRNsv2i32
|
|
164628357U, // VQRSHRNsv4i16
|
|
165152645U, // VQRSHRNsv8i8
|
|
179832709U, // VQRSHRNuv2i32
|
|
166201221U, // VQRSHRNuv4i16
|
|
166725509U, // VQRSHRNuv8i8
|
|
179308429U, // VQRSHRUNv2i32
|
|
164628365U, // VQRSHRUNv4i16
|
|
165152653U, // VQRSHRUNv8i8
|
|
165676950U, // VQSHLsiv16i8
|
|
179308438U, // VQSHLsiv1i64
|
|
164628374U, // VQSHLsiv2i32
|
|
179308438U, // VQSHLsiv2i64
|
|
165152662U, // VQSHLsiv4i16
|
|
164628374U, // VQSHLsiv4i32
|
|
165152662U, // VQSHLsiv8i16
|
|
165676950U, // VQSHLsiv8i8
|
|
165676956U, // VQSHLsuv16i8
|
|
179308444U, // VQSHLsuv1i64
|
|
164628380U, // VQSHLsuv2i32
|
|
179308444U, // VQSHLsuv2i64
|
|
165152668U, // VQSHLsuv4i16
|
|
164628380U, // VQSHLsuv4i32
|
|
165152668U, // VQSHLsuv8i16
|
|
165676956U, // VQSHLsuv8i8
|
|
165676950U, // VQSHLsv16i8
|
|
179308438U, // VQSHLsv1i64
|
|
164628374U, // VQSHLsv2i32
|
|
179308438U, // VQSHLsv2i64
|
|
165152662U, // VQSHLsv4i16
|
|
164628374U, // VQSHLsv4i32
|
|
165152662U, // VQSHLsv8i16
|
|
165676950U, // VQSHLsv8i8
|
|
167249814U, // VQSHLuiv16i8
|
|
179832726U, // VQSHLuiv1i64
|
|
166201238U, // VQSHLuiv2i32
|
|
179832726U, // VQSHLuiv2i64
|
|
166725526U, // VQSHLuiv4i16
|
|
166201238U, // VQSHLuiv4i32
|
|
166725526U, // VQSHLuiv8i16
|
|
167249814U, // VQSHLuiv8i8
|
|
167249814U, // VQSHLuv16i8
|
|
179832726U, // VQSHLuv1i64
|
|
166201238U, // VQSHLuv2i32
|
|
179832726U, // VQSHLuv2i64
|
|
166725526U, // VQSHLuv4i16
|
|
166201238U, // VQSHLuv4i32
|
|
166725526U, // VQSHLuv8i16
|
|
167249814U, // VQSHLuv8i8
|
|
179308451U, // VQSHRNsv2i32
|
|
164628387U, // VQSHRNsv4i16
|
|
165152675U, // VQSHRNsv8i8
|
|
179832739U, // VQSHRNuv2i32
|
|
166201251U, // VQSHRNuv4i16
|
|
166725539U, // VQSHRNuv8i8
|
|
179308458U, // VQSHRUNv2i32
|
|
164628394U, // VQSHRUNv4i16
|
|
165152682U, // VQSHRUNv8i8
|
|
165676978U, // VQSUBsv16i8
|
|
179308466U, // VQSUBsv1i64
|
|
164628402U, // VQSUBsv2i32
|
|
179308466U, // VQSUBsv2i64
|
|
165152690U, // VQSUBsv4i16
|
|
164628402U, // VQSUBsv4i32
|
|
165152690U, // VQSUBsv8i16
|
|
165676978U, // VQSUBsv8i8
|
|
167249842U, // VQSUBuv16i8
|
|
179832754U, // VQSUBuv1i64
|
|
166201266U, // VQSUBuv2i32
|
|
179832754U, // VQSUBuv2i64
|
|
166725554U, // VQSUBuv4i16
|
|
166201266U, // VQSUBuv4i32
|
|
166725554U, // VQSUBuv8i16
|
|
167249842U, // VQSUBuv8i8
|
|
167774136U, // VRADDHNv2i32
|
|
168298424U, // VRADDHNv4i16
|
|
168822712U, // VRADDHNv8i8
|
|
770181056U, // VRECPEd
|
|
756082624U, // VRECPEfd
|
|
756082624U, // VRECPEfq
|
|
770181056U, // VRECPEq
|
|
152102855U, // VRECPSfd
|
|
152102855U, // VRECPSfq
|
|
773875662U, // VREV16d8
|
|
773875662U, // VREV16q8
|
|
778594261U, // VREV32d16
|
|
773875669U, // VREV32d8
|
|
778594261U, // VREV32q16
|
|
773875669U, // VREV32q8
|
|
778594268U, // VREV64d16
|
|
779118556U, // VREV64d32
|
|
773875676U, // VREV64d8
|
|
779118556U, // VREV64df
|
|
778594268U, // VREV64q16
|
|
779118556U, // VREV64q32
|
|
773875676U, // VREV64q8
|
|
779118556U, // VREV64qf
|
|
165677027U, // VRHADDsv16i8
|
|
164628451U, // VRHADDsv2i32
|
|
165152739U, // VRHADDsv4i16
|
|
164628451U, // VRHADDsv4i32
|
|
165152739U, // VRHADDsv8i16
|
|
165677027U, // VRHADDsv8i8
|
|
167249891U, // VRHADDuv16i8
|
|
166201315U, // VRHADDuv2i32
|
|
166725603U, // VRHADDuv4i16
|
|
166201315U, // VRHADDuv4i32
|
|
166725603U, // VRHADDuv8i16
|
|
167249891U, // VRHADDuv8i8
|
|
165677034U, // VRSHLsv16i8
|
|
179308522U, // VRSHLsv1i64
|
|
164628458U, // VRSHLsv2i32
|
|
179308522U, // VRSHLsv2i64
|
|
165152746U, // VRSHLsv4i16
|
|
164628458U, // VRSHLsv4i32
|
|
165152746U, // VRSHLsv8i16
|
|
165677034U, // VRSHLsv8i8
|
|
167249898U, // VRSHLuv16i8
|
|
179832810U, // VRSHLuv1i64
|
|
166201322U, // VRSHLuv2i32
|
|
179832810U, // VRSHLuv2i64
|
|
166725610U, // VRSHLuv4i16
|
|
166201322U, // VRSHLuv4i32
|
|
166725610U, // VRSHLuv8i16
|
|
167249898U, // VRSHLuv8i8
|
|
167774192U, // VRSHRNv2i32
|
|
168298480U, // VRSHRNv4i16
|
|
168822768U, // VRSHRNv8i8
|
|
165677047U, // VRSHRsv16i8
|
|
179308535U, // VRSHRsv1i64
|
|
164628471U, // VRSHRsv2i32
|
|
179308535U, // VRSHRsv2i64
|
|
165152759U, // VRSHRsv4i16
|
|
164628471U, // VRSHRsv4i32
|
|
165152759U, // VRSHRsv8i16
|
|
165677047U, // VRSHRsv8i8
|
|
167249911U, // VRSHRuv16i8
|
|
179832823U, // VRSHRuv1i64
|
|
166201335U, // VRSHRuv2i32
|
|
179832823U, // VRSHRuv2i64
|
|
166725623U, // VRSHRuv4i16
|
|
166201335U, // VRSHRuv4i32
|
|
166725623U, // VRSHRuv8i16
|
|
167249911U, // VRSHRuv8i8
|
|
770181117U, // VRSQRTEd
|
|
756082685U, // VRSQRTEfd
|
|
756082685U, // VRSQRTEfq
|
|
770181117U, // VRSQRTEq
|
|
152102917U, // VRSQRTSfd
|
|
152102917U, // VRSQRTSfq
|
|
836782093U, // VRSRAsv16i8
|
|
850413581U, // VRSRAsv1i64
|
|
835733517U, // VRSRAsv2i32
|
|
850413581U, // VRSRAsv2i64
|
|
836257805U, // VRSRAsv4i16
|
|
835733517U, // VRSRAsv4i32
|
|
836257805U, // VRSRAsv8i16
|
|
836782093U, // VRSRAsv8i8
|
|
838354957U, // VRSRAuv16i8
|
|
850937869U, // VRSRAuv1i64
|
|
837306381U, // VRSRAuv2i32
|
|
850937869U, // VRSRAuv2i64
|
|
837830669U, // VRSRAuv4i16
|
|
837306381U, // VRSRAuv4i32
|
|
837830669U, // VRSRAuv8i16
|
|
838354957U, // VRSRAuv8i8
|
|
167774227U, // VRSUBHNv2i32
|
|
168298515U, // VRSUBHNv4i16
|
|
168822803U, // VRSUBHNv8i8
|
|
845701444U, // VSETLNi16
|
|
846225732U, // VSETLNi32
|
|
840982852U, // VSETLNi8
|
|
168822811U, // VSHLLi16
|
|
168298523U, // VSHLLi32
|
|
169347099U, // VSHLLi8
|
|
164628507U, // VSHLLsv2i64
|
|
165152795U, // VSHLLsv4i32
|
|
165677083U, // VSHLLsv8i16
|
|
166201371U, // VSHLLuv2i64
|
|
166725659U, // VSHLLuv4i32
|
|
167249947U, // VSHLLuv8i16
|
|
169347105U, // VSHLiv16i8
|
|
167774241U, // VSHLiv1i64
|
|
168298529U, // VSHLiv2i32
|
|
167774241U, // VSHLiv2i64
|
|
168822817U, // VSHLiv4i16
|
|
168298529U, // VSHLiv4i32
|
|
168822817U, // VSHLiv8i16
|
|
169347105U, // VSHLiv8i8
|
|
165677089U, // VSHLsv16i8
|
|
179308577U, // VSHLsv1i64
|
|
164628513U, // VSHLsv2i32
|
|
179308577U, // VSHLsv2i64
|
|
165152801U, // VSHLsv4i16
|
|
164628513U, // VSHLsv4i32
|
|
165152801U, // VSHLsv8i16
|
|
165677089U, // VSHLsv8i8
|
|
167249953U, // VSHLuv16i8
|
|
179832865U, // VSHLuv1i64
|
|
166201377U, // VSHLuv2i32
|
|
179832865U, // VSHLuv2i64
|
|
166725665U, // VSHLuv4i16
|
|
166201377U, // VSHLuv4i32
|
|
166725665U, // VSHLuv8i16
|
|
167249953U, // VSHLuv8i8
|
|
167774246U, // VSHRNv2i32
|
|
168298534U, // VSHRNv4i16
|
|
168822822U, // VSHRNv8i8
|
|
165677100U, // VSHRsv16i8
|
|
179308588U, // VSHRsv1i64
|
|
164628524U, // VSHRsv2i32
|
|
179308588U, // VSHRsv2i64
|
|
165152812U, // VSHRsv4i16
|
|
164628524U, // VSHRsv4i32
|
|
165152812U, // VSHRsv8i16
|
|
165677100U, // VSHRsv8i8
|
|
167249964U, // VSHRuv16i8
|
|
179832876U, // VSHRuv1i64
|
|
166201388U, // VSHRuv2i32
|
|
179832876U, // VSHRuv2i64
|
|
166725676U, // VSHRuv4i16
|
|
166201388U, // VSHRuv4i32
|
|
166725676U, // VSHRuv8i16
|
|
167249964U, // VSHRuv8i8
|
|
180356706U, // VSHTOD
|
|
180880994U, // VSHTOS
|
|
785507938U, // VSITOD
|
|
777643618U, // VSITOS
|
|
840984625U, // VSLIv16i8
|
|
848848945U, // VSLIv1i64
|
|
846227505U, // VSLIv2i32
|
|
848848945U, // VSLIv2i64
|
|
845703217U, // VSLIv4i16
|
|
846227505U, // VSLIv4i32
|
|
845703217U, // VSLIv8i16
|
|
840984625U, // VSLIv8i8
|
|
181462626U, // VSLTOD
|
|
173598306U, // VSLTOS
|
|
755558454U, // VSQRTD
|
|
756082742U, // VSQRTS
|
|
836782140U, // VSRAsv16i8
|
|
850413628U, // VSRAsv1i64
|
|
835733564U, // VSRAsv2i32
|
|
850413628U, // VSRAsv2i64
|
|
836257852U, // VSRAsv4i16
|
|
835733564U, // VSRAsv4i32
|
|
836257852U, // VSRAsv8i16
|
|
836782140U, // VSRAsv8i8
|
|
838355004U, // VSRAuv16i8
|
|
850937916U, // VSRAuv1i64
|
|
837306428U, // VSRAuv2i32
|
|
850937916U, // VSRAuv2i64
|
|
837830716U, // VSRAuv4i16
|
|
837306428U, // VSRAuv4i32
|
|
837830716U, // VSRAuv8i16
|
|
838355004U, // VSRAuv8i8
|
|
840984641U, // VSRIv16i8
|
|
848848961U, // VSRIv1i64
|
|
846227521U, // VSRIv2i32
|
|
848848961U, // VSRIv2i64
|
|
845703233U, // VSRIv4i16
|
|
846227521U, // VSRIv4i32
|
|
845703233U, // VSRIv8i16
|
|
840984641U, // VSRIv8i8
|
|
242927686U, // VST1d16
|
|
1316669510U, // VST1d16Q
|
|
1383778374U, // VST1d16T
|
|
243451974U, // VST1d32
|
|
1317193798U, // VST1d32Q
|
|
1384302662U, // VST1d32T
|
|
243976262U, // VST1d64
|
|
244500550U, // VST1d8
|
|
1318242374U, // VST1d8Q
|
|
1385351238U, // VST1d8T
|
|
243451974U, // VST1df
|
|
241887302U, // VST1q16
|
|
242411590U, // VST1q32
|
|
245033030U, // VST1q64
|
|
237168710U, // VST1q8
|
|
242411590U, // VST1qf
|
|
1383778379U, // VST2LNd16
|
|
1384302667U, // VST2LNd32
|
|
1385351243U, // VST2LNd8
|
|
1383778379U, // VST2LNq16a
|
|
1383778379U, // VST2LNq16b
|
|
1384302667U, // VST2LNq32a
|
|
1384302667U, // VST2LNq32b
|
|
645580875U, // VST2d16
|
|
645580875U, // VST2d16D
|
|
646105163U, // VST2d32
|
|
646105163U, // VST2d32D
|
|
646629446U, // VST2d64
|
|
647153739U, // VST2d8
|
|
647153739U, // VST2d8D
|
|
1316669515U, // VST2q16
|
|
1317193803U, // VST2q32
|
|
1318242379U, // VST2q8
|
|
1316669520U, // VST3LNd16
|
|
1317193808U, // VST3LNd32
|
|
1318242384U, // VST3LNd8
|
|
1316669520U, // VST3LNq16a
|
|
1316669520U, // VST3LNq16b
|
|
1317193808U, // VST3LNq32a
|
|
1317193808U, // VST3LNq32b
|
|
1383778384U, // VST3d16
|
|
1384302672U, // VST3d32
|
|
1384826950U, // VST3d64
|
|
1385351248U, // VST3d8
|
|
1316685904U, // VST3q16a
|
|
1316685904U, // VST3q16b
|
|
1317210192U, // VST3q32a
|
|
1317210192U, // VST3q32b
|
|
1318258768U, // VST3q8a
|
|
1318258768U, // VST3q8b
|
|
1450887253U, // VST4LNd16
|
|
1451411541U, // VST4LNd32
|
|
1452460117U, // VST4LNd8
|
|
1450887253U, // VST4LNq16a
|
|
1450887253U, // VST4LNq16b
|
|
1451411541U, // VST4LNq32a
|
|
1451411541U, // VST4LNq32b
|
|
1316669525U, // VST4d16
|
|
1317193813U, // VST4d32
|
|
1317718086U, // VST4d64
|
|
1318242389U, // VST4d8
|
|
1450903637U, // VST4q16a
|
|
1450903637U, // VST4q16b
|
|
1451427925U, // VST4q32a
|
|
1451427925U, // VST4q32b
|
|
1452476501U, // VST4q8a
|
|
1452476501U, // VST4q8b
|
|
1610614874U, // VSTMD
|
|
1610614874U, // VSTMS
|
|
177760351U, // VSTRD
|
|
135932004U, // VSTRQ
|
|
175138911U, // VSTRS
|
|
151578731U, // VSUBD
|
|
167774320U, // VSUBHNv2i32
|
|
168298608U, // VSUBHNv4i16
|
|
168822896U, // VSUBHNv8i8
|
|
164628599U, // VSUBLsv2i64
|
|
165152887U, // VSUBLsv4i32
|
|
165677175U, // VSUBLsv8i16
|
|
166201463U, // VSUBLuv2i64
|
|
166725751U, // VSUBLuv4i32
|
|
167250039U, // VSUBLuv8i16
|
|
152103019U, // VSUBS
|
|
164628605U, // VSUBWsv2i64
|
|
165152893U, // VSUBWsv4i32
|
|
165677181U, // VSUBWsv8i16
|
|
166201469U, // VSUBWuv2i64
|
|
166725757U, // VSUBWuv4i32
|
|
167250045U, // VSUBWuv8i16
|
|
152103019U, // VSUBfd
|
|
152103019U, // VSUBfd_sfp
|
|
152103019U, // VSUBfq
|
|
169347179U, // VSUBv16i8
|
|
167774315U, // VSUBv1i64
|
|
168298603U, // VSUBv2i32
|
|
167774315U, // VSUBv2i64
|
|
168822891U, // VSUBv4i16
|
|
168298603U, // VSUBv4i32
|
|
168822891U, // VSUBv8i16
|
|
169347179U, // VSUBv8i8
|
|
739797123U, // VSWPd
|
|
739797123U, // VSWPq
|
|
169896072U, // VTBL1
|
|
840984712U, // VTBL2
|
|
237004936U, // VTBL3
|
|
639658120U, // VTBL4
|
|
840984717U, // VTBX1
|
|
237004941U, // VTBX2
|
|
639658125U, // VTBX3
|
|
1377855629U, // VTBX4
|
|
181929570U, // VTOSHD
|
|
182453858U, // VTOSHS
|
|
787081362U, // VTOSIRD
|
|
776595602U, // VTOSIRS
|
|
787080802U, // VTOSIZD
|
|
776595042U, // VTOSIZS
|
|
183035490U, // VTOSLD
|
|
172549730U, // VTOSLS
|
|
183502434U, // VTOUHD
|
|
184026722U, // VTOUHS
|
|
788654226U, // VTOUIRD
|
|
777119890U, // VTOUIRS
|
|
788653666U, // VTOUIZD
|
|
777119330U, // VTOUIZS
|
|
184608354U, // VTOULD
|
|
173074018U, // VTOULS
|
|
845703320U, // VTRNd16
|
|
846227608U, // VTRNd32
|
|
840984728U, // VTRNd8
|
|
845703320U, // VTRNq16
|
|
846227608U, // VTRNq32
|
|
840984728U, // VTRNq8
|
|
169896093U, // VTSTv16i8
|
|
175138973U, // VTSTv2i32
|
|
174614685U, // VTSTv4i16
|
|
175138973U, // VTSTv4i32
|
|
174614685U, // VTSTv8i16
|
|
169896093U, // VTSTv8i8
|
|
185075298U, // VUHTOD
|
|
185599586U, // VUHTOS
|
|
790226530U, // VUITOD
|
|
778167906U, // VUITOS
|
|
186181218U, // VULTOD
|
|
174122594U, // VULTOS
|
|
845703330U, // VUZPd16
|
|
846227618U, // VUZPd32
|
|
840984738U, // VUZPd8
|
|
845703330U, // VUZPq16
|
|
846227618U, // VUZPq32
|
|
840984738U, // VUZPq8
|
|
845703335U, // VZIPd16
|
|
846227623U, // VZIPd32
|
|
840984743U, // VZIPd8
|
|
845703335U, // VZIPq16
|
|
846227623U, // VZIPq32
|
|
840984743U, // VZIPq8
|
|
538970284U, // WFE
|
|
538970288U, // WFI
|
|
538970292U, // YIELD
|
|
1679319057U, // t2ADCSri
|
|
1730207761U, // t2ADCSrr
|
|
1797316625U, // t2ADCSrs
|
|
1679319057U, // t2ADCri
|
|
1730207761U, // t2ADCrr
|
|
1797316625U, // t2ADCrs
|
|
186703893U, // t2ADDSri
|
|
186703893U, // t2ADDSrr
|
|
857792533U, // t2ADDSrs
|
|
1730207770U, // t2ADDrSPi
|
|
135817402U, // t2ADDrSPi12
|
|
1797316634U, // t2ADDrSPs
|
|
1730207770U, // t2ADDri
|
|
1679321274U, // t2ADDri12
|
|
1730207770U, // t2ADDrr
|
|
1797316634U, // t2ADDrs
|
|
1679319108U, // t2ANDri
|
|
1730207812U, // t2ANDrr
|
|
1797316676U, // t2ANDrs
|
|
1730209983U, // t2ASRri
|
|
1730209983U, // t2ASRrr
|
|
69208259U, // t2B
|
|
135815244U, // t2BFC
|
|
806903888U, // t2BFI
|
|
1679319124U, // t2BICri
|
|
1730207828U, // t2BICrr
|
|
1797316692U, // t2BICrs
|
|
120062079U, // t2BR_JT
|
|
337141912U, // t2BXJ
|
|
388096159U, // t2Bcc
|
|
538968236U, // t2CLREX
|
|
739795122U, // t2CLZ
|
|
790683830U, // t2CMNzri
|
|
790683830U, // t2CMNzrr
|
|
186704054U, // t2CMNzrs
|
|
790683834U, // t2CMPri
|
|
790683834U, // t2CMPrr
|
|
186704058U, // t2CMPrs
|
|
790683834U, // t2CMPzri
|
|
790683834U, // t2CMPzrr
|
|
186704058U, // t2CMPzrs
|
|
939524286U, // t2CPS
|
|
337141954U, // t2DBG
|
|
590348639U, // t2DMBish
|
|
590872927U, // t2DMBishst
|
|
591397215U, // t2DMBnsh
|
|
591921503U, // t2DMBnshst
|
|
592445791U, // t2DMBosh
|
|
592970079U, // t2DMBoshst
|
|
593494367U, // t2DMBst
|
|
590348643U, // t2DSBish
|
|
590872931U, // t2DSBishst
|
|
591397219U, // t2DSBnsh
|
|
591921507U, // t2DSBnshst
|
|
592445795U, // t2DSBosh
|
|
592970083U, // t2DSBoshst
|
|
593494371U, // t2DSBst
|
|
1679319360U, // t2EORri
|
|
1730208064U, // t2EORrr
|
|
1797316928U, // t2EORrs
|
|
538968398U, // t2ISBsy
|
|
1811941576U, // t2IT
|
|
351U, // t2Int_MemBarrierV7
|
|
355U, // t2Int_SyncBarrierV7
|
|
1879050443U, // t2Int_eh_sjlj_setjmp
|
|
1027809658U, // t2LDM
|
|
1027809658U, // t2LDM_RET
|
|
135815559U, // t2LDRBT
|
|
806904194U, // t2LDRB_POST
|
|
806904194U, // t2LDRB_PRE
|
|
186704258U, // t2LDRBi12
|
|
135815554U, // t2LDRBi8
|
|
790684034U, // t2LDRBpci
|
|
857792898U, // t2LDRBs
|
|
806904205U, // t2LDRDi8
|
|
135815565U, // t2LDRDpci
|
|
739795346U, // t2LDREX
|
|
739795352U, // t2LDREXB
|
|
135815583U, // t2LDREXD
|
|
739795366U, // t2LDREXH
|
|
135815602U, // t2LDRHT
|
|
806904237U, // t2LDRH_POST
|
|
806904237U, // t2LDRH_PRE
|
|
186704301U, // t2LDRHi12
|
|
135815597U, // t2LDRHi8
|
|
790684077U, // t2LDRHpci
|
|
857792941U, // t2LDRHs
|
|
135815614U, // t2LDRSBT
|
|
806904248U, // t2LDRSB_POST
|
|
806904248U, // t2LDRSB_PRE
|
|
186704312U, // t2LDRSBi12
|
|
135815608U, // t2LDRSBi8
|
|
790684088U, // t2LDRSBpci
|
|
857792952U, // t2LDRSBs
|
|
135815627U, // t2LDRSHT
|
|
806904261U, // t2LDRSH_POST
|
|
806904261U, // t2LDRSH_PRE
|
|
186704325U, // t2LDRSHi12
|
|
135815621U, // t2LDRSHi8
|
|
790684101U, // t2LDRSHpci
|
|
857792965U, // t2LDRSHs
|
|
135815634U, // t2LDRT
|
|
806904190U, // t2LDR_POST
|
|
806904190U, // t2LDR_PRE
|
|
186704254U, // t2LDRi12
|
|
135815550U, // t2LDRi8
|
|
790684030U, // t2LDRpci
|
|
67111120U, // t2LDRpci_pic
|
|
857792894U, // t2LDRs
|
|
790841561U, // t2LEApcrel
|
|
186861785U, // t2LEApcrelJT
|
|
1730210013U, // t2LSLri
|
|
1730210013U, // t2LSLrr
|
|
1730210017U, // t2LSRri
|
|
1730210017U, // t2LSRrr
|
|
806904309U, // t2MLA
|
|
806904313U, // t2MLS
|
|
857794751U, // t2MOVCCasr
|
|
186704381U, // t2MOVCCi
|
|
857794781U, // t2MOVCClsl
|
|
857794785U, // t2MOVCClsr
|
|
186704381U, // t2MOVCCr
|
|
857794789U, // t2MOVCCror
|
|
135815681U, // t2MOVTi16
|
|
1967350269U, // t2MOVi
|
|
739795462U, // t2MOVi16
|
|
739795462U, // t2MOVi32imm
|
|
1967350269U, // t2MOVr
|
|
1967212777U, // t2MOVrx
|
|
67111149U, // t2MOVsra_flag
|
|
67111157U, // t2MOVsrl_flag
|
|
337142312U, // t2MRS
|
|
337142312U, // t2MRSsys
|
|
359162412U, // t2MSR
|
|
359686700U, // t2MSRsys
|
|
135815728U, // t2MUL
|
|
1967211060U, // t2MVNi
|
|
790684212U, // t2MVNr
|
|
186704436U, // t2MVNs
|
|
594018872U, // t2NOP
|
|
1679321341U, // t2ORNri
|
|
1679321341U, // t2ORNrr
|
|
1746430205U, // t2ORNrs
|
|
1679319612U, // t2ORRri
|
|
1730208316U, // t2ORRrr
|
|
1797317180U, // t2ORRrs
|
|
806904386U, // t2PKHBT
|
|
806904392U, // t2PKHTB
|
|
740002049U, // t2PLDWi12
|
|
740010241U, // t2PLDWi8
|
|
795871489U, // t2PLDWpci
|
|
796641537U, // t2PLDWr
|
|
192669953U, // t2PLDWs
|
|
740002054U, // t2PLDi12
|
|
740010246U, // t2PLDi8
|
|
795871494U, // t2PLDpci
|
|
796641542U, // t2PLDr
|
|
192669958U, // t2PLDs
|
|
740002058U, // t2PLIi12
|
|
740010250U, // t2PLIi8
|
|
795871498U, // t2PLIpci
|
|
796641546U, // t2PLIr
|
|
192669962U, // t2PLIs
|
|
135815793U, // t2QADD
|
|
135815798U, // t2QADD16
|
|
135815805U, // t2QADD8
|
|
135815811U, // t2QASX
|
|
135815816U, // t2QDADD
|
|
135815822U, // t2QDSUB
|
|
135815828U, // t2QSAX
|
|
135815833U, // t2QSUB
|
|
135815838U, // t2QSUB16
|
|
135815845U, // t2QSUB8
|
|
739795627U, // t2RBIT
|
|
790684336U, // t2REV
|
|
790684340U, // t2REV16
|
|
790684346U, // t2REVSH
|
|
337144078U, // t2RFEDB
|
|
337144084U, // t2RFEDBW
|
|
337144090U, // t2RFEIA
|
|
337144090U, // t2RFEIAW
|
|
1730210021U, // t2RORri
|
|
1730210021U, // t2RORrr
|
|
2013266633U, // t2RSBSri
|
|
1947755209U, // t2RSBSrs
|
|
186704585U, // t2RSBri
|
|
806904521U, // t2RSBrs
|
|
135815895U, // t2SADD16
|
|
135815902U, // t2SADD8
|
|
135815908U, // t2SASX
|
|
1679319791U, // t2SBCSri
|
|
1730208495U, // t2SBCSrr
|
|
1797317359U, // t2SBCSrs
|
|
1679319791U, // t2SBCri
|
|
1730208495U, // t2SBCrr
|
|
1797317359U, // t2SBCrs
|
|
806904563U, // t2SBFX
|
|
135817504U, // t2SDIV
|
|
135815928U, // t2SEL
|
|
594019088U, // t2SEV
|
|
135815956U, // t2SHADD16
|
|
135815964U, // t2SHADD8
|
|
135815971U, // t2SHASX
|
|
135815977U, // t2SHSAX
|
|
135815983U, // t2SHSUB16
|
|
135815991U, // t2SHSUB8
|
|
337142590U, // t2SMC
|
|
806904642U, // t2SMLABB
|
|
806904649U, // t2SMLABT
|
|
806904656U, // t2SMLAD
|
|
806904662U, // t2SMLADX
|
|
806904669U, // t2SMLAL
|
|
806904675U, // t2SMLALBB
|
|
806904683U, // t2SMLALBT
|
|
806904691U, // t2SMLALD
|
|
806904698U, // t2SMLALDX
|
|
806904706U, // t2SMLALTB
|
|
806904714U, // t2SMLALTT
|
|
806904722U, // t2SMLATB
|
|
806904729U, // t2SMLATT
|
|
806904736U, // t2SMLAWB
|
|
806904743U, // t2SMLAWT
|
|
806904750U, // t2SMLSD
|
|
806904756U, // t2SMLSDX
|
|
806904763U, // t2SMLSLD
|
|
806904770U, // t2SMLSLDX
|
|
806904778U, // t2SMMLA
|
|
806904784U, // t2SMMLAR
|
|
806904791U, // t2SMMLS
|
|
806904797U, // t2SMMLSR
|
|
135816164U, // t2SMMUL
|
|
135816170U, // t2SMMULR
|
|
135816177U, // t2SMUAD
|
|
135816183U, // t2SMUADX
|
|
135816190U, // t2SMULBB
|
|
135816197U, // t2SMULBT
|
|
806904844U, // t2SMULL
|
|
135816210U, // t2SMULTB
|
|
135816217U, // t2SMULTT
|
|
135816224U, // t2SMULWB
|
|
135816231U, // t2SMULWT
|
|
135816238U, // t2SMUSD
|
|
135816244U, // t2SMUSDX
|
|
364931365U, // t2SRSDB
|
|
365455653U, // t2SRSDBW
|
|
364931371U, // t2SRSIA
|
|
365455659U, // t2SRSIAW
|
|
135816255U, // t2SSAT16
|
|
806904902U, // t2SSATasr
|
|
806904902U, // t2SSATlsl
|
|
135816267U, // t2SSAX
|
|
135816272U, // t2SSUB16
|
|
135816279U, // t2SSUB8
|
|
1027810406U, // t2STM
|
|
135816307U, // t2STRBT
|
|
806880366U, // t2STRB_POST
|
|
806880366U, // t2STRB_PRE
|
|
186705006U, // t2STRBi12
|
|
135816302U, // t2STRBi8
|
|
857793646U, // t2STRBs
|
|
806904953U, // t2STRDi8
|
|
135816318U, // t2STREX
|
|
135816324U, // t2STREXB
|
|
806904971U, // t2STREXD
|
|
135816338U, // t2STREXH
|
|
135816350U, // t2STRHT
|
|
806880409U, // t2STRH_POST
|
|
806880409U, // t2STRH_PRE
|
|
186705049U, // t2STRHi12
|
|
135816345U, // t2STRHi8
|
|
857793689U, // t2STRHs
|
|
135816356U, // t2STRT
|
|
806880362U, // t2STR_POST
|
|
806880362U, // t2STR_PRE
|
|
186705002U, // t2STRi12
|
|
135816298U, // t2STRi8
|
|
857793642U, // t2STRs
|
|
186705065U, // t2SUBSri
|
|
186705065U, // t2SUBSrr
|
|
857793705U, // t2SUBSrs
|
|
1730208942U, // t2SUBrSPi
|
|
135817521U, // t2SUBrSPi12
|
|
67111222U, // t2SUBrSPi12_
|
|
67111230U, // t2SUBrSPi_
|
|
1746429102U, // t2SUBrSPs
|
|
67111239U, // t2SUBrSPs_
|
|
1730208942U, // t2SUBri
|
|
1679321393U, // t2SUBri12
|
|
1730208942U, // t2SUBrr
|
|
1797317806U, // t2SUBrs
|
|
135816383U, // t2SXTAB16rr
|
|
806905023U, // t2SXTAB16rr_rot
|
|
135816391U, // t2SXTABrr
|
|
806905031U, // t2SXTABrr_rot
|
|
135816397U, // t2SXTAHrr
|
|
806905037U, // t2SXTAHrr_rot
|
|
739796179U, // t2SXTB16r
|
|
135816403U, // t2SXTB16r_rot
|
|
790684890U, // t2SXTBr
|
|
186705114U, // t2SXTBr_rot
|
|
790684895U, // t2SXTHr
|
|
186705119U, // t2SXTHr_rot
|
|
2080377166U, // t2TBB
|
|
796641619U, // t2TBBgen
|
|
2080377175U, // t2TBH
|
|
796658012U, // t2TBHgen
|
|
790684900U, // t2TEQri
|
|
790684900U, // t2TEQrr
|
|
186705124U, // t2TEQrs
|
|
1256U, // t2TPsoft
|
|
790684928U, // t2TSTri
|
|
790684928U, // t2TSTrr
|
|
186705152U, // t2TSTrs
|
|
135816452U, // t2UADD16
|
|
135816459U, // t2UADD8
|
|
135816465U, // t2UASX
|
|
806905110U, // t2UBFX
|
|
135817568U, // t2UDIV
|
|
135816475U, // t2UHADD16
|
|
135816483U, // t2UHADD8
|
|
135816490U, // t2UHASX
|
|
135816496U, // t2UHSAX
|
|
135816502U, // t2UHSUB16
|
|
135816510U, // t2UHSUB8
|
|
806905157U, // t2UMAAL
|
|
806905163U, // t2UMLAL
|
|
806905169U, // t2UMULL
|
|
135816535U, // t2UQADD16
|
|
135816543U, // t2UQADD8
|
|
135816550U, // t2UQASX
|
|
135816556U, // t2UQSAX
|
|
135816562U, // t2UQSUB16
|
|
135816570U, // t2UQSUB8
|
|
135816577U, // t2USAD8
|
|
806905223U, // t2USADA8
|
|
135816590U, // t2USAT16
|
|
806905237U, // t2USATasr
|
|
806905237U, // t2USATlsl
|
|
135816602U, // t2USAX
|
|
135816607U, // t2USUB16
|
|
135816614U, // t2USUB8
|
|
135816620U, // t2UXTAB16rr
|
|
806905260U, // t2UXTAB16rr_rot
|
|
135816628U, // t2UXTABrr
|
|
806905268U, // t2UXTABrr_rot
|
|
135816634U, // t2UXTAHrr
|
|
806905274U, // t2UXTAHrr_rot
|
|
739796416U, // t2UXTB16r
|
|
135816640U, // t2UXTB16r_rot
|
|
790685127U, // t2UXTBr
|
|
186705351U, // t2UXTBr_rot
|
|
790685132U, // t2UXTHr
|
|
186705356U, // t2UXTHr_rot
|
|
594020524U, // t2WFE
|
|
594020528U, // t2WFI
|
|
594020532U, // t2YIELD
|
|
2206474257U, // tADC
|
|
135815194U, // tADDhirr
|
|
2206220314U, // tADDi3
|
|
2206474266U, // tADDi8
|
|
126355813U, // tADDrPCi
|
|
67127653U, // tADDrSP
|
|
67111269U, // tADDrSPi
|
|
2206220314U, // tADDrr
|
|
67389797U, // tADDspi
|
|
67127653U, // tADDspr
|
|
67127658U, // tADDspr_
|
|
69208433U, // tADJCALLSTACKDOWN
|
|
69208454U, // tADJCALLSTACKUP
|
|
2206474308U, // tAND
|
|
67127705U, // tANDsp
|
|
2206222527U, // tASRri
|
|
2206476479U, // tASRrr
|
|
69206089U, // tB
|
|
2206474324U, // tBIC
|
|
69208480U, // tBKPT
|
|
402653277U, // tBL
|
|
402653281U, // tBLXi
|
|
402653281U, // tBLXi_r9
|
|
69206113U, // tBLXr
|
|
69206113U, // tBLXr_r9
|
|
402653277U, // tBLr9
|
|
69206143U, // tBRIND
|
|
126877823U, // tBR_JTr
|
|
69206152U, // tBX
|
|
2470U, // tBX_RET
|
|
69206121U, // tBX_RET_vararg
|
|
69206152U, // tBXr9
|
|
337141919U, // tBcc
|
|
127402077U, // tBfar
|
|
67111340U, // tCBNZ
|
|
67111346U, // tCBZ
|
|
739795126U, // tCMNz
|
|
739795130U, // tCMPhir
|
|
739795130U, // tCMPi8
|
|
739795130U, // tCMPr
|
|
739795130U, // tCMPzhir
|
|
739795130U, // tCMPzi8
|
|
739795130U, // tCMPzr
|
|
939524286U, // tCPS
|
|
2206474560U, // tEOR
|
|
1879050443U, // tInt_eh_sjlj_setjmp
|
|
1027686778U, // tLDM
|
|
806904190U, // tLDR
|
|
806904194U, // tLDRB
|
|
806904194U, // tLDRBi
|
|
806904237U, // tLDRH
|
|
806904237U, // tLDRHi
|
|
135815608U, // tLDRSB
|
|
135815621U, // tLDRSH
|
|
739795326U, // tLDRcp
|
|
806904190U, // tLDRi
|
|
799015294U, // tLDRpci
|
|
67111351U, // tLDRpci_pic
|
|
135815550U, // tLDRspi
|
|
739797209U, // tLEApcrel
|
|
135817433U, // tLEApcrelJT
|
|
2206222557U, // tLSLri
|
|
2206476509U, // tLSLrr
|
|
2206222561U, // tLSRri
|
|
2206476513U, // tLSRrr
|
|
135815677U, // tMOVCCi
|
|
135815677U, // tMOVCCr
|
|
136317376U, // tMOVCCr_pseudo
|
|
67111371U, // tMOVSr
|
|
67111377U, // tMOVgpr2gpr
|
|
67111377U, // tMOVgpr2tgpr
|
|
2208948733U, // tMOVi8
|
|
67111377U, // tMOVr
|
|
67111377U, // tMOVtgpr2gpr
|
|
2206474800U, // tMUL
|
|
2208948788U, // tMVN
|
|
538968632U, // tNOP
|
|
2206474812U, // tORR
|
|
1202717248U, // tPICADD
|
|
538733014U, // tPOP
|
|
538733014U, // tPOP_RET
|
|
538733018U, // tPUSH
|
|
739795632U, // tREV
|
|
739795636U, // tREV16
|
|
739795642U, // tREVSH
|
|
2206476517U, // tROR
|
|
2208940745U, // tRSB
|
|
135815550U, // tRestore
|
|
2206474991U, // tSBC
|
|
764U, // tSETENDBE
|
|
774U, // tSETENDLE
|
|
538968848U, // tSEV
|
|
1027687526U, // tSTM
|
|
806904938U, // tSTR
|
|
806904942U, // tSTRB
|
|
806904942U, // tSTRBi
|
|
806904985U, // tSTRH
|
|
806904985U, // tSTRHi
|
|
806904938U, // tSTRi
|
|
135816298U, // tSTRspi
|
|
2206221486U, // tSUBi3
|
|
2206475438U, // tSUBi8
|
|
2206221486U, // tSUBrr
|
|
67389919U, // tSUBspi
|
|
67389767U, // tSUBspi_
|
|
337142962U, // tSVC
|
|
739796186U, // tSXTB
|
|
739796191U, // tSXTH
|
|
135816298U, // tSpill
|
|
1256U, // tTPsoft
|
|
1275U, // tTRAP
|
|
739796224U, // tTST
|
|
739796423U, // tUXTB
|
|
739796428U, // tUXTH
|
|
538970284U, // tWFE
|
|
538970288U, // tWFI
|
|
538970292U, // tYIELD
|
|
0U
|
|
};
|
|
|
|
const char *AsmStrs =
|
|
"DBG_VALUE\000adcs\t\000adc\000adds\000add\000@ ADJCALLSTACKDOWN \000@ A"
|
|
"DJCALLSTACKUP \000and\000\000b\t\000bfc\000bfi\000bic\000bkpt\000bl\t\000"
|
|
"blx\t\000bl\000bx\t\000add\tpc, \000ldr\tpc, \000mov\tpc, \000mov\tlr, "
|
|
"pc\n\tbx\t\000bxj\000bx\000b\000cdp\000cdp2\tp\000clrex\000clz\000cmn\000"
|
|
"cmp\000cps\000dbg\000dmb\tish\000dmb\tishst\000dmb\tnsh\000dmb\tnshst\000"
|
|
"dmb\tosh\000dmb\toshst\000dmb\tst\000dsb\tish\000dsb\tishst\000dsb\tnsh"
|
|
"\000dsb\tnshst\000dsb\tosh\000dsb\toshst\000dsb\tst\000eor\000vmov\000v"
|
|
"mrs\000isb\000mcr\tp15, 0, \000dmb\000dsb\000str\tsp, [\000ldc2\000ldc\000"
|
|
"ldm\000ldr\000ldrb\000ldrbt\000ldrd\000ldrex\000ldrexb\000ldrexd\000ldr"
|
|
"exh\000ldrh\000ldrht\000ldrsb\000ldrsbt\000ldrsh\000ldrsht\000ldrt\000."
|
|
"set \000mcr\000mcr2\tp\000mcrr\000mcrr2\tp\000mla\000mls\000mov\000movt"
|
|
"\000movw\000movs\000mrc\000mrc2\tp\000mrrc\000mrrc2\tp\000mrs\000msr\000"
|
|
"mul\000mvn\000nop\000orr\000\n\000pkhbt\000pkhtb\000pldw\t[\000pldw\t\000"
|
|
"pld\t[\000pld\t\000pli\t[\000pli\t\000qadd\000qadd16\000qadd8\000qasx\000"
|
|
"qdadd\000qdsub\000qsax\000qsub\000qsub16\000qsub8\000rbit\000rev\000rev"
|
|
"16\000revsh\000rfe\000rsbs\000rsb\000rscs\t\000rsc\000sadd16\000sadd8\000"
|
|
"sasx\000sbcs\t\000sbc\000sbfx\000sel\000setend\tbe\000setend\tle\000sev"
|
|
"\000shadd16\000shadd8\000shasx\000shsax\000shsub16\000shsub8\000smc\000"
|
|
"smlabb\000smlabt\000smlad\000smladx\000smlal\000smlalbb\000smlalbt\000s"
|
|
"mlald\000smlaldx\000smlaltb\000smlaltt\000smlatb\000smlatt\000smlawb\000"
|
|
"smlawt\000smlsd\000smlsdx\000smlsld\000smlsldx\000smmla\000smmlar\000sm"
|
|
"mls\000smmlsr\000smmul\000smmulr\000smuad\000smuadx\000smulbb\000smulbt"
|
|
"\000smull\000smultb\000smultt\000smulwb\000smulwt\000smusd\000smusdx\000"
|
|
"srs\000ssat16\000ssat\000ssax\000ssub16\000ssub8\000stc2\000stc\000stm\000"
|
|
"str\000strb\000strbt\000strd\000strex\000strexb\000strexd\000strexh\000"
|
|
"strh\000strht\000strt\000subs\000sub\000svc\000swp\000swpb\000sxtab16\000"
|
|
"sxtab\000sxtah\000sxtb16\000sxtb\000sxth\000teq\000bl\t__aeabi_read_tp\000"
|
|
"trap\000tst\000uadd16\000uadd8\000uasx\000ubfx\000uhadd16\000uhadd8\000"
|
|
"uhasx\000uhsax\000uhsub16\000uhsub8\000umaal\000umlal\000umull\000uqadd"
|
|
"16\000uqadd8\000uqasx\000uqsax\000uqsub16\000uqsub8\000usad8\000usada8\000"
|
|
"usat16\000usat\000usax\000usub16\000usub8\000uxtab16\000uxtab\000uxtah\000"
|
|
"uxtb16\000uxtb\000uxth\000vabal\000vaba\000vabdl\000vabd\000vabs\000vac"
|
|
"ge\000vacgt\000vadd\000vaddhn\000vaddl\000vaddw\000vand\000vbic\000vbif"
|
|
"\000vbit\000vbsl\000vceq\000vcge\000vcgt\000vcle\000vcls\000vclt\000vcl"
|
|
"z\000vcmp\000vcmpe\000vcnt\000vcvtb\000vcvt\000vcvtt\000vdiv\000vdup\000"
|
|
"veor\000vext\000vhadd\000vhsub\000vld1\000vld2\000vld3\000vld4\000vldm\000"
|
|
"vldr\000vldmia\000vmax\000vmin\000vmla\000vmlal\000vmls\000vmlsl\000vmo"
|
|
"vl\000vmovn\000vmsr\000vmul\000vmull\000vmvn\000vneg\000vnmla\000vnmls\000"
|
|
"vnmul\000vorn\000vorr\000vpadal\000vpaddl\000vpadd\000vpmax\000vpmin\000"
|
|
"vqabs\000vqadd\000vqdmlal\000vqdmlsl\000vqdmulh\000vqdmull\000vqmovun\000"
|
|
"vqmovn\000vqneg\000vqrdmulh\000vqrshl\000vqrshrn\000vqrshrun\000vqshl\000"
|
|
"vqshlu\000vqshrn\000vqshrun\000vqsub\000vraddhn\000vrecpe\000vrecps\000"
|
|
"vrev16\000vrev32\000vrev64\000vrhadd\000vrshl\000vrshrn\000vrshr\000vrs"
|
|
"qrte\000vrsqrts\000vrsra\000vrsubhn\000vshll\000vshl\000vshrn\000vshr\000"
|
|
"vsli\000vsqrt\000vsra\000vsri\000vst1\000vst2\000vst3\000vst4\000vstm\000"
|
|
"vstr\000vstmia\000vsub\000vsubhn\000vsubl\000vsubw\000vswp\000vtbl\000v"
|
|
"tbx\000vcvtr\000vtrn\000vtst\000vuzp\000vzip\000wfe\000wfi\000yield\000"
|
|
"addw\000asr\000b.w\t\000it\000str\t\000@ ldr.w\t\000adr\000lsl\000lsr\000"
|
|
"ror\000rrx\000asrs.w\t\000lsrs.w\t\000orn\000pldw\000pld\000pli\000rfea"
|
|
"b\000rfedb\000rfeia\000sdiv\000srsdb\000srsia\000subw\000@ subw\t\000@ "
|
|
"sub.w\t\000@ sub\t\000tbb\t\000tbb\000tbh\t\000tbh\000udiv\000add\t\000"
|
|
"@ add\t\000@ tADJCALLSTACKDOWN \000@ tADJCALLSTACKUP \000@ and\t\000bkp"
|
|
"t\t\000bx\tlr\000cbnz\t\000cbz\t\000@ ldr.n\t\000@ tMOVCCr \000movs\t\000"
|
|
"mov\t\000pop\000push\000sub\t\000";
|
|
|
|
O << "\t";
|
|
|
|
// Emit the opcode for the instruction.
|
|
unsigned Bits = OpInfo[MI->getOpcode()];
|
|
assert(Bits != 0 && "Cannot print this instruction.");
|
|
O << AsmStrs+(Bits & 4095)-1;
|
|
|
|
|
|
// Fragment 0 encoded into 6 bits for 33 unique commands.
|
|
switch ((Bits >> 26) & 63) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// DBG_VALUE, CLREX, DMBish, DMBishst, DMBnsh, DMBnshst, DMBosh, DMBoshst...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// ADCSSri, ADCSSrr, ADCSSrs, ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, B...
|
|
printOperand(MI, 0);
|
|
break;
|
|
case 2:
|
|
// ADCri, ADCrr, ADDSri, ADDSrr, ADDri, ADDrr, ANDri, ANDrr, BFC, BFI, BI...
|
|
printPredicateOperand(MI, 3);
|
|
break;
|
|
case 3:
|
|
// ADCrs, ADDSrs, ADDrs, ANDrs, BICrs, EORrs, LDC2L_OFFSET, LDC2L_POST, L...
|
|
printPredicateOperand(MI, 5);
|
|
break;
|
|
case 4:
|
|
// ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, ATOMIC_CMP_SWAP_I8, ATOMIC_L...
|
|
PrintSpecial(MI, "comment");
|
|
break;
|
|
case 5:
|
|
// BKPT, BL_pred, BLr9_pred, BXJ, Bcc, DBG, MRS, MRSsys, MSR, MSRi, MSRsy...
|
|
printPredicateOperand(MI, 1);
|
|
break;
|
|
case 6:
|
|
// BL, BLr9, tBL, tBLXi, tBLXi_r9, tBLr9
|
|
printOperand(MI, 0, "call");
|
|
return;
|
|
break;
|
|
case 7:
|
|
// BR_JTm, PLDWr, PLDr, PLIr
|
|
printAddrMode2Operand(MI, 0);
|
|
break;
|
|
case 8:
|
|
// BX_RET, FMSTAT, NOP, SEV, TRAP, WFE, WFI, YIELD, t2CLREX, t2DMBish, t2...
|
|
printPredicateOperand(MI, 0);
|
|
break;
|
|
case 9:
|
|
// CDP, LDRD_POST, LDRD_PRE, MCR, MRC, STRD_POST, STRD_PRE, VLD2d16, VLD2...
|
|
printPredicateOperand(MI, 6);
|
|
break;
|
|
case 10:
|
|
// CDP2, MCR2, MCRR2, MRC2, MRRC2
|
|
printNoHashImmediate(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 11:
|
|
// CLZ, CMNzri, CMNzrr, CMPri, CMPrr, CMPzri, CMPzrr, FCONSTD, FCONSTS, L...
|
|
printPredicateOperand(MI, 2);
|
|
break;
|
|
case 12:
|
|
// CMNzrs, CMPrs, CMPzrs, LDC2L_OPTION, LDC2_OPTION, LDCL_OPTION, LDC_OPT...
|
|
printPredicateOperand(MI, 4);
|
|
break;
|
|
case 13:
|
|
// CONSTPOOL_ENTRY
|
|
printCPInstOperand(MI, 0, "label");
|
|
O << ' ';
|
|
printCPInstOperand(MI, 1, "cpentry");
|
|
return;
|
|
break;
|
|
case 14:
|
|
// CPS, t2CPS, tCPS
|
|
printOperand(MI, 0, "cps");
|
|
return;
|
|
break;
|
|
case 15:
|
|
// LDM, LDM_RET, RFE, RFEW, SRS, SRSW, STM, t2LDM, t2LDM_RET, t2STM, tLDM...
|
|
printAddrMode4Operand(MI, 0, "submode");
|
|
break;
|
|
case 16:
|
|
// LEApcrel, LEApcrelJT
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELV";
|
|
PrintSpecial(MI, "uid");
|
|
O << ", (";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 17:
|
|
// PICADD, tPICADD
|
|
printPCLabel(MI, 2);
|
|
break;
|
|
case 18:
|
|
// PICLDR, PICLDRB, PICLDRH, PICLDRSB, PICLDRSH, PICSTR, PICSTRB, PICSTRH
|
|
printAddrModePCOperand(MI, 1, "label");
|
|
break;
|
|
case 19:
|
|
// VLD1d16Q, VLD1d32Q, VLD1d8Q, VLD2q16, VLD2q32, VLD2q8, VLD3q16a, VLD3q...
|
|
printPredicateOperand(MI, 8);
|
|
break;
|
|
case 20:
|
|
// VLD1d16T, VLD1d32T, VLD1d8T, VLD3d16, VLD3d32, VLD3d64, VLD3d8, VST1d1...
|
|
printPredicateOperand(MI, 7);
|
|
break;
|
|
case 21:
|
|
// VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16a, VLD2LNq16b, VLD2LNq32a, VL...
|
|
printPredicateOperand(MI, 9);
|
|
break;
|
|
case 22:
|
|
// VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16a, VLD3LNq16b, VLD3LNq32a, VL...
|
|
printPredicateOperand(MI, 11);
|
|
break;
|
|
case 23:
|
|
// VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16a, VLD4LNq16b, VLD4LNq32a, VL...
|
|
printPredicateOperand(MI, 13);
|
|
break;
|
|
case 24:
|
|
// VLDMD, VLDMS, VSTMD, VSTMS
|
|
printAddrMode5Operand(MI, 0, "submode");
|
|
printPredicateOperand(MI, 2);
|
|
O << "\t";
|
|
printAddrMode5Operand(MI, 0, "base");
|
|
O << ", ";
|
|
printRegisterList(MI, 4);
|
|
return;
|
|
break;
|
|
case 25:
|
|
// t2ADCSri, t2ADCSrr, t2ADCri, t2ADCrr, t2ADDrSPi, t2ADDri, t2ADDri12, t...
|
|
printSBitModifierOperand(MI, 5);
|
|
printPredicateOperand(MI, 3);
|
|
break;
|
|
case 26:
|
|
// t2ADCSrs, t2ADCrs, t2ADDrSPs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2OR...
|
|
printSBitModifierOperand(MI, 6);
|
|
printPredicateOperand(MI, 4);
|
|
break;
|
|
case 27:
|
|
// t2IT
|
|
printThumbITMask(MI, 1);
|
|
O << "\t";
|
|
printMandatoryPredicateOperand(MI, 0);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// t2Int_eh_sjlj_setjmp, tInt_eh_sjlj_setjmp
|
|
printOperand(MI, 1);
|
|
O << ", [";
|
|
printOperand(MI, 0);
|
|
O << ", #8]\t@ begin eh.setjmp\n\tmov\t";
|
|
printOperand(MI, 1);
|
|
O << ", pc\n\tadds\t";
|
|
printOperand(MI, 1);
|
|
O << ", #9\n\tstr\t";
|
|
printOperand(MI, 1);
|
|
O << ", [";
|
|
printOperand(MI, 0);
|
|
O << ", #4]\n\tmovs\tr0, #0\n\tb\t1f\n\tmovs\tr0, #1\t@ end eh.setjmp\n1:";
|
|
return;
|
|
break;
|
|
case 29:
|
|
// t2MOVi, t2MOVr, t2MOVrx, t2MVNi, t2RSBSrs
|
|
printSBitModifierOperand(MI, 4);
|
|
break;
|
|
case 30:
|
|
// t2RSBSri
|
|
printSBitModifierOperand(MI, 3);
|
|
O << ".w\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 31:
|
|
// t2TBB, t2TBH
|
|
printTBAddrMode(MI, 0);
|
|
O << "\n";
|
|
printJT2BlockOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 32:
|
|
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
|
|
printSBitModifierOperand(MI, 1);
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 1 encoded into 7 bits for 119 unique commands.
|
|
switch ((Bits >> 19) & 127) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MCR2, MCRR2, MRC2, MRRC2, PLDWi, ...
|
|
O << ", ";
|
|
break;
|
|
case 1:
|
|
// ADCri, ADCrr, ADDri, ADDrr, ANDri, ANDrr, BICri, BICrr, EORri, EORrr, ...
|
|
printSBitModifierOperand(MI, 5);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
break;
|
|
case 2:
|
|
// ADCrs, ADDrs, ANDrs, BICrs, EORrs, ORRrs, RSBrs, RSCrs, SBCrs, SUBrs
|
|
printSBitModifierOperand(MI, 7);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printSORegOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ADDSri, ADDSrr, ADDSrs, BFC, BFI, BKPT, BL_pred, BLr9_pred, BXJ, Bcc, ...
|
|
O << "\t";
|
|
break;
|
|
case 4:
|
|
// ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, BLXr9, BRIND, BX, BXr9, NOP,...
|
|
return;
|
|
break;
|
|
case 5:
|
|
// ATOMIC_CMP_SWAP_I16
|
|
O << " ATOMIC_CMP_SWAP_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 6:
|
|
// ATOMIC_CMP_SWAP_I32
|
|
O << " ATOMIC_CMP_SWAP_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 7:
|
|
// ATOMIC_CMP_SWAP_I8
|
|
O << " ATOMIC_CMP_SWAP_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 8:
|
|
// ATOMIC_LOAD_ADD_I16
|
|
O << " ATOMIC_LOAD_ADD_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 9:
|
|
// ATOMIC_LOAD_ADD_I32
|
|
O << " ATOMIC_LOAD_ADD_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 10:
|
|
// ATOMIC_LOAD_ADD_I8
|
|
O << " ATOMIC_LOAD_ADD_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 11:
|
|
// ATOMIC_LOAD_AND_I16
|
|
O << " ATOMIC_LOAD_AND_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 12:
|
|
// ATOMIC_LOAD_AND_I32
|
|
O << " ATOMIC_LOAD_AND_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 13:
|
|
// ATOMIC_LOAD_AND_I8
|
|
O << " ATOMIC_LOAD_AND_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 14:
|
|
// ATOMIC_LOAD_NAND_I16
|
|
O << " ATOMIC_LOAD_NAND_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 15:
|
|
// ATOMIC_LOAD_NAND_I32
|
|
O << " ATOMIC_LOAD_NAND_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 16:
|
|
// ATOMIC_LOAD_NAND_I8
|
|
O << " ATOMIC_LOAD_NAND_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 17:
|
|
// ATOMIC_LOAD_OR_I16
|
|
O << " ATOMIC_LOAD_OR_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 18:
|
|
// ATOMIC_LOAD_OR_I32
|
|
O << " ATOMIC_LOAD_OR_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 19:
|
|
// ATOMIC_LOAD_OR_I8
|
|
O << " ATOMIC_LOAD_OR_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 20:
|
|
// ATOMIC_LOAD_SUB_I16
|
|
O << " ATOMIC_LOAD_SUB_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 21:
|
|
// ATOMIC_LOAD_SUB_I32
|
|
O << " ATOMIC_LOAD_SUB_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 22:
|
|
// ATOMIC_LOAD_SUB_I8
|
|
O << " ATOMIC_LOAD_SUB_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 23:
|
|
// ATOMIC_LOAD_XOR_I16
|
|
O << " ATOMIC_LOAD_XOR_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 24:
|
|
// ATOMIC_LOAD_XOR_I32
|
|
O << " ATOMIC_LOAD_XOR_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 25:
|
|
// ATOMIC_LOAD_XOR_I8
|
|
O << " ATOMIC_LOAD_XOR_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 26:
|
|
// ATOMIC_SWAP_I16
|
|
O << " ATOMIC_SWAP_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 27:
|
|
// ATOMIC_SWAP_I32
|
|
O << " ATOMIC_SWAP_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 28:
|
|
// ATOMIC_SWAP_I8
|
|
O << " ATOMIC_SWAP_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 29:
|
|
// BR_JTm, BR_JTr
|
|
O << " \n";
|
|
break;
|
|
case 30:
|
|
// BX_RET
|
|
O << "\tlr";
|
|
return;
|
|
break;
|
|
case 31:
|
|
// CDP, LDC2_OFFSET, LDC2_OPTION, LDC2_POST, LDC2_PRE, LDC_OFFSET, LDC_OP...
|
|
O << "\tp";
|
|
printNoHashImmediate(MI, 0);
|
|
break;
|
|
case 32:
|
|
// CDP2
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 2);
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 3);
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 4);
|
|
O << ", ";
|
|
printOperand(MI, 5);
|
|
return;
|
|
break;
|
|
case 33:
|
|
// FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VMLAD, V...
|
|
O << ".f64\t";
|
|
printOperand(MI, 0);
|
|
break;
|
|
case 34:
|
|
// FCONSTS, VABDfd, VABDfq, VABSS, VABSfd, VABSfd_sfp, VABSfq, VACGEd, VA...
|
|
O << ".f32\t";
|
|
printOperand(MI, 0);
|
|
break;
|
|
case 35:
|
|
// FMSTAT
|
|
O << "\tapsr_nzcv, fpscr";
|
|
return;
|
|
break;
|
|
case 36:
|
|
// Int_MemBarrierV6
|
|
O << ", c7, c10, 5";
|
|
return;
|
|
break;
|
|
case 37:
|
|
// Int_SyncBarrierV6
|
|
O << ", c7, c10, 4";
|
|
return;
|
|
break;
|
|
case 38:
|
|
// Int_eh_sjlj_setjmp
|
|
O << ", #+8] @ eh_setjmp begin\n\tadd\t";
|
|
printOperand(MI, 1);
|
|
O << ", pc, #8\n\tstr\t";
|
|
printOperand(MI, 1);
|
|
O << ", [";
|
|
printOperand(MI, 0);
|
|
O << ", #+4]\n\tmov\tr0, #0\n\tadd\tpc, pc, #0\n\tmov\tr0, #1 @ eh_setjmp end";
|
|
return;
|
|
break;
|
|
case 39:
|
|
// LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDCL_OFFSET, LDCL_O...
|
|
O << "l\tp";
|
|
printNoHashImmediate(MI, 0);
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 1);
|
|
break;
|
|
case 40:
|
|
// LDM, LDM_RET, STM, t2LDM, t2LDM_RET, t2MOVi, t2MOVr, t2MOVrx, t2MVNi, ...
|
|
printPredicateOperand(MI, 2);
|
|
break;
|
|
case 41:
|
|
// LEApcrel
|
|
O << "-(";
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELL";
|
|
PrintSpecial(MI, "uid");
|
|
O << "+8))\n";
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELL";
|
|
PrintSpecial(MI, "uid");
|
|
O << ":\n\tadd";
|
|
printPredicateOperand(MI, 2);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", pc, #";
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELV";
|
|
PrintSpecial(MI, "uid");
|
|
return;
|
|
break;
|
|
case 42:
|
|
// LEApcrelJT
|
|
O << '_';
|
|
printNoHashImmediate(MI, 2);
|
|
O << "-(";
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELL";
|
|
PrintSpecial(MI, "uid");
|
|
O << "+8))\n";
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELL";
|
|
PrintSpecial(MI, "uid");
|
|
O << ":\n\tadd";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", pc, #";
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELV";
|
|
PrintSpecial(MI, "uid");
|
|
return;
|
|
break;
|
|
case 43:
|
|
// MLA, MOVs, MVNs, SMLAL, SMULL, UMLAL, UMULL
|
|
printSBitModifierOperand(MI, 6);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 44:
|
|
// MOVi, MOVr, MOVrx, MVNi, MVNr
|
|
printSBitModifierOperand(MI, 4);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 45:
|
|
// MSR, MSRi, t2MSR
|
|
O << "\tcpsr, ";
|
|
break;
|
|
case 46:
|
|
// MSRsys, MSRsysi, t2MSRsys
|
|
O << "\tspsr, ";
|
|
break;
|
|
case 47:
|
|
// PICADD
|
|
O << ":\n\tadd";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", pc, ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 48:
|
|
// PICLDR
|
|
O << ":\n\tldr";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 49:
|
|
// PICLDRB
|
|
O << ":\n\tldrb";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 50:
|
|
// PICLDRH
|
|
O << ":\n\tldrh";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 51:
|
|
// PICLDRSB
|
|
O << ":\n\tldrsb";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 52:
|
|
// PICLDRSH
|
|
O << ":\n\tldrsh";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 53:
|
|
// PICSTR
|
|
O << ":\n\tstr";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 54:
|
|
// PICSTRB
|
|
O << ":\n\tstrb";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 55:
|
|
// PICSTRH
|
|
O << ":\n\tstrh";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 56:
|
|
// SRS, t2SRSDB, t2SRSIA
|
|
O << "\tsp, ";
|
|
break;
|
|
case 57:
|
|
// SRSW, t2SRSDBW, t2SRSIAW
|
|
O << "\tsp!, ";
|
|
break;
|
|
case 58:
|
|
// VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i...
|
|
O << ".s32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 59:
|
|
// VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i...
|
|
O << ".s16\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 60:
|
|
// VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8...
|
|
O << ".s8\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 61:
|
|
// VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i...
|
|
O << ".u32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 62:
|
|
// VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i...
|
|
O << ".u16\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 63:
|
|
// VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8...
|
|
O << ".u8\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 64:
|
|
// VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V...
|
|
O << ".i64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 65:
|
|
// VADDHNv4i16, VADDv2i32, VADDv4i32, VCEQv2i32, VCEQv4i32, VCEQzv2i32, V...
|
|
O << ".i32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 66:
|
|
// VADDHNv8i8, VADDv4i16, VADDv8i16, VCEQv4i16, VCEQv8i16, VCEQzv4i16, VC...
|
|
O << ".i16\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 67:
|
|
// VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCEQzv16i8, VCEQzv8i8, VCLZv...
|
|
O << ".i8\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 68:
|
|
// VCNTd, VCNTq, VDUP8d, VDUP8q, VDUPLN8d, VDUPLN8q, VEXTd8, VEXTq8, VLD1...
|
|
O << ".8\t";
|
|
break;
|
|
case 69:
|
|
// VCVTBHS, VCVTTHS
|
|
O << ".f16.f32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 70:
|
|
// VCVTBSH, VCVTTSH
|
|
O << ".f32.f16\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 71:
|
|
// VCVTDS
|
|
O << ".f64.f32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 72:
|
|
// VCVTSD
|
|
O << ".f32.f64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 73:
|
|
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIRS, VTOSI...
|
|
O << ".s32.f32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 74:
|
|
// VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIRS, VTOUI...
|
|
O << ".u32.f32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 75:
|
|
// VCVTs2fd, VCVTs2fd_sfp, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS, VSLTOS
|
|
O << ".f32.s32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 76:
|
|
// VCVTu2fd, VCVTu2fd_sfp, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS, VULTOS
|
|
O << ".f32.u32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 77:
|
|
// VDUP16d, VDUP16q, VDUPLN16d, VDUPLN16q, VEXTd16, VEXTq16, VLD1q16, VRE...
|
|
O << ".16\t";
|
|
break;
|
|
case 78:
|
|
// VDUP32d, VDUP32q, VDUPLN32d, VDUPLN32q, VDUPLNfd, VDUPLNfq, VDUPfd, VD...
|
|
O << ".32\t";
|
|
break;
|
|
case 79:
|
|
// VLD1d16, VLD1d16Q, VLD1d16T, VLD2LNd16, VLD2LNq16a, VLD2LNq16b, VLD2d1...
|
|
O << ".16\t{";
|
|
break;
|
|
case 80:
|
|
// VLD1d32, VLD1d32Q, VLD1d32T, VLD1df, VLD2LNd32, VLD2LNq32a, VLD2LNq32b...
|
|
O << ".32\t{";
|
|
break;
|
|
case 81:
|
|
// VLD1d64, VLD2d64, VLD3d64, VLD4d64, VST1d64, VST2d64, VST3d64, VST4d64
|
|
O << ".64\t{";
|
|
break;
|
|
case 82:
|
|
// VLD1d8, VLD1d8Q, VLD1d8T, VLD2LNd8, VLD2d8, VLD2d8D, VLD2q8, VLD3LNd8,...
|
|
O << ".8\t{";
|
|
break;
|
|
case 83:
|
|
// VLD1q64, VLDRD, VSLIv1i64, VSLIv2i64, VSRIv1i64, VSRIv2i64, VST1q64, V...
|
|
O << ".64\t";
|
|
break;
|
|
case 84:
|
|
// VMSR
|
|
O << "\tfpscr, ";
|
|
printOperand(MI, 0);
|
|
return;
|
|
break;
|
|
case 85:
|
|
// VMULLp, VMULpd, VMULpq
|
|
O << ".p8\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 86:
|
|
// VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
|
|
O << ".s64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 87:
|
|
// VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ...
|
|
O << ".u64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 88:
|
|
// VSHTOD
|
|
O << ".f64.s16\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 89:
|
|
// VSHTOS
|
|
O << ".f32.s16\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 90:
|
|
// VSITOD, VSLTOD
|
|
O << ".f64.s32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 91:
|
|
// VTOSHD
|
|
O << ".s16.f64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 92:
|
|
// VTOSHS
|
|
O << ".s16.f32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 93:
|
|
// VTOSIRD, VTOSIZD, VTOSLD
|
|
O << ".s32.f64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 94:
|
|
// VTOUHD
|
|
O << ".u16.f64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 95:
|
|
// VTOUHS
|
|
O << ".u16.f32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 96:
|
|
// VTOUIRD, VTOUIZD, VTOULD
|
|
O << ".u32.f64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 97:
|
|
// VUHTOD
|
|
O << ".f64.u16\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 98:
|
|
// VUHTOS
|
|
O << ".f32.u16\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 99:
|
|
// VUITOD, VULTOD
|
|
O << ".f64.u32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 100:
|
|
// t2ADCSrr, t2ADCSrs, t2ADCrr, t2ADCrs, t2ADDSri, t2ADDSrr, t2ADDSrs, t2...
|
|
O << ".w\t";
|
|
printOperand(MI, 0);
|
|
break;
|
|
case 101:
|
|
// t2BR_JT
|
|
O << "\n";
|
|
printJT2BlockOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 102:
|
|
// t2DMBish, t2DSBish
|
|
O << "\tish";
|
|
return;
|
|
break;
|
|
case 103:
|
|
// t2DMBishst, t2DSBishst
|
|
O << "\tishst";
|
|
return;
|
|
break;
|
|
case 104:
|
|
// t2DMBnsh, t2DSBnsh
|
|
O << "\tnsh";
|
|
return;
|
|
break;
|
|
case 105:
|
|
// t2DMBnshst, t2DSBnshst
|
|
O << "\tnshst";
|
|
return;
|
|
break;
|
|
case 106:
|
|
// t2DMBosh, t2DSBosh
|
|
O << "\tosh";
|
|
return;
|
|
break;
|
|
case 107:
|
|
// t2DMBoshst, t2DSBoshst
|
|
O << "\toshst";
|
|
return;
|
|
break;
|
|
case 108:
|
|
// t2DMBst, t2DSBst
|
|
O << "\tst";
|
|
return;
|
|
break;
|
|
case 109:
|
|
// t2NOP, t2SEV, t2WFE, t2WFI, t2YIELD
|
|
O << ".w";
|
|
return;
|
|
break;
|
|
case 110:
|
|
// t2PLDWpci, t2PLDpci, t2PLIpci
|
|
O << "\t[pc, ";
|
|
printOperand(MI, 1, "negzero");
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case 111:
|
|
// t2PLDWr, t2PLDWs, t2PLDr, t2PLDs, t2PLIr, t2PLIs, t2TBBgen, t2TBHgen
|
|
O << "\t[";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 112:
|
|
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
|
|
printPredicateOperand(MI, 4);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 113:
|
|
// tADDrPCi
|
|
O << ", pc, ";
|
|
printThumbS4ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 114:
|
|
// tBR_JTr
|
|
O << "\n\t.align\t2\n";
|
|
printJTBlockOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 115:
|
|
// tBfar
|
|
O << "\t@ far jump";
|
|
return;
|
|
break;
|
|
case 116:
|
|
// tLDRpci
|
|
O << ".n\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 117:
|
|
// tMOVi8, tMVN, tRSB
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
break;
|
|
case 118:
|
|
// tPICADD
|
|
O << ":\n\tadd\t";
|
|
printOperand(MI, 0);
|
|
O << ", pc";
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 2 encoded into 6 bits for 36 unique commands.
|
|
switch ((Bits >> 13) & 63) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MLA, MOVr, MOVrx, MVNr, PLDWi, PL...
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 1:
|
|
// ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri
|
|
printSOImmOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ADCrr, ADDrr, ANDrr, BICrr, EORrr, MCR2, MCRR2, MRC2, MRRC2, MUL, ORRr...
|
|
printOperand(MI, 2);
|
|
break;
|
|
case 3:
|
|
// ADDSri, ADDSrr, ADDSrs, BFC, BFI, BKPT, BXJ, Bcc, CLZ, CMNzri, CMNzrr,...
|
|
printOperand(MI, 0);
|
|
break;
|
|
case 4:
|
|
// BL_pred, BLr9_pred
|
|
printOperand(MI, 0, "call");
|
|
return;
|
|
break;
|
|
case 5:
|
|
// BR_JTm
|
|
printJTBlockOperand(MI, 3);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// BR_JTr
|
|
printJTBlockOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// CDP, FCONSTD, FCONSTS, LDC2L_OFFSET, LDC2L_PRE, LDCL_OFFSET, LDCL_PRE,...
|
|
O << ", ";
|
|
break;
|
|
case 8:
|
|
// LDC2L_OPTION, LDC2L_POST, LDCL_OPTION, LDCL_POST, STC2L_OPTION, STC2L_...
|
|
O << ", [";
|
|
printOperand(MI, 2);
|
|
O << "], ";
|
|
break;
|
|
case 9:
|
|
// LDC2_OFFSET, LDC2_OPTION, LDC2_POST, LDC2_PRE, LDC_OFFSET, LDC_OPTION,...
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 1);
|
|
break;
|
|
case 10:
|
|
// LDM, LDM_RET, STM, t2MOVrx, t2MVNi, tLDM, tSTM
|
|
O << "\t";
|
|
break;
|
|
case 11:
|
|
// MOVi, MVNi
|
|
printSOImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// MOVs, MVNs
|
|
printSORegOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// MSRi, MSRsysi
|
|
printSOImmOperand(MI, 0);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// VCMPEZD, VCMPEZS, VCMPZD, VCMPZS, tRSB
|
|
O << ", #0";
|
|
return;
|
|
break;
|
|
case 15:
|
|
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VC...
|
|
return;
|
|
break;
|
|
case 16:
|
|
// VLD1q16, VLD1q32, VLD1q64, VLD1q8, VLD1qf
|
|
printOperand(MI, 0, "dregpair");
|
|
O << ", ";
|
|
printAddrMode6Operand(MI, 1);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// VLDRQ, VSTRQ
|
|
printAddrMode4Operand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 0, "dregpair");
|
|
return;
|
|
break;
|
|
case 18:
|
|
// VMOVv16i8, VMOVv8i8
|
|
printHex8ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// VMOVv1i64, VMOVv2i64
|
|
printHex64ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 20:
|
|
// VMOVv2i32, VMOVv4i32
|
|
printHex32ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 21:
|
|
// VMOVv4i16, VMOVv8i16
|
|
printHex16ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// VST1d16, VST1d16Q, VST1d16T, VST1d32, VST1d32Q, VST1d32T, VST1d64, VST...
|
|
printOperand(MI, 4);
|
|
break;
|
|
case 23:
|
|
// VST1q16, VST1q32, VST1q64, VST1q8, VST1qf
|
|
printOperand(MI, 4, "dregpair");
|
|
O << ", ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case 24:
|
|
// VST3q16a, VST3q16b, VST3q32a, VST3q32b, VST3q8a, VST3q8b, VST4q16a, VS...
|
|
printOperand(MI, 5);
|
|
O << ", ";
|
|
printOperand(MI, 6);
|
|
O << ", ";
|
|
printOperand(MI, 7);
|
|
break;
|
|
case 25:
|
|
// t2LDM, t2LDM_RET, t2STM
|
|
printAddrMode4Operand(MI, 0, "wide");
|
|
O << "\t";
|
|
printAddrMode4Operand(MI, 0);
|
|
O << ", ";
|
|
printRegisterList(MI, 4);
|
|
return;
|
|
break;
|
|
case 26:
|
|
// t2LEApcrel, t2LEApcrelJT
|
|
O << ", #";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 27:
|
|
// t2MOVi, t2MOVr
|
|
O << ".w\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// t2PLDWi12, t2PLDi12, t2PLIi12
|
|
printT2AddrModeImm12Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// t2PLDWi8, t2PLDi8, t2PLIi8
|
|
printT2AddrModeImm8Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case 30:
|
|
// t2PLDWr, t2PLDr, t2PLIr, t2TBBgen
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case 31:
|
|
// t2PLDWs, t2PLDs, t2PLIs
|
|
O << ", lsl ";
|
|
printOperand(MI, 2);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case 32:
|
|
// t2TBHgen
|
|
O << ", lsl #1]";
|
|
return;
|
|
break;
|
|
case 33:
|
|
// tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tMUL, tORR, tR...
|
|
printOperand(MI, 3);
|
|
break;
|
|
case 34:
|
|
// tADDspi, tSUBspi, tSUBspi_
|
|
printThumbS4ImmOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 35:
|
|
// tPOP, tPOP_RET, tPUSH
|
|
printRegisterList(MI, 2);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
switch (MI->getOpcode()) {
|
|
case ARM::ADCSSri:
|
|
case ARM::ADCSSrr:
|
|
case ARM::ADCSSrs:
|
|
case ARM::BFC:
|
|
case ARM::CLZ:
|
|
case ARM::CMNzri:
|
|
case ARM::CMNzrr:
|
|
case ARM::CMNzrs:
|
|
case ARM::CMPri:
|
|
case ARM::CMPrr:
|
|
case ARM::CMPrs:
|
|
case ARM::CMPzri:
|
|
case ARM::CMPzrr:
|
|
case ARM::CMPzrs:
|
|
case ARM::LDC2_OFFSET:
|
|
case ARM::LDC_OFFSET:
|
|
case ARM::LDR:
|
|
case ARM::LDRB:
|
|
case ARM::LDRD:
|
|
case ARM::LDRH:
|
|
case ARM::LDRSB:
|
|
case ARM::LDRSH:
|
|
case ARM::LDRcp:
|
|
case ARM::MOVCCi:
|
|
case ARM::MOVCCr:
|
|
case ARM::MOVCCs:
|
|
case ARM::MOVTi16:
|
|
case ARM::MOVi16:
|
|
case ARM::MOVi2pieces:
|
|
case ARM::RBIT:
|
|
case ARM::REV:
|
|
case ARM::REV16:
|
|
case ARM::REVSH:
|
|
case ARM::RSCSri:
|
|
case ARM::RSCSrs:
|
|
case ARM::SBCSSri:
|
|
case ARM::SBCSSrr:
|
|
case ARM::SBCSSrs:
|
|
case ARM::STC2_OFFSET:
|
|
case ARM::STC_OFFSET:
|
|
case ARM::STR:
|
|
case ARM::STRB:
|
|
case ARM::STRD:
|
|
case ARM::STRH:
|
|
case ARM::SXTB16r:
|
|
case ARM::SXTBr:
|
|
case ARM::SXTHr:
|
|
case ARM::TEQri:
|
|
case ARM::TEQrr:
|
|
case ARM::TEQrs:
|
|
case ARM::TSTri:
|
|
case ARM::TSTrr:
|
|
case ARM::TSTrs:
|
|
case ARM::UXTB16r:
|
|
case ARM::UXTBr:
|
|
case ARM::UXTHr:
|
|
case ARM::VABALsv2i64:
|
|
case ARM::VABALsv4i32:
|
|
case ARM::VABALsv8i16:
|
|
case ARM::VABALuv2i64:
|
|
case ARM::VABALuv4i32:
|
|
case ARM::VABALuv8i16:
|
|
case ARM::VABAsv16i8:
|
|
case ARM::VABAsv2i32:
|
|
case ARM::VABAsv4i16:
|
|
case ARM::VABAsv4i32:
|
|
case ARM::VABAsv8i16:
|
|
case ARM::VABAsv8i8:
|
|
case ARM::VABAuv16i8:
|
|
case ARM::VABAuv2i32:
|
|
case ARM::VABAuv4i16:
|
|
case ARM::VABAuv4i32:
|
|
case ARM::VABAuv8i16:
|
|
case ARM::VABAuv8i8:
|
|
case ARM::VABDLsv2i64:
|
|
case ARM::VABDLsv4i32:
|
|
case ARM::VABDLsv8i16:
|
|
case ARM::VABDLuv2i64:
|
|
case ARM::VABDLuv4i32:
|
|
case ARM::VABDLuv8i16:
|
|
case ARM::VABDsv16i8:
|
|
case ARM::VABDsv2i32:
|
|
case ARM::VABDsv4i16:
|
|
case ARM::VABDsv4i32:
|
|
case ARM::VABDsv8i16:
|
|
case ARM::VABDsv8i8:
|
|
case ARM::VABDuv16i8:
|
|
case ARM::VABDuv2i32:
|
|
case ARM::VABDuv4i16:
|
|
case ARM::VABDuv4i32:
|
|
case ARM::VABDuv8i16:
|
|
case ARM::VABDuv8i8:
|
|
case ARM::VADDHNv2i32:
|
|
case ARM::VADDHNv4i16:
|
|
case ARM::VADDHNv8i8:
|
|
case ARM::VADDLsv2i64:
|
|
case ARM::VADDLsv4i32:
|
|
case ARM::VADDLsv8i16:
|
|
case ARM::VADDLuv2i64:
|
|
case ARM::VADDLuv4i32:
|
|
case ARM::VADDLuv8i16:
|
|
case ARM::VADDWsv2i64:
|
|
case ARM::VADDWsv4i32:
|
|
case ARM::VADDWsv8i16:
|
|
case ARM::VADDWuv2i64:
|
|
case ARM::VADDWuv4i32:
|
|
case ARM::VADDWuv8i16:
|
|
case ARM::VADDv16i8:
|
|
case ARM::VADDv1i64:
|
|
case ARM::VADDv2i32:
|
|
case ARM::VADDv2i64:
|
|
case ARM::VADDv4i16:
|
|
case ARM::VADDv4i32:
|
|
case ARM::VADDv8i16:
|
|
case ARM::VADDv8i8:
|
|
case ARM::VCEQv16i8:
|
|
case ARM::VCEQv2i32:
|
|
case ARM::VCEQv4i16:
|
|
case ARM::VCEQv4i32:
|
|
case ARM::VCEQv8i16:
|
|
case ARM::VCEQv8i8:
|
|
case ARM::VCGEsv16i8:
|
|
case ARM::VCGEsv2i32:
|
|
case ARM::VCGEsv4i16:
|
|
case ARM::VCGEsv4i32:
|
|
case ARM::VCGEsv8i16:
|
|
case ARM::VCGEsv8i8:
|
|
case ARM::VCGEuv16i8:
|
|
case ARM::VCGEuv2i32:
|
|
case ARM::VCGEuv4i16:
|
|
case ARM::VCGEuv4i32:
|
|
case ARM::VCGEuv8i16:
|
|
case ARM::VCGEuv8i8:
|
|
case ARM::VCGTsv16i8:
|
|
case ARM::VCGTsv2i32:
|
|
case ARM::VCGTsv4i16:
|
|
case ARM::VCGTsv4i32:
|
|
case ARM::VCGTsv8i16:
|
|
case ARM::VCGTsv8i8:
|
|
case ARM::VCGTuv16i8:
|
|
case ARM::VCGTuv2i32:
|
|
case ARM::VCGTuv4i16:
|
|
case ARM::VCGTuv4i32:
|
|
case ARM::VCGTuv8i16:
|
|
case ARM::VCGTuv8i8:
|
|
case ARM::VCNTd:
|
|
case ARM::VCNTq:
|
|
case ARM::VDUP16d:
|
|
case ARM::VDUP16q:
|
|
case ARM::VDUP32d:
|
|
case ARM::VDUP32q:
|
|
case ARM::VDUP8d:
|
|
case ARM::VDUP8q:
|
|
case ARM::VDUPfd:
|
|
case ARM::VDUPfdf:
|
|
case ARM::VDUPfq:
|
|
case ARM::VDUPfqf:
|
|
case ARM::VHADDsv16i8:
|
|
case ARM::VHADDsv2i32:
|
|
case ARM::VHADDsv4i16:
|
|
case ARM::VHADDsv4i32:
|
|
case ARM::VHADDsv8i16:
|
|
case ARM::VHADDsv8i8:
|
|
case ARM::VHADDuv16i8:
|
|
case ARM::VHADDuv2i32:
|
|
case ARM::VHADDuv4i16:
|
|
case ARM::VHADDuv4i32:
|
|
case ARM::VHADDuv8i16:
|
|
case ARM::VHADDuv8i8:
|
|
case ARM::VHSUBsv16i8:
|
|
case ARM::VHSUBsv2i32:
|
|
case ARM::VHSUBsv4i16:
|
|
case ARM::VHSUBsv4i32:
|
|
case ARM::VHSUBsv8i16:
|
|
case ARM::VHSUBsv8i8:
|
|
case ARM::VHSUBuv16i8:
|
|
case ARM::VHSUBuv2i32:
|
|
case ARM::VHSUBuv4i16:
|
|
case ARM::VHSUBuv4i32:
|
|
case ARM::VHSUBuv8i16:
|
|
case ARM::VHSUBuv8i8:
|
|
case ARM::VLDRD:
|
|
case ARM::VLDRS:
|
|
case ARM::VMAXsv16i8:
|
|
case ARM::VMAXsv2i32:
|
|
case ARM::VMAXsv4i16:
|
|
case ARM::VMAXsv4i32:
|
|
case ARM::VMAXsv8i16:
|
|
case ARM::VMAXsv8i8:
|
|
case ARM::VMAXuv16i8:
|
|
case ARM::VMAXuv2i32:
|
|
case ARM::VMAXuv4i16:
|
|
case ARM::VMAXuv4i32:
|
|
case ARM::VMAXuv8i16:
|
|
case ARM::VMAXuv8i8:
|
|
case ARM::VMINsv16i8:
|
|
case ARM::VMINsv2i32:
|
|
case ARM::VMINsv4i16:
|
|
case ARM::VMINsv4i32:
|
|
case ARM::VMINsv8i16:
|
|
case ARM::VMINsv8i8:
|
|
case ARM::VMINuv16i8:
|
|
case ARM::VMINuv2i32:
|
|
case ARM::VMINuv4i16:
|
|
case ARM::VMINuv4i32:
|
|
case ARM::VMINuv8i16:
|
|
case ARM::VMINuv8i8:
|
|
case ARM::VMLALsv2i64:
|
|
case ARM::VMLALsv4i32:
|
|
case ARM::VMLALsv8i16:
|
|
case ARM::VMLALuv2i64:
|
|
case ARM::VMLALuv4i32:
|
|
case ARM::VMLALuv8i16:
|
|
case ARM::VMLAv16i8:
|
|
case ARM::VMLAv2i32:
|
|
case ARM::VMLAv4i16:
|
|
case ARM::VMLAv4i32:
|
|
case ARM::VMLAv8i16:
|
|
case ARM::VMLAv8i8:
|
|
case ARM::VMLSLsv2i64:
|
|
case ARM::VMLSLsv4i32:
|
|
case ARM::VMLSLsv8i16:
|
|
case ARM::VMLSLuv2i64:
|
|
case ARM::VMLSLuv4i32:
|
|
case ARM::VMLSLuv8i16:
|
|
case ARM::VMLSv16i8:
|
|
case ARM::VMLSv2i32:
|
|
case ARM::VMLSv4i16:
|
|
case ARM::VMLSv4i32:
|
|
case ARM::VMLSv8i16:
|
|
case ARM::VMLSv8i8:
|
|
case ARM::VMOVDneon:
|
|
case ARM::VMOVQ:
|
|
case ARM::VMOVRS:
|
|
case ARM::VMOVSR:
|
|
case ARM::VMULLsv2i64:
|
|
case ARM::VMULLsv4i32:
|
|
case ARM::VMULLsv8i16:
|
|
case ARM::VMULLuv2i64:
|
|
case ARM::VMULLuv4i32:
|
|
case ARM::VMULLuv8i16:
|
|
case ARM::VMULv16i8:
|
|
case ARM::VMULv2i32:
|
|
case ARM::VMULv4i16:
|
|
case ARM::VMULv4i32:
|
|
case ARM::VMULv8i16:
|
|
case ARM::VMULv8i8:
|
|
case ARM::VMVNd:
|
|
case ARM::VMVNq:
|
|
case ARM::VPADDi16:
|
|
case ARM::VPADDi32:
|
|
case ARM::VPADDi8:
|
|
case ARM::VPMAXs16:
|
|
case ARM::VPMAXs32:
|
|
case ARM::VPMAXs8:
|
|
case ARM::VPMAXu16:
|
|
case ARM::VPMAXu32:
|
|
case ARM::VPMAXu8:
|
|
case ARM::VPMINs16:
|
|
case ARM::VPMINs32:
|
|
case ARM::VPMINs8:
|
|
case ARM::VPMINu16:
|
|
case ARM::VPMINu32:
|
|
case ARM::VPMINu8:
|
|
case ARM::VQADDsv16i8:
|
|
case ARM::VQADDsv1i64:
|
|
case ARM::VQADDsv2i32:
|
|
case ARM::VQADDsv2i64:
|
|
case ARM::VQADDsv4i16:
|
|
case ARM::VQADDsv4i32:
|
|
case ARM::VQADDsv8i16:
|
|
case ARM::VQADDsv8i8:
|
|
case ARM::VQADDuv16i8:
|
|
case ARM::VQADDuv1i64:
|
|
case ARM::VQADDuv2i32:
|
|
case ARM::VQADDuv2i64:
|
|
case ARM::VQADDuv4i16:
|
|
case ARM::VQADDuv4i32:
|
|
case ARM::VQADDuv8i16:
|
|
case ARM::VQADDuv8i8:
|
|
case ARM::VQDMLALv2i64:
|
|
case ARM::VQDMLALv4i32:
|
|
case ARM::VQDMLSLv2i64:
|
|
case ARM::VQDMLSLv4i32:
|
|
case ARM::VQDMULHv2i32:
|
|
case ARM::VQDMULHv4i16:
|
|
case ARM::VQDMULHv4i32:
|
|
case ARM::VQDMULHv8i16:
|
|
case ARM::VQDMULLv2i64:
|
|
case ARM::VQDMULLv4i32:
|
|
case ARM::VQRDMULHv2i32:
|
|
case ARM::VQRDMULHv4i16:
|
|
case ARM::VQRDMULHv4i32:
|
|
case ARM::VQRDMULHv8i16:
|
|
case ARM::VQRSHLsv16i8:
|
|
case ARM::VQRSHLsv1i64:
|
|
case ARM::VQRSHLsv2i32:
|
|
case ARM::VQRSHLsv2i64:
|
|
case ARM::VQRSHLsv4i16:
|
|
case ARM::VQRSHLsv4i32:
|
|
case ARM::VQRSHLsv8i16:
|
|
case ARM::VQRSHLsv8i8:
|
|
case ARM::VQRSHLuv16i8:
|
|
case ARM::VQRSHLuv1i64:
|
|
case ARM::VQRSHLuv2i32:
|
|
case ARM::VQRSHLuv2i64:
|
|
case ARM::VQRSHLuv4i16:
|
|
case ARM::VQRSHLuv4i32:
|
|
case ARM::VQRSHLuv8i16:
|
|
case ARM::VQRSHLuv8i8:
|
|
case ARM::VQRSHRNsv2i32:
|
|
case ARM::VQRSHRNsv4i16:
|
|
case ARM::VQRSHRNsv8i8:
|
|
case ARM::VQRSHRNuv2i32:
|
|
case ARM::VQRSHRNuv4i16:
|
|
case ARM::VQRSHRNuv8i8:
|
|
case ARM::VQRSHRUNv2i32:
|
|
case ARM::VQRSHRUNv4i16:
|
|
case ARM::VQRSHRUNv8i8:
|
|
case ARM::VQSHLsiv16i8:
|
|
case ARM::VQSHLsiv1i64:
|
|
case ARM::VQSHLsiv2i32:
|
|
case ARM::VQSHLsiv2i64:
|
|
case ARM::VQSHLsiv4i16:
|
|
case ARM::VQSHLsiv4i32:
|
|
case ARM::VQSHLsiv8i16:
|
|
case ARM::VQSHLsiv8i8:
|
|
case ARM::VQSHLsuv16i8:
|
|
case ARM::VQSHLsuv1i64:
|
|
case ARM::VQSHLsuv2i32:
|
|
case ARM::VQSHLsuv2i64:
|
|
case ARM::VQSHLsuv4i16:
|
|
case ARM::VQSHLsuv4i32:
|
|
case ARM::VQSHLsuv8i16:
|
|
case ARM::VQSHLsuv8i8:
|
|
case ARM::VQSHLsv16i8:
|
|
case ARM::VQSHLsv1i64:
|
|
case ARM::VQSHLsv2i32:
|
|
case ARM::VQSHLsv2i64:
|
|
case ARM::VQSHLsv4i16:
|
|
case ARM::VQSHLsv4i32:
|
|
case ARM::VQSHLsv8i16:
|
|
case ARM::VQSHLsv8i8:
|
|
case ARM::VQSHLuiv16i8:
|
|
case ARM::VQSHLuiv1i64:
|
|
case ARM::VQSHLuiv2i32:
|
|
case ARM::VQSHLuiv2i64:
|
|
case ARM::VQSHLuiv4i16:
|
|
case ARM::VQSHLuiv4i32:
|
|
case ARM::VQSHLuiv8i16:
|
|
case ARM::VQSHLuiv8i8:
|
|
case ARM::VQSHLuv16i8:
|
|
case ARM::VQSHLuv1i64:
|
|
case ARM::VQSHLuv2i32:
|
|
case ARM::VQSHLuv2i64:
|
|
case ARM::VQSHLuv4i16:
|
|
case ARM::VQSHLuv4i32:
|
|
case ARM::VQSHLuv8i16:
|
|
case ARM::VQSHLuv8i8:
|
|
case ARM::VQSHRNsv2i32:
|
|
case ARM::VQSHRNsv4i16:
|
|
case ARM::VQSHRNsv8i8:
|
|
case ARM::VQSHRNuv2i32:
|
|
case ARM::VQSHRNuv4i16:
|
|
case ARM::VQSHRNuv8i8:
|
|
case ARM::VQSHRUNv2i32:
|
|
case ARM::VQSHRUNv4i16:
|
|
case ARM::VQSHRUNv8i8:
|
|
case ARM::VQSUBsv16i8:
|
|
case ARM::VQSUBsv1i64:
|
|
case ARM::VQSUBsv2i32:
|
|
case ARM::VQSUBsv2i64:
|
|
case ARM::VQSUBsv4i16:
|
|
case ARM::VQSUBsv4i32:
|
|
case ARM::VQSUBsv8i16:
|
|
case ARM::VQSUBsv8i8:
|
|
case ARM::VQSUBuv16i8:
|
|
case ARM::VQSUBuv1i64:
|
|
case ARM::VQSUBuv2i32:
|
|
case ARM::VQSUBuv2i64:
|
|
case ARM::VQSUBuv4i16:
|
|
case ARM::VQSUBuv4i32:
|
|
case ARM::VQSUBuv8i16:
|
|
case ARM::VQSUBuv8i8:
|
|
case ARM::VRADDHNv2i32:
|
|
case ARM::VRADDHNv4i16:
|
|
case ARM::VRADDHNv8i8:
|
|
case ARM::VREV16d8:
|
|
case ARM::VREV16q8:
|
|
case ARM::VREV32d16:
|
|
case ARM::VREV32d8:
|
|
case ARM::VREV32q16:
|
|
case ARM::VREV32q8:
|
|
case ARM::VREV64d16:
|
|
case ARM::VREV64d32:
|
|
case ARM::VREV64d8:
|
|
case ARM::VREV64df:
|
|
case ARM::VREV64q16:
|
|
case ARM::VREV64q32:
|
|
case ARM::VREV64q8:
|
|
case ARM::VREV64qf:
|
|
case ARM::VRHADDsv16i8:
|
|
case ARM::VRHADDsv2i32:
|
|
case ARM::VRHADDsv4i16:
|
|
case ARM::VRHADDsv4i32:
|
|
case ARM::VRHADDsv8i16:
|
|
case ARM::VRHADDsv8i8:
|
|
case ARM::VRHADDuv16i8:
|
|
case ARM::VRHADDuv2i32:
|
|
case ARM::VRHADDuv4i16:
|
|
case ARM::VRHADDuv4i32:
|
|
case ARM::VRHADDuv8i16:
|
|
case ARM::VRHADDuv8i8:
|
|
case ARM::VRSHLsv16i8:
|
|
case ARM::VRSHLsv1i64:
|
|
case ARM::VRSHLsv2i32:
|
|
case ARM::VRSHLsv2i64:
|
|
case ARM::VRSHLsv4i16:
|
|
case ARM::VRSHLsv4i32:
|
|
case ARM::VRSHLsv8i16:
|
|
case ARM::VRSHLsv8i8:
|
|
case ARM::VRSHLuv16i8:
|
|
case ARM::VRSHLuv1i64:
|
|
case ARM::VRSHLuv2i32:
|
|
case ARM::VRSHLuv2i64:
|
|
case ARM::VRSHLuv4i16:
|
|
case ARM::VRSHLuv4i32:
|
|
case ARM::VRSHLuv8i16:
|
|
case ARM::VRSHLuv8i8:
|
|
case ARM::VRSHRNv2i32:
|
|
case ARM::VRSHRNv4i16:
|
|
case ARM::VRSHRNv8i8:
|
|
case ARM::VRSHRsv16i8:
|
|
case ARM::VRSHRsv1i64:
|
|
case ARM::VRSHRsv2i32:
|
|
case ARM::VRSHRsv2i64:
|
|
case ARM::VRSHRsv4i16:
|
|
case ARM::VRSHRsv4i32:
|
|
case ARM::VRSHRsv8i16:
|
|
case ARM::VRSHRsv8i8:
|
|
case ARM::VRSHRuv16i8:
|
|
case ARM::VRSHRuv1i64:
|
|
case ARM::VRSHRuv2i32:
|
|
case ARM::VRSHRuv2i64:
|
|
case ARM::VRSHRuv4i16:
|
|
case ARM::VRSHRuv4i32:
|
|
case ARM::VRSHRuv8i16:
|
|
case ARM::VRSHRuv8i8:
|
|
case ARM::VRSRAsv16i8:
|
|
case ARM::VRSRAsv1i64:
|
|
case ARM::VRSRAsv2i32:
|
|
case ARM::VRSRAsv2i64:
|
|
case ARM::VRSRAsv4i16:
|
|
case ARM::VRSRAsv4i32:
|
|
case ARM::VRSRAsv8i16:
|
|
case ARM::VRSRAsv8i8:
|
|
case ARM::VRSRAuv16i8:
|
|
case ARM::VRSRAuv1i64:
|
|
case ARM::VRSRAuv2i32:
|
|
case ARM::VRSRAuv2i64:
|
|
case ARM::VRSRAuv4i16:
|
|
case ARM::VRSRAuv4i32:
|
|
case ARM::VRSRAuv8i16:
|
|
case ARM::VRSRAuv8i8:
|
|
case ARM::VRSUBHNv2i32:
|
|
case ARM::VRSUBHNv4i16:
|
|
case ARM::VRSUBHNv8i8:
|
|
case ARM::VSHLLi16:
|
|
case ARM::VSHLLi32:
|
|
case ARM::VSHLLi8:
|
|
case ARM::VSHLLsv2i64:
|
|
case ARM::VSHLLsv4i32:
|
|
case ARM::VSHLLsv8i16:
|
|
case ARM::VSHLLuv2i64:
|
|
case ARM::VSHLLuv4i32:
|
|
case ARM::VSHLLuv8i16:
|
|
case ARM::VSHLiv16i8:
|
|
case ARM::VSHLiv1i64:
|
|
case ARM::VSHLiv2i32:
|
|
case ARM::VSHLiv2i64:
|
|
case ARM::VSHLiv4i16:
|
|
case ARM::VSHLiv4i32:
|
|
case ARM::VSHLiv8i16:
|
|
case ARM::VSHLiv8i8:
|
|
case ARM::VSHLsv16i8:
|
|
case ARM::VSHLsv1i64:
|
|
case ARM::VSHLsv2i32:
|
|
case ARM::VSHLsv2i64:
|
|
case ARM::VSHLsv4i16:
|
|
case ARM::VSHLsv4i32:
|
|
case ARM::VSHLsv8i16:
|
|
case ARM::VSHLsv8i8:
|
|
case ARM::VSHLuv16i8:
|
|
case ARM::VSHLuv1i64:
|
|
case ARM::VSHLuv2i32:
|
|
case ARM::VSHLuv2i64:
|
|
case ARM::VSHLuv4i16:
|
|
case ARM::VSHLuv4i32:
|
|
case ARM::VSHLuv8i16:
|
|
case ARM::VSHLuv8i8:
|
|
case ARM::VSHRNv2i32:
|
|
case ARM::VSHRNv4i16:
|
|
case ARM::VSHRNv8i8:
|
|
case ARM::VSHRsv16i8:
|
|
case ARM::VSHRsv1i64:
|
|
case ARM::VSHRsv2i32:
|
|
case ARM::VSHRsv2i64:
|
|
case ARM::VSHRsv4i16:
|
|
case ARM::VSHRsv4i32:
|
|
case ARM::VSHRsv8i16:
|
|
case ARM::VSHRsv8i8:
|
|
case ARM::VSHRuv16i8:
|
|
case ARM::VSHRuv1i64:
|
|
case ARM::VSHRuv2i32:
|
|
case ARM::VSHRuv2i64:
|
|
case ARM::VSHRuv4i16:
|
|
case ARM::VSHRuv4i32:
|
|
case ARM::VSHRuv8i16:
|
|
case ARM::VSHRuv8i8:
|
|
case ARM::VSRAsv16i8:
|
|
case ARM::VSRAsv1i64:
|
|
case ARM::VSRAsv2i32:
|
|
case ARM::VSRAsv2i64:
|
|
case ARM::VSRAsv4i16:
|
|
case ARM::VSRAsv4i32:
|
|
case ARM::VSRAsv8i16:
|
|
case ARM::VSRAsv8i8:
|
|
case ARM::VSRAuv16i8:
|
|
case ARM::VSRAuv1i64:
|
|
case ARM::VSRAuv2i32:
|
|
case ARM::VSRAuv2i64:
|
|
case ARM::VSRAuv4i16:
|
|
case ARM::VSRAuv4i32:
|
|
case ARM::VSRAuv8i16:
|
|
case ARM::VSRAuv8i8:
|
|
case ARM::VSTRD:
|
|
case ARM::VSTRS:
|
|
case ARM::VSUBHNv2i32:
|
|
case ARM::VSUBHNv4i16:
|
|
case ARM::VSUBHNv8i8:
|
|
case ARM::VSUBLsv2i64:
|
|
case ARM::VSUBLsv4i32:
|
|
case ARM::VSUBLsv8i16:
|
|
case ARM::VSUBLuv2i64:
|
|
case ARM::VSUBLuv4i32:
|
|
case ARM::VSUBLuv8i16:
|
|
case ARM::VSUBWsv2i64:
|
|
case ARM::VSUBWsv4i32:
|
|
case ARM::VSUBWsv8i16:
|
|
case ARM::VSUBWuv2i64:
|
|
case ARM::VSUBWuv4i32:
|
|
case ARM::VSUBWuv8i16:
|
|
case ARM::VSUBv16i8:
|
|
case ARM::VSUBv1i64:
|
|
case ARM::VSUBv2i32:
|
|
case ARM::VSUBv2i64:
|
|
case ARM::VSUBv4i16:
|
|
case ARM::VSUBv4i32:
|
|
case ARM::VSUBv8i16:
|
|
case ARM::VSUBv8i8:
|
|
case ARM::VSWPd:
|
|
case ARM::VSWPq:
|
|
case ARM::VTRNd16:
|
|
case ARM::VTRNd32:
|
|
case ARM::VTRNd8:
|
|
case ARM::VTRNq16:
|
|
case ARM::VTRNq32:
|
|
case ARM::VTRNq8:
|
|
case ARM::VUZPd16:
|
|
case ARM::VUZPd32:
|
|
case ARM::VUZPd8:
|
|
case ARM::VUZPq16:
|
|
case ARM::VUZPq32:
|
|
case ARM::VUZPq8:
|
|
case ARM::VZIPd16:
|
|
case ARM::VZIPd32:
|
|
case ARM::VZIPd8:
|
|
case ARM::VZIPq16:
|
|
case ARM::VZIPq32:
|
|
case ARM::VZIPq8:
|
|
case ARM::t2BFC:
|
|
case ARM::t2CLZ:
|
|
case ARM::t2LDRBT:
|
|
case ARM::t2LDRBi8:
|
|
case ARM::t2LDRDi8:
|
|
case ARM::t2LDRDpci:
|
|
case ARM::t2LDRHT:
|
|
case ARM::t2LDRHi8:
|
|
case ARM::t2LDRSBT:
|
|
case ARM::t2LDRSBi8:
|
|
case ARM::t2LDRSHT:
|
|
case ARM::t2LDRSHi8:
|
|
case ARM::t2LDRT:
|
|
case ARM::t2LDRi8:
|
|
case ARM::t2MOVTi16:
|
|
case ARM::t2MOVi16:
|
|
case ARM::t2RBIT:
|
|
case ARM::t2STRBT:
|
|
case ARM::t2STRBi8:
|
|
case ARM::t2STRDi8:
|
|
case ARM::t2STRHT:
|
|
case ARM::t2STRHi8:
|
|
case ARM::t2STRT:
|
|
case ARM::t2STRi8:
|
|
case ARM::t2SUBrSPi12_:
|
|
case ARM::t2SUBrSPi_:
|
|
case ARM::t2SUBrSPs_:
|
|
case ARM::t2SXTB16r:
|
|
case ARM::t2UXTB16r:
|
|
case ARM::tADDhirr:
|
|
case ARM::tADDi3:
|
|
case ARM::tADDrSPi:
|
|
case ARM::tADDrr:
|
|
case ARM::tASRri:
|
|
case ARM::tCMNz:
|
|
case ARM::tCMPhir:
|
|
case ARM::tCMPi8:
|
|
case ARM::tCMPr:
|
|
case ARM::tCMPzhir:
|
|
case ARM::tCMPzi8:
|
|
case ARM::tCMPzr:
|
|
case ARM::tLDR:
|
|
case ARM::tLDRB:
|
|
case ARM::tLDRBi:
|
|
case ARM::tLDRH:
|
|
case ARM::tLDRHi:
|
|
case ARM::tLDRSB:
|
|
case ARM::tLDRSH:
|
|
case ARM::tLDRcp:
|
|
case ARM::tLDRi:
|
|
case ARM::tLDRspi:
|
|
case ARM::tLSLri:
|
|
case ARM::tLSRri:
|
|
case ARM::tMOVCCi:
|
|
case ARM::tMOVCCr:
|
|
case ARM::tMUL:
|
|
case ARM::tREV:
|
|
case ARM::tREV16:
|
|
case ARM::tREVSH:
|
|
case ARM::tRestore:
|
|
case ARM::tSTR:
|
|
case ARM::tSTRB:
|
|
case ARM::tSTRBi:
|
|
case ARM::tSTRH:
|
|
case ARM::tSTRHi:
|
|
case ARM::tSTRi:
|
|
case ARM::tSTRspi:
|
|
case ARM::tSUBi3:
|
|
case ARM::tSUBrr:
|
|
case ARM::tSXTB:
|
|
case ARM::tSXTH:
|
|
case ARM::tSpill:
|
|
case ARM::tTST:
|
|
case ARM::tUXTB:
|
|
case ARM::tUXTH:
|
|
O << ", ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::ADCSSri:
|
|
case ARM::MOVCCi:
|
|
case ARM::RSCSri:
|
|
case ARM::SBCSSri: printSOImmOperand(MI, 2); break;
|
|
case ARM::ADCSSrr:
|
|
case ARM::MOVCCr:
|
|
case ARM::MOVTi16:
|
|
case ARM::SBCSSrr:
|
|
case ARM::VABDLsv2i64:
|
|
case ARM::VABDLsv4i32:
|
|
case ARM::VABDLsv8i16:
|
|
case ARM::VABDLuv2i64:
|
|
case ARM::VABDLuv4i32:
|
|
case ARM::VABDLuv8i16:
|
|
case ARM::VABDsv16i8:
|
|
case ARM::VABDsv2i32:
|
|
case ARM::VABDsv4i16:
|
|
case ARM::VABDsv4i32:
|
|
case ARM::VABDsv8i16:
|
|
case ARM::VABDsv8i8:
|
|
case ARM::VABDuv16i8:
|
|
case ARM::VABDuv2i32:
|
|
case ARM::VABDuv4i16:
|
|
case ARM::VABDuv4i32:
|
|
case ARM::VABDuv8i16:
|
|
case ARM::VABDuv8i8:
|
|
case ARM::VADDHNv2i32:
|
|
case ARM::VADDHNv4i16:
|
|
case ARM::VADDHNv8i8:
|
|
case ARM::VADDLsv2i64:
|
|
case ARM::VADDLsv4i32:
|
|
case ARM::VADDLsv8i16:
|
|
case ARM::VADDLuv2i64:
|
|
case ARM::VADDLuv4i32:
|
|
case ARM::VADDLuv8i16:
|
|
case ARM::VADDWsv2i64:
|
|
case ARM::VADDWsv4i32:
|
|
case ARM::VADDWsv8i16:
|
|
case ARM::VADDWuv2i64:
|
|
case ARM::VADDWuv4i32:
|
|
case ARM::VADDWuv8i16:
|
|
case ARM::VADDv16i8:
|
|
case ARM::VADDv1i64:
|
|
case ARM::VADDv2i32:
|
|
case ARM::VADDv2i64:
|
|
case ARM::VADDv4i16:
|
|
case ARM::VADDv4i32:
|
|
case ARM::VADDv8i16:
|
|
case ARM::VADDv8i8:
|
|
case ARM::VCEQv16i8:
|
|
case ARM::VCEQv2i32:
|
|
case ARM::VCEQv4i16:
|
|
case ARM::VCEQv4i32:
|
|
case ARM::VCEQv8i16:
|
|
case ARM::VCEQv8i8:
|
|
case ARM::VCGEsv16i8:
|
|
case ARM::VCGEsv2i32:
|
|
case ARM::VCGEsv4i16:
|
|
case ARM::VCGEsv4i32:
|
|
case ARM::VCGEsv8i16:
|
|
case ARM::VCGEsv8i8:
|
|
case ARM::VCGEuv16i8:
|
|
case ARM::VCGEuv2i32:
|
|
case ARM::VCGEuv4i16:
|
|
case ARM::VCGEuv4i32:
|
|
case ARM::VCGEuv8i16:
|
|
case ARM::VCGEuv8i8:
|
|
case ARM::VCGTsv16i8:
|
|
case ARM::VCGTsv2i32:
|
|
case ARM::VCGTsv4i16:
|
|
case ARM::VCGTsv4i32:
|
|
case ARM::VCGTsv8i16:
|
|
case ARM::VCGTsv8i8:
|
|
case ARM::VCGTuv16i8:
|
|
case ARM::VCGTuv2i32:
|
|
case ARM::VCGTuv4i16:
|
|
case ARM::VCGTuv4i32:
|
|
case ARM::VCGTuv8i16:
|
|
case ARM::VCGTuv8i8:
|
|
case ARM::VHADDsv16i8:
|
|
case ARM::VHADDsv2i32:
|
|
case ARM::VHADDsv4i16:
|
|
case ARM::VHADDsv4i32:
|
|
case ARM::VHADDsv8i16:
|
|
case ARM::VHADDsv8i8:
|
|
case ARM::VHADDuv16i8:
|
|
case ARM::VHADDuv2i32:
|
|
case ARM::VHADDuv4i16:
|
|
case ARM::VHADDuv4i32:
|
|
case ARM::VHADDuv8i16:
|
|
case ARM::VHADDuv8i8:
|
|
case ARM::VHSUBsv16i8:
|
|
case ARM::VHSUBsv2i32:
|
|
case ARM::VHSUBsv4i16:
|
|
case ARM::VHSUBsv4i32:
|
|
case ARM::VHSUBsv8i16:
|
|
case ARM::VHSUBsv8i8:
|
|
case ARM::VHSUBuv16i8:
|
|
case ARM::VHSUBuv2i32:
|
|
case ARM::VHSUBuv4i16:
|
|
case ARM::VHSUBuv4i32:
|
|
case ARM::VHSUBuv8i16:
|
|
case ARM::VHSUBuv8i8:
|
|
case ARM::VMAXsv16i8:
|
|
case ARM::VMAXsv2i32:
|
|
case ARM::VMAXsv4i16:
|
|
case ARM::VMAXsv4i32:
|
|
case ARM::VMAXsv8i16:
|
|
case ARM::VMAXsv8i8:
|
|
case ARM::VMAXuv16i8:
|
|
case ARM::VMAXuv2i32:
|
|
case ARM::VMAXuv4i16:
|
|
case ARM::VMAXuv4i32:
|
|
case ARM::VMAXuv8i16:
|
|
case ARM::VMAXuv8i8:
|
|
case ARM::VMINsv16i8:
|
|
case ARM::VMINsv2i32:
|
|
case ARM::VMINsv4i16:
|
|
case ARM::VMINsv4i32:
|
|
case ARM::VMINsv8i16:
|
|
case ARM::VMINsv8i8:
|
|
case ARM::VMINuv16i8:
|
|
case ARM::VMINuv2i32:
|
|
case ARM::VMINuv4i16:
|
|
case ARM::VMINuv4i32:
|
|
case ARM::VMINuv8i16:
|
|
case ARM::VMINuv8i8:
|
|
case ARM::VMULLsv2i64:
|
|
case ARM::VMULLsv4i32:
|
|
case ARM::VMULLsv8i16:
|
|
case ARM::VMULLuv2i64:
|
|
case ARM::VMULLuv4i32:
|
|
case ARM::VMULLuv8i16:
|
|
case ARM::VMULv16i8:
|
|
case ARM::VMULv2i32:
|
|
case ARM::VMULv4i16:
|
|
case ARM::VMULv4i32:
|
|
case ARM::VMULv8i16:
|
|
case ARM::VMULv8i8:
|
|
case ARM::VPADDi16:
|
|
case ARM::VPADDi32:
|
|
case ARM::VPADDi8:
|
|
case ARM::VPMAXs16:
|
|
case ARM::VPMAXs32:
|
|
case ARM::VPMAXs8:
|
|
case ARM::VPMAXu16:
|
|
case ARM::VPMAXu32:
|
|
case ARM::VPMAXu8:
|
|
case ARM::VPMINs16:
|
|
case ARM::VPMINs32:
|
|
case ARM::VPMINs8:
|
|
case ARM::VPMINu16:
|
|
case ARM::VPMINu32:
|
|
case ARM::VPMINu8:
|
|
case ARM::VQADDsv16i8:
|
|
case ARM::VQADDsv1i64:
|
|
case ARM::VQADDsv2i32:
|
|
case ARM::VQADDsv2i64:
|
|
case ARM::VQADDsv4i16:
|
|
case ARM::VQADDsv4i32:
|
|
case ARM::VQADDsv8i16:
|
|
case ARM::VQADDsv8i8:
|
|
case ARM::VQADDuv16i8:
|
|
case ARM::VQADDuv1i64:
|
|
case ARM::VQADDuv2i32:
|
|
case ARM::VQADDuv2i64:
|
|
case ARM::VQADDuv4i16:
|
|
case ARM::VQADDuv4i32:
|
|
case ARM::VQADDuv8i16:
|
|
case ARM::VQADDuv8i8:
|
|
case ARM::VQDMULHv2i32:
|
|
case ARM::VQDMULHv4i16:
|
|
case ARM::VQDMULHv4i32:
|
|
case ARM::VQDMULHv8i16:
|
|
case ARM::VQDMULLv2i64:
|
|
case ARM::VQDMULLv4i32:
|
|
case ARM::VQRDMULHv2i32:
|
|
case ARM::VQRDMULHv4i16:
|
|
case ARM::VQRDMULHv4i32:
|
|
case ARM::VQRDMULHv8i16:
|
|
case ARM::VQRSHLsv16i8:
|
|
case ARM::VQRSHLsv1i64:
|
|
case ARM::VQRSHLsv2i32:
|
|
case ARM::VQRSHLsv2i64:
|
|
case ARM::VQRSHLsv4i16:
|
|
case ARM::VQRSHLsv4i32:
|
|
case ARM::VQRSHLsv8i16:
|
|
case ARM::VQRSHLsv8i8:
|
|
case ARM::VQRSHLuv16i8:
|
|
case ARM::VQRSHLuv1i64:
|
|
case ARM::VQRSHLuv2i32:
|
|
case ARM::VQRSHLuv2i64:
|
|
case ARM::VQRSHLuv4i16:
|
|
case ARM::VQRSHLuv4i32:
|
|
case ARM::VQRSHLuv8i16:
|
|
case ARM::VQRSHLuv8i8:
|
|
case ARM::VQRSHRNsv2i32:
|
|
case ARM::VQRSHRNsv4i16:
|
|
case ARM::VQRSHRNsv8i8:
|
|
case ARM::VQRSHRNuv2i32:
|
|
case ARM::VQRSHRNuv4i16:
|
|
case ARM::VQRSHRNuv8i8:
|
|
case ARM::VQRSHRUNv2i32:
|
|
case ARM::VQRSHRUNv4i16:
|
|
case ARM::VQRSHRUNv8i8:
|
|
case ARM::VQSHLsiv16i8:
|
|
case ARM::VQSHLsiv1i64:
|
|
case ARM::VQSHLsiv2i32:
|
|
case ARM::VQSHLsiv2i64:
|
|
case ARM::VQSHLsiv4i16:
|
|
case ARM::VQSHLsiv4i32:
|
|
case ARM::VQSHLsiv8i16:
|
|
case ARM::VQSHLsiv8i8:
|
|
case ARM::VQSHLsuv16i8:
|
|
case ARM::VQSHLsuv1i64:
|
|
case ARM::VQSHLsuv2i32:
|
|
case ARM::VQSHLsuv2i64:
|
|
case ARM::VQSHLsuv4i16:
|
|
case ARM::VQSHLsuv4i32:
|
|
case ARM::VQSHLsuv8i16:
|
|
case ARM::VQSHLsuv8i8:
|
|
case ARM::VQSHLsv16i8:
|
|
case ARM::VQSHLsv1i64:
|
|
case ARM::VQSHLsv2i32:
|
|
case ARM::VQSHLsv2i64:
|
|
case ARM::VQSHLsv4i16:
|
|
case ARM::VQSHLsv4i32:
|
|
case ARM::VQSHLsv8i16:
|
|
case ARM::VQSHLsv8i8:
|
|
case ARM::VQSHLuiv16i8:
|
|
case ARM::VQSHLuiv1i64:
|
|
case ARM::VQSHLuiv2i32:
|
|
case ARM::VQSHLuiv2i64:
|
|
case ARM::VQSHLuiv4i16:
|
|
case ARM::VQSHLuiv4i32:
|
|
case ARM::VQSHLuiv8i16:
|
|
case ARM::VQSHLuiv8i8:
|
|
case ARM::VQSHLuv16i8:
|
|
case ARM::VQSHLuv1i64:
|
|
case ARM::VQSHLuv2i32:
|
|
case ARM::VQSHLuv2i64:
|
|
case ARM::VQSHLuv4i16:
|
|
case ARM::VQSHLuv4i32:
|
|
case ARM::VQSHLuv8i16:
|
|
case ARM::VQSHLuv8i8:
|
|
case ARM::VQSHRNsv2i32:
|
|
case ARM::VQSHRNsv4i16:
|
|
case ARM::VQSHRNsv8i8:
|
|
case ARM::VQSHRNuv2i32:
|
|
case ARM::VQSHRNuv4i16:
|
|
case ARM::VQSHRNuv8i8:
|
|
case ARM::VQSHRUNv2i32:
|
|
case ARM::VQSHRUNv4i16:
|
|
case ARM::VQSHRUNv8i8:
|
|
case ARM::VQSUBsv16i8:
|
|
case ARM::VQSUBsv1i64:
|
|
case ARM::VQSUBsv2i32:
|
|
case ARM::VQSUBsv2i64:
|
|
case ARM::VQSUBsv4i16:
|
|
case ARM::VQSUBsv4i32:
|
|
case ARM::VQSUBsv8i16:
|
|
case ARM::VQSUBsv8i8:
|
|
case ARM::VQSUBuv16i8:
|
|
case ARM::VQSUBuv1i64:
|
|
case ARM::VQSUBuv2i32:
|
|
case ARM::VQSUBuv2i64:
|
|
case ARM::VQSUBuv4i16:
|
|
case ARM::VQSUBuv4i32:
|
|
case ARM::VQSUBuv8i16:
|
|
case ARM::VQSUBuv8i8:
|
|
case ARM::VRADDHNv2i32:
|
|
case ARM::VRADDHNv4i16:
|
|
case ARM::VRADDHNv8i8:
|
|
case ARM::VRHADDsv16i8:
|
|
case ARM::VRHADDsv2i32:
|
|
case ARM::VRHADDsv4i16:
|
|
case ARM::VRHADDsv4i32:
|
|
case ARM::VRHADDsv8i16:
|
|
case ARM::VRHADDsv8i8:
|
|
case ARM::VRHADDuv16i8:
|
|
case ARM::VRHADDuv2i32:
|
|
case ARM::VRHADDuv4i16:
|
|
case ARM::VRHADDuv4i32:
|
|
case ARM::VRHADDuv8i16:
|
|
case ARM::VRHADDuv8i8:
|
|
case ARM::VRSHLsv16i8:
|
|
case ARM::VRSHLsv1i64:
|
|
case ARM::VRSHLsv2i32:
|
|
case ARM::VRSHLsv2i64:
|
|
case ARM::VRSHLsv4i16:
|
|
case ARM::VRSHLsv4i32:
|
|
case ARM::VRSHLsv8i16:
|
|
case ARM::VRSHLsv8i8:
|
|
case ARM::VRSHLuv16i8:
|
|
case ARM::VRSHLuv1i64:
|
|
case ARM::VRSHLuv2i32:
|
|
case ARM::VRSHLuv2i64:
|
|
case ARM::VRSHLuv4i16:
|
|
case ARM::VRSHLuv4i32:
|
|
case ARM::VRSHLuv8i16:
|
|
case ARM::VRSHLuv8i8:
|
|
case ARM::VRSHRNv2i32:
|
|
case ARM::VRSHRNv4i16:
|
|
case ARM::VRSHRNv8i8:
|
|
case ARM::VRSHRsv16i8:
|
|
case ARM::VRSHRsv1i64:
|
|
case ARM::VRSHRsv2i32:
|
|
case ARM::VRSHRsv2i64:
|
|
case ARM::VRSHRsv4i16:
|
|
case ARM::VRSHRsv4i32:
|
|
case ARM::VRSHRsv8i16:
|
|
case ARM::VRSHRsv8i8:
|
|
case ARM::VRSHRuv16i8:
|
|
case ARM::VRSHRuv1i64:
|
|
case ARM::VRSHRuv2i32:
|
|
case ARM::VRSHRuv2i64:
|
|
case ARM::VRSHRuv4i16:
|
|
case ARM::VRSHRuv4i32:
|
|
case ARM::VRSHRuv8i16:
|
|
case ARM::VRSHRuv8i8:
|
|
case ARM::VRSUBHNv2i32:
|
|
case ARM::VRSUBHNv4i16:
|
|
case ARM::VRSUBHNv8i8:
|
|
case ARM::VSHLLi16:
|
|
case ARM::VSHLLi32:
|
|
case ARM::VSHLLi8:
|
|
case ARM::VSHLLsv2i64:
|
|
case ARM::VSHLLsv4i32:
|
|
case ARM::VSHLLsv8i16:
|
|
case ARM::VSHLLuv2i64:
|
|
case ARM::VSHLLuv4i32:
|
|
case ARM::VSHLLuv8i16:
|
|
case ARM::VSHLiv16i8:
|
|
case ARM::VSHLiv1i64:
|
|
case ARM::VSHLiv2i32:
|
|
case ARM::VSHLiv2i64:
|
|
case ARM::VSHLiv4i16:
|
|
case ARM::VSHLiv4i32:
|
|
case ARM::VSHLiv8i16:
|
|
case ARM::VSHLiv8i8:
|
|
case ARM::VSHLsv16i8:
|
|
case ARM::VSHLsv1i64:
|
|
case ARM::VSHLsv2i32:
|
|
case ARM::VSHLsv2i64:
|
|
case ARM::VSHLsv4i16:
|
|
case ARM::VSHLsv4i32:
|
|
case ARM::VSHLsv8i16:
|
|
case ARM::VSHLsv8i8:
|
|
case ARM::VSHLuv16i8:
|
|
case ARM::VSHLuv1i64:
|
|
case ARM::VSHLuv2i32:
|
|
case ARM::VSHLuv2i64:
|
|
case ARM::VSHLuv4i16:
|
|
case ARM::VSHLuv4i32:
|
|
case ARM::VSHLuv8i16:
|
|
case ARM::VSHLuv8i8:
|
|
case ARM::VSHRNv2i32:
|
|
case ARM::VSHRNv4i16:
|
|
case ARM::VSHRNv8i8:
|
|
case ARM::VSHRsv16i8:
|
|
case ARM::VSHRsv1i64:
|
|
case ARM::VSHRsv2i32:
|
|
case ARM::VSHRsv2i64:
|
|
case ARM::VSHRsv4i16:
|
|
case ARM::VSHRsv4i32:
|
|
case ARM::VSHRsv8i16:
|
|
case ARM::VSHRsv8i8:
|
|
case ARM::VSHRuv16i8:
|
|
case ARM::VSHRuv1i64:
|
|
case ARM::VSHRuv2i32:
|
|
case ARM::VSHRuv2i64:
|
|
case ARM::VSHRuv4i16:
|
|
case ARM::VSHRuv4i32:
|
|
case ARM::VSHRuv8i16:
|
|
case ARM::VSHRuv8i8:
|
|
case ARM::VSUBHNv2i32:
|
|
case ARM::VSUBHNv4i16:
|
|
case ARM::VSUBHNv8i8:
|
|
case ARM::VSUBLsv2i64:
|
|
case ARM::VSUBLsv4i32:
|
|
case ARM::VSUBLsv8i16:
|
|
case ARM::VSUBLuv2i64:
|
|
case ARM::VSUBLuv4i32:
|
|
case ARM::VSUBLuv8i16:
|
|
case ARM::VSUBWsv2i64:
|
|
case ARM::VSUBWsv4i32:
|
|
case ARM::VSUBWsv8i16:
|
|
case ARM::VSUBWuv2i64:
|
|
case ARM::VSUBWuv4i32:
|
|
case ARM::VSUBWuv8i16:
|
|
case ARM::VSUBv16i8:
|
|
case ARM::VSUBv1i64:
|
|
case ARM::VSUBv2i32:
|
|
case ARM::VSUBv2i64:
|
|
case ARM::VSUBv4i16:
|
|
case ARM::VSUBv4i32:
|
|
case ARM::VSUBv8i16:
|
|
case ARM::VSUBv8i8:
|
|
case ARM::t2LDRDpci:
|
|
case ARM::t2MOVTi16:
|
|
case ARM::t2SUBrSPi12_:
|
|
case ARM::t2SUBrSPi_:
|
|
case ARM::tADDhirr:
|
|
case ARM::tMOVCCi:
|
|
case ARM::tMOVCCr: printOperand(MI, 2); break;
|
|
case ARM::ADCSSrs:
|
|
case ARM::MOVCCs:
|
|
case ARM::RSCSrs:
|
|
case ARM::SBCSSrs: printSORegOperand(MI, 2); break;
|
|
case ARM::BFC:
|
|
case ARM::t2BFC: printBitfieldInvMaskImmOperand(MI, 2); break;
|
|
case ARM::CLZ:
|
|
case ARM::CMNzrr:
|
|
case ARM::CMPrr:
|
|
case ARM::CMPzrr:
|
|
case ARM::MOVi16:
|
|
case ARM::RBIT:
|
|
case ARM::REV:
|
|
case ARM::REV16:
|
|
case ARM::REVSH:
|
|
case ARM::SXTB16r:
|
|
case ARM::SXTBr:
|
|
case ARM::SXTHr:
|
|
case ARM::TEQrr:
|
|
case ARM::TSTrr:
|
|
case ARM::UXTB16r:
|
|
case ARM::UXTBr:
|
|
case ARM::UXTHr:
|
|
case ARM::VCNTd:
|
|
case ARM::VCNTq:
|
|
case ARM::VDUP16d:
|
|
case ARM::VDUP16q:
|
|
case ARM::VDUP32d:
|
|
case ARM::VDUP32q:
|
|
case ARM::VDUP8d:
|
|
case ARM::VDUP8q:
|
|
case ARM::VDUPfd:
|
|
case ARM::VDUPfq:
|
|
case ARM::VMOVDneon:
|
|
case ARM::VMOVQ:
|
|
case ARM::VMOVRS:
|
|
case ARM::VMOVSR:
|
|
case ARM::VMVNd:
|
|
case ARM::VMVNq:
|
|
case ARM::VREV16d8:
|
|
case ARM::VREV16q8:
|
|
case ARM::VREV32d16:
|
|
case ARM::VREV32d8:
|
|
case ARM::VREV32q16:
|
|
case ARM::VREV32q8:
|
|
case ARM::VREV64d16:
|
|
case ARM::VREV64d32:
|
|
case ARM::VREV64d8:
|
|
case ARM::VREV64df:
|
|
case ARM::VREV64q16:
|
|
case ARM::VREV64q32:
|
|
case ARM::VREV64q8:
|
|
case ARM::VREV64qf:
|
|
case ARM::VSWPd:
|
|
case ARM::VSWPq:
|
|
case ARM::VTRNd16:
|
|
case ARM::VTRNd32:
|
|
case ARM::VTRNd8:
|
|
case ARM::VTRNq16:
|
|
case ARM::VTRNq32:
|
|
case ARM::VTRNq8:
|
|
case ARM::VUZPd16:
|
|
case ARM::VUZPd32:
|
|
case ARM::VUZPd8:
|
|
case ARM::VUZPq16:
|
|
case ARM::VUZPq32:
|
|
case ARM::VUZPq8:
|
|
case ARM::VZIPd16:
|
|
case ARM::VZIPd32:
|
|
case ARM::VZIPd8:
|
|
case ARM::VZIPq16:
|
|
case ARM::VZIPq32:
|
|
case ARM::VZIPq8:
|
|
case ARM::t2CLZ:
|
|
case ARM::t2MOVi16:
|
|
case ARM::t2RBIT:
|
|
case ARM::t2SXTB16r:
|
|
case ARM::t2UXTB16r:
|
|
case ARM::tCMNz:
|
|
case ARM::tCMPhir:
|
|
case ARM::tCMPi8:
|
|
case ARM::tCMPr:
|
|
case ARM::tCMPzhir:
|
|
case ARM::tCMPzi8:
|
|
case ARM::tCMPzr:
|
|
case ARM::tLDRcp:
|
|
case ARM::tREV:
|
|
case ARM::tREV16:
|
|
case ARM::tREVSH:
|
|
case ARM::tSXTB:
|
|
case ARM::tSXTH:
|
|
case ARM::tTST:
|
|
case ARM::tUXTB:
|
|
case ARM::tUXTH: printOperand(MI, 1); break;
|
|
case ARM::CMNzri:
|
|
case ARM::CMPri:
|
|
case ARM::CMPzri:
|
|
case ARM::TEQri:
|
|
case ARM::TSTri: printSOImmOperand(MI, 1); break;
|
|
case ARM::CMNzrs:
|
|
case ARM::CMPrs:
|
|
case ARM::CMPzrs:
|
|
case ARM::TEQrs:
|
|
case ARM::TSTrs: printSORegOperand(MI, 1); break;
|
|
case ARM::LDC2_OFFSET:
|
|
case ARM::LDC_OFFSET:
|
|
case ARM::STC2_OFFSET:
|
|
case ARM::STC_OFFSET: printAddrMode2Operand(MI, 2); break;
|
|
case ARM::LDR:
|
|
case ARM::LDRB:
|
|
case ARM::LDRcp:
|
|
case ARM::STR:
|
|
case ARM::STRB: printAddrMode2Operand(MI, 1); break;
|
|
case ARM::LDRD:
|
|
case ARM::STRD: printAddrMode3Operand(MI, 2); break;
|
|
case ARM::LDRH:
|
|
case ARM::LDRSB:
|
|
case ARM::LDRSH:
|
|
case ARM::STRH: printAddrMode3Operand(MI, 1); break;
|
|
case ARM::MOVi2pieces: printSOImm2PartOperand(MI, 1); break;
|
|
case ARM::VABALsv2i64:
|
|
case ARM::VABALsv4i32:
|
|
case ARM::VABALsv8i16:
|
|
case ARM::VABALuv2i64:
|
|
case ARM::VABALuv4i32:
|
|
case ARM::VABALuv8i16:
|
|
case ARM::VABAsv16i8:
|
|
case ARM::VABAsv2i32:
|
|
case ARM::VABAsv4i16:
|
|
case ARM::VABAsv4i32:
|
|
case ARM::VABAsv8i16:
|
|
case ARM::VABAsv8i8:
|
|
case ARM::VABAuv16i8:
|
|
case ARM::VABAuv2i32:
|
|
case ARM::VABAuv4i16:
|
|
case ARM::VABAuv4i32:
|
|
case ARM::VABAuv8i16:
|
|
case ARM::VABAuv8i8:
|
|
case ARM::VMLALsv2i64:
|
|
case ARM::VMLALsv4i32:
|
|
case ARM::VMLALsv8i16:
|
|
case ARM::VMLALuv2i64:
|
|
case ARM::VMLALuv4i32:
|
|
case ARM::VMLALuv8i16:
|
|
case ARM::VMLAv16i8:
|
|
case ARM::VMLAv2i32:
|
|
case ARM::VMLAv4i16:
|
|
case ARM::VMLAv4i32:
|
|
case ARM::VMLAv8i16:
|
|
case ARM::VMLAv8i8:
|
|
case ARM::VMLSLsv2i64:
|
|
case ARM::VMLSLsv4i32:
|
|
case ARM::VMLSLsv8i16:
|
|
case ARM::VMLSLuv2i64:
|
|
case ARM::VMLSLuv4i32:
|
|
case ARM::VMLSLuv8i16:
|
|
case ARM::VMLSv16i8:
|
|
case ARM::VMLSv2i32:
|
|
case ARM::VMLSv4i16:
|
|
case ARM::VMLSv4i32:
|
|
case ARM::VMLSv8i16:
|
|
case ARM::VMLSv8i8:
|
|
case ARM::VQDMLALv2i64:
|
|
case ARM::VQDMLALv4i32:
|
|
case ARM::VQDMLSLv2i64:
|
|
case ARM::VQDMLSLv4i32:
|
|
case ARM::VRSRAsv16i8:
|
|
case ARM::VRSRAsv1i64:
|
|
case ARM::VRSRAsv2i32:
|
|
case ARM::VRSRAsv2i64:
|
|
case ARM::VRSRAsv4i16:
|
|
case ARM::VRSRAsv4i32:
|
|
case ARM::VRSRAsv8i16:
|
|
case ARM::VRSRAsv8i8:
|
|
case ARM::VRSRAuv16i8:
|
|
case ARM::VRSRAuv1i64:
|
|
case ARM::VRSRAuv2i32:
|
|
case ARM::VRSRAuv2i64:
|
|
case ARM::VRSRAuv4i16:
|
|
case ARM::VRSRAuv4i32:
|
|
case ARM::VRSRAuv8i16:
|
|
case ARM::VRSRAuv8i8:
|
|
case ARM::VSRAsv16i8:
|
|
case ARM::VSRAsv1i64:
|
|
case ARM::VSRAsv2i32:
|
|
case ARM::VSRAsv2i64:
|
|
case ARM::VSRAsv4i16:
|
|
case ARM::VSRAsv4i32:
|
|
case ARM::VSRAsv8i16:
|
|
case ARM::VSRAsv8i8:
|
|
case ARM::VSRAuv16i8:
|
|
case ARM::VSRAuv1i64:
|
|
case ARM::VSRAuv2i32:
|
|
case ARM::VSRAuv2i64:
|
|
case ARM::VSRAuv4i16:
|
|
case ARM::VSRAuv4i32:
|
|
case ARM::VSRAuv8i16:
|
|
case ARM::VSRAuv8i8:
|
|
case ARM::tADDi3:
|
|
case ARM::tADDrr:
|
|
case ARM::tASRri:
|
|
case ARM::tLSLri:
|
|
case ARM::tLSRri:
|
|
case ARM::tSUBi3:
|
|
case ARM::tSUBrr: printOperand(MI, 3); break;
|
|
case ARM::VDUPfdf:
|
|
case ARM::VDUPfqf: printOperand(MI, 1, "lane"); break;
|
|
case ARM::VLDRD:
|
|
case ARM::VLDRS:
|
|
case ARM::VSTRD:
|
|
case ARM::VSTRS: printAddrMode5Operand(MI, 1); break;
|
|
case ARM::t2LDRBT:
|
|
case ARM::t2LDRBi8:
|
|
case ARM::t2LDRHT:
|
|
case ARM::t2LDRHi8:
|
|
case ARM::t2LDRSBT:
|
|
case ARM::t2LDRSBi8:
|
|
case ARM::t2LDRSHT:
|
|
case ARM::t2LDRSHi8:
|
|
case ARM::t2LDRT:
|
|
case ARM::t2LDRi8:
|
|
case ARM::t2STRBT:
|
|
case ARM::t2STRBi8:
|
|
case ARM::t2STRHT:
|
|
case ARM::t2STRHi8:
|
|
case ARM::t2STRT:
|
|
case ARM::t2STRi8: printT2AddrModeImm8Operand(MI, 1); break;
|
|
case ARM::t2LDRDi8:
|
|
case ARM::t2STRDi8: printT2AddrModeImm8s4Operand(MI, 2); break;
|
|
case ARM::t2SUBrSPs_: printT2SOOperand(MI, 2); break;
|
|
case ARM::tADDrSPi: printThumbS4ImmOperand(MI, 2); break;
|
|
case ARM::tLDR:
|
|
case ARM::tLDRi:
|
|
case ARM::tSTR:
|
|
case ARM::tSTRi: printThumbAddrModeS4Operand(MI, 1); break;
|
|
case ARM::tLDRB:
|
|
case ARM::tLDRBi:
|
|
case ARM::tSTRB:
|
|
case ARM::tSTRBi: printThumbAddrModeS1Operand(MI, 1); break;
|
|
case ARM::tLDRH:
|
|
case ARM::tLDRHi:
|
|
case ARM::tSTRH:
|
|
case ARM::tSTRHi: printThumbAddrModeS2Operand(MI, 1); break;
|
|
case ARM::tLDRSB:
|
|
case ARM::tLDRSH: printThumbAddrModeRROperand(MI, 1); break;
|
|
case ARM::tLDRspi:
|
|
case ARM::tRestore:
|
|
case ARM::tSTRspi:
|
|
case ARM::tSpill: printThumbAddrModeSPOperand(MI, 1); break;
|
|
case ARM::tMUL: printOperand(MI, 0); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::ADCrr:
|
|
case ARM::ADDrr:
|
|
case ARM::ANDrr:
|
|
case ARM::BICrr:
|
|
case ARM::BKPT:
|
|
case ARM::BXJ:
|
|
case ARM::Bcc:
|
|
case ARM::DBG:
|
|
case ARM::EORrr:
|
|
case ARM::MOVr:
|
|
case ARM::MSR:
|
|
case ARM::MSRsys:
|
|
case ARM::MUL:
|
|
case ARM::MVNr:
|
|
case ARM::ORRrr:
|
|
case ARM::RFE:
|
|
case ARM::SBCrr:
|
|
case ARM::SMC:
|
|
case ARM::SRS:
|
|
case ARM::SRSW:
|
|
case ARM::SUBrr:
|
|
case ARM::SVC:
|
|
case ARM::VABSv16i8:
|
|
case ARM::VABSv2i32:
|
|
case ARM::VABSv4i16:
|
|
case ARM::VABSv4i32:
|
|
case ARM::VABSv8i16:
|
|
case ARM::VABSv8i8:
|
|
case ARM::VCLSv16i8:
|
|
case ARM::VCLSv2i32:
|
|
case ARM::VCLSv4i16:
|
|
case ARM::VCLSv4i32:
|
|
case ARM::VCLSv8i16:
|
|
case ARM::VCLSv8i8:
|
|
case ARM::VCLZv16i8:
|
|
case ARM::VCLZv2i32:
|
|
case ARM::VCLZv4i16:
|
|
case ARM::VCLZv4i32:
|
|
case ARM::VCLZv8i16:
|
|
case ARM::VCLZv8i8:
|
|
case ARM::VMOVLsv2i64:
|
|
case ARM::VMOVLsv4i32:
|
|
case ARM::VMOVLsv8i16:
|
|
case ARM::VMOVLuv2i64:
|
|
case ARM::VMOVLuv4i32:
|
|
case ARM::VMOVLuv8i16:
|
|
case ARM::VMOVNv2i32:
|
|
case ARM::VMOVNv4i16:
|
|
case ARM::VMOVNv8i8:
|
|
case ARM::VNEGs16d:
|
|
case ARM::VNEGs16q:
|
|
case ARM::VNEGs32d:
|
|
case ARM::VNEGs32q:
|
|
case ARM::VNEGs8d:
|
|
case ARM::VNEGs8q:
|
|
case ARM::VPADALsv16i8:
|
|
case ARM::VPADALsv2i32:
|
|
case ARM::VPADALsv4i16:
|
|
case ARM::VPADALsv4i32:
|
|
case ARM::VPADALsv8i16:
|
|
case ARM::VPADALsv8i8:
|
|
case ARM::VPADALuv16i8:
|
|
case ARM::VPADALuv2i32:
|
|
case ARM::VPADALuv4i16:
|
|
case ARM::VPADALuv4i32:
|
|
case ARM::VPADALuv8i16:
|
|
case ARM::VPADALuv8i8:
|
|
case ARM::VPADDLsv16i8:
|
|
case ARM::VPADDLsv2i32:
|
|
case ARM::VPADDLsv4i16:
|
|
case ARM::VPADDLsv4i32:
|
|
case ARM::VPADDLsv8i16:
|
|
case ARM::VPADDLsv8i8:
|
|
case ARM::VPADDLuv16i8:
|
|
case ARM::VPADDLuv2i32:
|
|
case ARM::VPADDLuv4i16:
|
|
case ARM::VPADDLuv4i32:
|
|
case ARM::VPADDLuv8i16:
|
|
case ARM::VPADDLuv8i8:
|
|
case ARM::VQABSv16i8:
|
|
case ARM::VQABSv2i32:
|
|
case ARM::VQABSv4i16:
|
|
case ARM::VQABSv4i32:
|
|
case ARM::VQABSv8i16:
|
|
case ARM::VQABSv8i8:
|
|
case ARM::VQMOVNsuv2i32:
|
|
case ARM::VQMOVNsuv4i16:
|
|
case ARM::VQMOVNsuv8i8:
|
|
case ARM::VQMOVNsv2i32:
|
|
case ARM::VQMOVNsv4i16:
|
|
case ARM::VQMOVNsv8i8:
|
|
case ARM::VQMOVNuv2i32:
|
|
case ARM::VQMOVNuv4i16:
|
|
case ARM::VQMOVNuv8i8:
|
|
case ARM::VQNEGv16i8:
|
|
case ARM::VQNEGv2i32:
|
|
case ARM::VQNEGv4i16:
|
|
case ARM::VQNEGv4i32:
|
|
case ARM::VQNEGv8i16:
|
|
case ARM::VQNEGv8i8:
|
|
case ARM::VRECPEd:
|
|
case ARM::VRECPEq:
|
|
case ARM::VRSQRTEd:
|
|
case ARM::VRSQRTEq:
|
|
case ARM::t2BXJ:
|
|
case ARM::t2DBG:
|
|
case ARM::t2LEApcrel:
|
|
case ARM::t2MSR:
|
|
case ARM::t2MSRsys:
|
|
case ARM::t2RFEDB:
|
|
case ARM::t2RFEIA:
|
|
case ARM::t2SMC:
|
|
case ARM::t2SRSDB:
|
|
case ARM::t2SRSDBW:
|
|
case ARM::t2SRSIA:
|
|
case ARM::t2SRSIAW:
|
|
case ARM::tADC:
|
|
case ARM::tADDi8:
|
|
case ARM::tADDrSP:
|
|
case ARM::tADDspr:
|
|
case ARM::tADDspr_:
|
|
case ARM::tAND:
|
|
case ARM::tANDsp:
|
|
case ARM::tASRrr:
|
|
case ARM::tBIC:
|
|
case ARM::tBcc:
|
|
case ARM::tCBNZ:
|
|
case ARM::tCBZ:
|
|
case ARM::tEOR:
|
|
case ARM::tLSLrr:
|
|
case ARM::tLSRrr:
|
|
case ARM::tMOVSr:
|
|
case ARM::tMOVgpr2gpr:
|
|
case ARM::tMOVgpr2tgpr:
|
|
case ARM::tMOVr:
|
|
case ARM::tMOVtgpr2gpr:
|
|
case ARM::tORR:
|
|
case ARM::tROR:
|
|
case ARM::tSBC:
|
|
case ARM::tSUBi8:
|
|
case ARM::tSVC:
|
|
return;
|
|
break;
|
|
case ARM::ADDSri:
|
|
case ARM::ADDSrr:
|
|
case ARM::ADDSrs:
|
|
case ARM::BFI:
|
|
case ARM::QADD:
|
|
case ARM::QADD16:
|
|
case ARM::QADD8:
|
|
case ARM::QASX:
|
|
case ARM::QDADD:
|
|
case ARM::QDSUB:
|
|
case ARM::QSAX:
|
|
case ARM::QSUB:
|
|
case ARM::QSUB16:
|
|
case ARM::QSUB8:
|
|
case ARM::RSBSri:
|
|
case ARM::RSBSrs:
|
|
case ARM::SADD16:
|
|
case ARM::SADD8:
|
|
case ARM::SASX:
|
|
case ARM::SEL:
|
|
case ARM::SHADD16:
|
|
case ARM::SHADD8:
|
|
case ARM::SHASX:
|
|
case ARM::SHSAX:
|
|
case ARM::SHSUB16:
|
|
case ARM::SHSUB8:
|
|
case ARM::SMMUL:
|
|
case ARM::SMMULR:
|
|
case ARM::SMUAD:
|
|
case ARM::SMUADX:
|
|
case ARM::SMULBB:
|
|
case ARM::SMULBT:
|
|
case ARM::SMULTB:
|
|
case ARM::SMULTT:
|
|
case ARM::SMULWB:
|
|
case ARM::SMULWT:
|
|
case ARM::SMUSD:
|
|
case ARM::SMUSDX:
|
|
case ARM::SSAT16:
|
|
case ARM::SSAX:
|
|
case ARM::SSUB16:
|
|
case ARM::SSUB8:
|
|
case ARM::SUBSri:
|
|
case ARM::SUBSrr:
|
|
case ARM::SUBSrs:
|
|
case ARM::SXTAB16rr:
|
|
case ARM::SXTABrr:
|
|
case ARM::SXTAHrr:
|
|
case ARM::UADD16:
|
|
case ARM::UADD8:
|
|
case ARM::UASX:
|
|
case ARM::UHADD16:
|
|
case ARM::UHADD8:
|
|
case ARM::UHASX:
|
|
case ARM::UHSAX:
|
|
case ARM::UHSUB16:
|
|
case ARM::UHSUB8:
|
|
case ARM::UQADD16:
|
|
case ARM::UQADD8:
|
|
case ARM::UQASX:
|
|
case ARM::UQSAX:
|
|
case ARM::UQSUB16:
|
|
case ARM::UQSUB8:
|
|
case ARM::USAD8:
|
|
case ARM::USAT16:
|
|
case ARM::USAX:
|
|
case ARM::USUB16:
|
|
case ARM::USUB8:
|
|
case ARM::UXTAB16rr:
|
|
case ARM::UXTABrr:
|
|
case ARM::UXTAHrr:
|
|
case ARM::VANDd:
|
|
case ARM::VANDq:
|
|
case ARM::VBICd:
|
|
case ARM::VBICq:
|
|
case ARM::VEORd:
|
|
case ARM::VEORq:
|
|
case ARM::VMOVDRR:
|
|
case ARM::VMOVRRD:
|
|
case ARM::VORNd:
|
|
case ARM::VORNq:
|
|
case ARM::VORRd:
|
|
case ARM::VORRq:
|
|
case ARM::VTSTv16i8:
|
|
case ARM::VTSTv2i32:
|
|
case ARM::VTSTv4i16:
|
|
case ARM::VTSTv4i32:
|
|
case ARM::VTSTv8i16:
|
|
case ARM::VTSTv8i8:
|
|
case ARM::t2ADCSri:
|
|
case ARM::t2ADCri:
|
|
case ARM::t2ADDrSPi12:
|
|
case ARM::t2ADDri12:
|
|
case ARM::t2ANDri:
|
|
case ARM::t2BICri:
|
|
case ARM::t2EORri:
|
|
case ARM::t2MUL:
|
|
case ARM::t2ORNri:
|
|
case ARM::t2ORNrr:
|
|
case ARM::t2ORNrs:
|
|
case ARM::t2ORRri:
|
|
case ARM::t2QADD:
|
|
case ARM::t2QADD16:
|
|
case ARM::t2QADD8:
|
|
case ARM::t2QASX:
|
|
case ARM::t2QDADD:
|
|
case ARM::t2QDSUB:
|
|
case ARM::t2QSAX:
|
|
case ARM::t2QSUB:
|
|
case ARM::t2QSUB16:
|
|
case ARM::t2QSUB8:
|
|
case ARM::t2RSBSrs:
|
|
case ARM::t2RSBrs:
|
|
case ARM::t2SADD16:
|
|
case ARM::t2SADD8:
|
|
case ARM::t2SASX:
|
|
case ARM::t2SBCSri:
|
|
case ARM::t2SBCri:
|
|
case ARM::t2SDIV:
|
|
case ARM::t2SEL:
|
|
case ARM::t2SHADD16:
|
|
case ARM::t2SHADD8:
|
|
case ARM::t2SHASX:
|
|
case ARM::t2SHSAX:
|
|
case ARM::t2SHSUB16:
|
|
case ARM::t2SHSUB8:
|
|
case ARM::t2SMMUL:
|
|
case ARM::t2SMMULR:
|
|
case ARM::t2SMUAD:
|
|
case ARM::t2SMUADX:
|
|
case ARM::t2SMULBB:
|
|
case ARM::t2SMULBT:
|
|
case ARM::t2SMULTB:
|
|
case ARM::t2SMULTT:
|
|
case ARM::t2SMULWB:
|
|
case ARM::t2SMULWT:
|
|
case ARM::t2SMUSD:
|
|
case ARM::t2SMUSDX:
|
|
case ARM::t2SSAT16:
|
|
case ARM::t2SSAX:
|
|
case ARM::t2SSUB16:
|
|
case ARM::t2SSUB8:
|
|
case ARM::t2SUBrSPi12:
|
|
case ARM::t2SUBrSPs:
|
|
case ARM::t2SUBri12:
|
|
case ARM::t2SXTAB16rr:
|
|
case ARM::t2SXTABrr:
|
|
case ARM::t2SXTAHrr:
|
|
case ARM::t2UADD16:
|
|
case ARM::t2UADD8:
|
|
case ARM::t2UASX:
|
|
case ARM::t2UDIV:
|
|
case ARM::t2UHADD16:
|
|
case ARM::t2UHADD8:
|
|
case ARM::t2UHASX:
|
|
case ARM::t2UHSAX:
|
|
case ARM::t2UHSUB16:
|
|
case ARM::t2UHSUB8:
|
|
case ARM::t2UQADD16:
|
|
case ARM::t2UQADD8:
|
|
case ARM::t2UQASX:
|
|
case ARM::t2UQSAX:
|
|
case ARM::t2UQSUB16:
|
|
case ARM::t2UQSUB8:
|
|
case ARM::t2USAD8:
|
|
case ARM::t2USAT16:
|
|
case ARM::t2USAX:
|
|
case ARM::t2USUB16:
|
|
case ARM::t2USUB8:
|
|
case ARM::t2UXTAB16rr:
|
|
case ARM::t2UXTABrr:
|
|
case ARM::t2UXTAHrr:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::ADDSri:
|
|
case ARM::RSBSri:
|
|
case ARM::SUBSri: printSOImmOperand(MI, 2); break;
|
|
case ARM::ADDSrr:
|
|
case ARM::QADD:
|
|
case ARM::QADD16:
|
|
case ARM::QADD8:
|
|
case ARM::QASX:
|
|
case ARM::QDADD:
|
|
case ARM::QDSUB:
|
|
case ARM::QSAX:
|
|
case ARM::QSUB:
|
|
case ARM::QSUB16:
|
|
case ARM::QSUB8:
|
|
case ARM::SADD16:
|
|
case ARM::SADD8:
|
|
case ARM::SASX:
|
|
case ARM::SEL:
|
|
case ARM::SHADD16:
|
|
case ARM::SHADD8:
|
|
case ARM::SHASX:
|
|
case ARM::SHSAX:
|
|
case ARM::SHSUB16:
|
|
case ARM::SHSUB8:
|
|
case ARM::SMMUL:
|
|
case ARM::SMMULR:
|
|
case ARM::SMUAD:
|
|
case ARM::SMUADX:
|
|
case ARM::SMULBB:
|
|
case ARM::SMULBT:
|
|
case ARM::SMULTB:
|
|
case ARM::SMULTT:
|
|
case ARM::SMULWB:
|
|
case ARM::SMULWT:
|
|
case ARM::SMUSD:
|
|
case ARM::SMUSDX:
|
|
case ARM::SSAT16:
|
|
case ARM::SSAX:
|
|
case ARM::SSUB16:
|
|
case ARM::SSUB8:
|
|
case ARM::SUBSrr:
|
|
case ARM::SXTAB16rr:
|
|
case ARM::SXTABrr:
|
|
case ARM::SXTAHrr:
|
|
case ARM::UADD16:
|
|
case ARM::UADD8:
|
|
case ARM::UASX:
|
|
case ARM::UHADD16:
|
|
case ARM::UHADD8:
|
|
case ARM::UHASX:
|
|
case ARM::UHSAX:
|
|
case ARM::UHSUB16:
|
|
case ARM::UHSUB8:
|
|
case ARM::UQADD16:
|
|
case ARM::UQADD8:
|
|
case ARM::UQASX:
|
|
case ARM::UQSAX:
|
|
case ARM::UQSUB16:
|
|
case ARM::UQSUB8:
|
|
case ARM::USAD8:
|
|
case ARM::USAT16:
|
|
case ARM::USAX:
|
|
case ARM::USUB16:
|
|
case ARM::USUB8:
|
|
case ARM::UXTAB16rr:
|
|
case ARM::UXTABrr:
|
|
case ARM::UXTAHrr:
|
|
case ARM::VANDd:
|
|
case ARM::VANDq:
|
|
case ARM::VBICd:
|
|
case ARM::VBICq:
|
|
case ARM::VEORd:
|
|
case ARM::VEORq:
|
|
case ARM::VMOVDRR:
|
|
case ARM::VMOVRRD:
|
|
case ARM::VORNd:
|
|
case ARM::VORNq:
|
|
case ARM::VORRd:
|
|
case ARM::VORRq:
|
|
case ARM::VTSTv16i8:
|
|
case ARM::VTSTv2i32:
|
|
case ARM::VTSTv4i16:
|
|
case ARM::VTSTv4i32:
|
|
case ARM::VTSTv8i16:
|
|
case ARM::VTSTv8i8:
|
|
case ARM::t2ADCSri:
|
|
case ARM::t2ADCri:
|
|
case ARM::t2ADDrSPi12:
|
|
case ARM::t2ADDri12:
|
|
case ARM::t2ANDri:
|
|
case ARM::t2BICri:
|
|
case ARM::t2EORri:
|
|
case ARM::t2MUL:
|
|
case ARM::t2ORNri:
|
|
case ARM::t2ORNrr:
|
|
case ARM::t2ORRri:
|
|
case ARM::t2QADD:
|
|
case ARM::t2QADD16:
|
|
case ARM::t2QADD8:
|
|
case ARM::t2QASX:
|
|
case ARM::t2QDADD:
|
|
case ARM::t2QDSUB:
|
|
case ARM::t2QSAX:
|
|
case ARM::t2QSUB:
|
|
case ARM::t2QSUB16:
|
|
case ARM::t2QSUB8:
|
|
case ARM::t2SADD16:
|
|
case ARM::t2SADD8:
|
|
case ARM::t2SASX:
|
|
case ARM::t2SBCSri:
|
|
case ARM::t2SBCri:
|
|
case ARM::t2SDIV:
|
|
case ARM::t2SEL:
|
|
case ARM::t2SHADD16:
|
|
case ARM::t2SHADD8:
|
|
case ARM::t2SHASX:
|
|
case ARM::t2SHSAX:
|
|
case ARM::t2SHSUB16:
|
|
case ARM::t2SHSUB8:
|
|
case ARM::t2SMMUL:
|
|
case ARM::t2SMMULR:
|
|
case ARM::t2SMUAD:
|
|
case ARM::t2SMUADX:
|
|
case ARM::t2SMULBB:
|
|
case ARM::t2SMULBT:
|
|
case ARM::t2SMULTB:
|
|
case ARM::t2SMULTT:
|
|
case ARM::t2SMULWB:
|
|
case ARM::t2SMULWT:
|
|
case ARM::t2SMUSD:
|
|
case ARM::t2SMUSDX:
|
|
case ARM::t2SSAT16:
|
|
case ARM::t2SSAX:
|
|
case ARM::t2SSUB16:
|
|
case ARM::t2SSUB8:
|
|
case ARM::t2SUBrSPi12:
|
|
case ARM::t2SUBri12:
|
|
case ARM::t2SXTAB16rr:
|
|
case ARM::t2SXTABrr:
|
|
case ARM::t2SXTAHrr:
|
|
case ARM::t2UADD16:
|
|
case ARM::t2UADD8:
|
|
case ARM::t2UASX:
|
|
case ARM::t2UDIV:
|
|
case ARM::t2UHADD16:
|
|
case ARM::t2UHADD8:
|
|
case ARM::t2UHASX:
|
|
case ARM::t2UHSAX:
|
|
case ARM::t2UHSUB16:
|
|
case ARM::t2UHSUB8:
|
|
case ARM::t2UQADD16:
|
|
case ARM::t2UQADD8:
|
|
case ARM::t2UQASX:
|
|
case ARM::t2UQSAX:
|
|
case ARM::t2UQSUB16:
|
|
case ARM::t2UQSUB8:
|
|
case ARM::t2USAD8:
|
|
case ARM::t2USAT16:
|
|
case ARM::t2USAX:
|
|
case ARM::t2USUB16:
|
|
case ARM::t2USUB8:
|
|
case ARM::t2UXTAB16rr:
|
|
case ARM::t2UXTABrr:
|
|
case ARM::t2UXTAHrr: printOperand(MI, 2); break;
|
|
case ARM::ADDSrs:
|
|
case ARM::RSBSrs:
|
|
case ARM::SUBSrs: printSORegOperand(MI, 2); break;
|
|
case ARM::BFI: printBitfieldInvMaskImmOperand(MI, 2); break;
|
|
case ARM::t2ORNrs:
|
|
case ARM::t2RSBSrs:
|
|
case ARM::t2RSBrs:
|
|
case ARM::t2SUBrSPs: printT2SOOperand(MI, 2); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::BR_JTadd:
|
|
O << " \n";
|
|
printJTBlockOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::CDP:
|
|
printOperand(MI, 1);
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 2);
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 3);
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 4);
|
|
O << ", ";
|
|
printOperand(MI, 5);
|
|
return;
|
|
break;
|
|
case ARM::FCONSTD:
|
|
case ARM::FCONSTS:
|
|
case ARM::LDC2L_OFFSET:
|
|
case ARM::LDC2L_OPTION:
|
|
case ARM::LDC2L_POST:
|
|
case ARM::LDCL_OFFSET:
|
|
case ARM::LDCL_OPTION:
|
|
case ARM::LDCL_POST:
|
|
case ARM::MOVrx:
|
|
case ARM::MRS:
|
|
case ARM::MRSsys:
|
|
case ARM::PLDWi:
|
|
case ARM::PLDi:
|
|
case ARM::PLIi:
|
|
case ARM::RFEW:
|
|
case ARM::STC2L_OFFSET:
|
|
case ARM::STC2L_OPTION:
|
|
case ARM::STC2L_POST:
|
|
case ARM::STCL_OFFSET:
|
|
case ARM::STCL_OPTION:
|
|
case ARM::STCL_POST:
|
|
case ARM::VABSD:
|
|
case ARM::VABSS:
|
|
case ARM::VABSfd:
|
|
case ARM::VABSfd_sfp:
|
|
case ARM::VABSfq:
|
|
case ARM::VCEQzv16i8:
|
|
case ARM::VCEQzv2i32:
|
|
case ARM::VCEQzv4i16:
|
|
case ARM::VCEQzv4i32:
|
|
case ARM::VCEQzv8i16:
|
|
case ARM::VCEQzv8i8:
|
|
case ARM::VCGEzv16i8:
|
|
case ARM::VCGEzv2i32:
|
|
case ARM::VCGEzv4i16:
|
|
case ARM::VCGEzv4i32:
|
|
case ARM::VCGEzv8i16:
|
|
case ARM::VCGEzv8i8:
|
|
case ARM::VCGTzv16i8:
|
|
case ARM::VCGTzv2i32:
|
|
case ARM::VCGTzv4i16:
|
|
case ARM::VCGTzv4i32:
|
|
case ARM::VCGTzv8i16:
|
|
case ARM::VCGTzv8i8:
|
|
case ARM::VCLEzv16i8:
|
|
case ARM::VCLEzv2i32:
|
|
case ARM::VCLEzv4i16:
|
|
case ARM::VCLEzv4i32:
|
|
case ARM::VCLEzv8i16:
|
|
case ARM::VCLEzv8i8:
|
|
case ARM::VCLTzv16i8:
|
|
case ARM::VCLTzv2i32:
|
|
case ARM::VCLTzv4i16:
|
|
case ARM::VCLTzv4i32:
|
|
case ARM::VCLTzv8i16:
|
|
case ARM::VCLTzv8i8:
|
|
case ARM::VCMPD:
|
|
case ARM::VCMPED:
|
|
case ARM::VCMPES:
|
|
case ARM::VCMPS:
|
|
case ARM::VCVTf2xsd:
|
|
case ARM::VCVTf2xsq:
|
|
case ARM::VCVTf2xud:
|
|
case ARM::VCVTf2xuq:
|
|
case ARM::VCVTxs2fd:
|
|
case ARM::VCVTxs2fq:
|
|
case ARM::VCVTxu2fd:
|
|
case ARM::VCVTxu2fq:
|
|
case ARM::VMOVD:
|
|
case ARM::VMOVDcc:
|
|
case ARM::VMOVS:
|
|
case ARM::VMOVScc:
|
|
case ARM::VMRS:
|
|
case ARM::VNEGD:
|
|
case ARM::VNEGDcc:
|
|
case ARM::VNEGS:
|
|
case ARM::VNEGScc:
|
|
case ARM::VNEGf32q:
|
|
case ARM::VNEGfd:
|
|
case ARM::VNEGfd_sfp:
|
|
case ARM::VRECPEfd:
|
|
case ARM::VRECPEfq:
|
|
case ARM::VRSQRTEfd:
|
|
case ARM::VRSQRTEfq:
|
|
case ARM::VSLTOD:
|
|
case ARM::VSLTOS:
|
|
case ARM::VSQRTD:
|
|
case ARM::VSQRTS:
|
|
case ARM::VTOSLD:
|
|
case ARM::VTOSLS:
|
|
case ARM::VTOULD:
|
|
case ARM::VTOULS:
|
|
case ARM::VULTOD:
|
|
case ARM::VULTOS:
|
|
case ARM::t2CMNzri:
|
|
case ARM::t2CMNzrr:
|
|
case ARM::t2CMNzrs:
|
|
case ARM::t2CMPri:
|
|
case ARM::t2CMPrr:
|
|
case ARM::t2CMPrs:
|
|
case ARM::t2CMPzri:
|
|
case ARM::t2CMPzrr:
|
|
case ARM::t2CMPzrs:
|
|
case ARM::t2LDRBi12:
|
|
case ARM::t2LDRBpci:
|
|
case ARM::t2LDRBs:
|
|
case ARM::t2LDRHi12:
|
|
case ARM::t2LDRHpci:
|
|
case ARM::t2LDRHs:
|
|
case ARM::t2LDRSBi12:
|
|
case ARM::t2LDRSBpci:
|
|
case ARM::t2LDRSBs:
|
|
case ARM::t2LDRSHi12:
|
|
case ARM::t2LDRSHpci:
|
|
case ARM::t2LDRSHs:
|
|
case ARM::t2LDRi12:
|
|
case ARM::t2LDRpci:
|
|
case ARM::t2LDRs:
|
|
case ARM::t2MOVCCi:
|
|
case ARM::t2MOVCCr:
|
|
case ARM::t2MOVsra_flag:
|
|
case ARM::t2MOVsrl_flag:
|
|
case ARM::t2MRS:
|
|
case ARM::t2MRSsys:
|
|
case ARM::t2MVNr:
|
|
case ARM::t2MVNs:
|
|
case ARM::t2REV:
|
|
case ARM::t2REV16:
|
|
case ARM::t2REVSH:
|
|
case ARM::t2RFEDBW:
|
|
case ARM::t2RFEIAW:
|
|
case ARM::t2STRBi12:
|
|
case ARM::t2STRBs:
|
|
case ARM::t2STRHi12:
|
|
case ARM::t2STRHs:
|
|
case ARM::t2STRi12:
|
|
case ARM::t2STRs:
|
|
case ARM::t2SXTBr:
|
|
case ARM::t2SXTHr:
|
|
case ARM::t2TEQri:
|
|
case ARM::t2TEQrr:
|
|
case ARM::t2TEQrs:
|
|
case ARM::t2TSTri:
|
|
case ARM::t2TSTrr:
|
|
case ARM::t2TSTrs:
|
|
case ARM::t2UXTBr:
|
|
case ARM::t2UXTHr:
|
|
switch (MI->getOpcode()) {
|
|
case ARM::FCONSTD: printVFPf64ImmOperand(MI, 1); break;
|
|
case ARM::FCONSTS: printVFPf32ImmOperand(MI, 1); break;
|
|
case ARM::LDC2L_OFFSET:
|
|
case ARM::LDCL_OFFSET:
|
|
case ARM::STC2L_OFFSET:
|
|
case ARM::STCL_OFFSET: printAddrMode2Operand(MI, 2); break;
|
|
case ARM::LDC2L_OPTION:
|
|
case ARM::LDCL_OPTION:
|
|
case ARM::STC2L_OPTION:
|
|
case ARM::STCL_OPTION: printNoHashImmediate(MI, 3); break;
|
|
case ARM::LDC2L_POST:
|
|
case ARM::LDCL_POST:
|
|
case ARM::STC2L_POST:
|
|
case ARM::STCL_POST: printAddrMode2OffsetOperand(MI, 3); break;
|
|
case ARM::MOVrx: O << ", rrx"; break;
|
|
case ARM::MRS:
|
|
case ARM::t2MRS: O << ", cpsr"; break;
|
|
case ARM::MRSsys:
|
|
case ARM::t2MRSsys: O << ", spsr"; break;
|
|
case ARM::PLDWi:
|
|
case ARM::PLDi:
|
|
case ARM::PLIi: O << ']'; break;
|
|
case ARM::RFEW:
|
|
case ARM::t2RFEDBW:
|
|
case ARM::t2RFEIAW: O << '!'; break;
|
|
case ARM::VABSD:
|
|
case ARM::VABSS:
|
|
case ARM::VABSfd:
|
|
case ARM::VABSfd_sfp:
|
|
case ARM::VABSfq:
|
|
case ARM::VCMPD:
|
|
case ARM::VCMPED:
|
|
case ARM::VCMPES:
|
|
case ARM::VCMPS:
|
|
case ARM::VMOVD:
|
|
case ARM::VMOVS:
|
|
case ARM::VNEGD:
|
|
case ARM::VNEGS:
|
|
case ARM::VNEGf32q:
|
|
case ARM::VNEGfd:
|
|
case ARM::VNEGfd_sfp:
|
|
case ARM::VRECPEfd:
|
|
case ARM::VRECPEfq:
|
|
case ARM::VRSQRTEfd:
|
|
case ARM::VRSQRTEfq:
|
|
case ARM::VSQRTD:
|
|
case ARM::VSQRTS:
|
|
case ARM::t2CMNzri:
|
|
case ARM::t2CMNzrr:
|
|
case ARM::t2CMPri:
|
|
case ARM::t2CMPrr:
|
|
case ARM::t2CMPzri:
|
|
case ARM::t2CMPzrr:
|
|
case ARM::t2LDRBpci:
|
|
case ARM::t2LDRHpci:
|
|
case ARM::t2LDRSBpci:
|
|
case ARM::t2LDRSHpci:
|
|
case ARM::t2LDRpci:
|
|
case ARM::t2MVNr:
|
|
case ARM::t2REV:
|
|
case ARM::t2REV16:
|
|
case ARM::t2REVSH:
|
|
case ARM::t2SXTBr:
|
|
case ARM::t2SXTHr:
|
|
case ARM::t2TEQri:
|
|
case ARM::t2TEQrr:
|
|
case ARM::t2TSTri:
|
|
case ARM::t2TSTrr:
|
|
case ARM::t2UXTBr:
|
|
case ARM::t2UXTHr: printOperand(MI, 1); break;
|
|
case ARM::VCEQzv16i8:
|
|
case ARM::VCEQzv2i32:
|
|
case ARM::VCEQzv4i16:
|
|
case ARM::VCEQzv4i32:
|
|
case ARM::VCEQzv8i16:
|
|
case ARM::VCEQzv8i8:
|
|
case ARM::VCGEzv16i8:
|
|
case ARM::VCGEzv2i32:
|
|
case ARM::VCGEzv4i16:
|
|
case ARM::VCGEzv4i32:
|
|
case ARM::VCGEzv8i16:
|
|
case ARM::VCGEzv8i8:
|
|
case ARM::VCGTzv16i8:
|
|
case ARM::VCGTzv2i32:
|
|
case ARM::VCGTzv4i16:
|
|
case ARM::VCGTzv4i32:
|
|
case ARM::VCGTzv8i16:
|
|
case ARM::VCGTzv8i8:
|
|
case ARM::VCLEzv16i8:
|
|
case ARM::VCLEzv2i32:
|
|
case ARM::VCLEzv4i16:
|
|
case ARM::VCLEzv4i32:
|
|
case ARM::VCLEzv8i16:
|
|
case ARM::VCLEzv8i8:
|
|
case ARM::VCLTzv16i8:
|
|
case ARM::VCLTzv2i32:
|
|
case ARM::VCLTzv4i16:
|
|
case ARM::VCLTzv4i32:
|
|
case ARM::VCLTzv8i16:
|
|
case ARM::VCLTzv8i8: O << ", #0"; break;
|
|
case ARM::VCVTf2xsd:
|
|
case ARM::VCVTf2xsq:
|
|
case ARM::VCVTf2xud:
|
|
case ARM::VCVTf2xuq:
|
|
case ARM::VCVTxs2fd:
|
|
case ARM::VCVTxs2fq:
|
|
case ARM::VCVTxu2fd:
|
|
case ARM::VCVTxu2fq:
|
|
case ARM::VMOVDcc:
|
|
case ARM::VMOVScc:
|
|
case ARM::VNEGDcc:
|
|
case ARM::VNEGScc:
|
|
case ARM::VSLTOD:
|
|
case ARM::VSLTOS:
|
|
case ARM::VTOSLD:
|
|
case ARM::VTOSLS:
|
|
case ARM::VTOULD:
|
|
case ARM::VTOULS:
|
|
case ARM::VULTOD:
|
|
case ARM::VULTOS:
|
|
case ARM::t2MOVCCi:
|
|
case ARM::t2MOVCCr: printOperand(MI, 2); break;
|
|
case ARM::VMRS: O << ", fpscr"; break;
|
|
case ARM::t2CMNzrs:
|
|
case ARM::t2CMPrs:
|
|
case ARM::t2CMPzrs:
|
|
case ARM::t2MVNs:
|
|
case ARM::t2TEQrs:
|
|
case ARM::t2TSTrs: printT2SOOperand(MI, 1); break;
|
|
case ARM::t2LDRBi12:
|
|
case ARM::t2LDRHi12:
|
|
case ARM::t2LDRSBi12:
|
|
case ARM::t2LDRSHi12:
|
|
case ARM::t2LDRi12:
|
|
case ARM::t2STRBi12:
|
|
case ARM::t2STRHi12:
|
|
case ARM::t2STRi12: printT2AddrModeImm12Operand(MI, 1); break;
|
|
case ARM::t2LDRBs:
|
|
case ARM::t2LDRHs:
|
|
case ARM::t2LDRSBs:
|
|
case ARM::t2LDRSHs:
|
|
case ARM::t2LDRs:
|
|
case ARM::t2STRBs:
|
|
case ARM::t2STRHs:
|
|
case ARM::t2STRs: printT2AddrModeSoRegOperand(MI, 1); break;
|
|
case ARM::t2MOVsra_flag:
|
|
case ARM::t2MOVsrl_flag: O << ", #1"; break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::LDC2L_PRE:
|
|
case ARM::LDCL_PRE:
|
|
case ARM::STC2L_PRE:
|
|
case ARM::STCL_PRE:
|
|
printAddrMode2Operand(MI, 2);
|
|
O << '!';
|
|
return;
|
|
break;
|
|
case ARM::LDC2_OPTION:
|
|
case ARM::LDC2_POST:
|
|
case ARM::LDC_OPTION:
|
|
case ARM::LDC_POST:
|
|
case ARM::LDRBT:
|
|
case ARM::LDRB_POST:
|
|
case ARM::LDRHT:
|
|
case ARM::LDRH_POST:
|
|
case ARM::LDRSBT:
|
|
case ARM::LDRSB_POST:
|
|
case ARM::LDRSHT:
|
|
case ARM::LDRSH_POST:
|
|
case ARM::LDRT:
|
|
case ARM::LDR_POST:
|
|
case ARM::STC2_OPTION:
|
|
case ARM::STC2_POST:
|
|
case ARM::STC_OPTION:
|
|
case ARM::STC_POST:
|
|
case ARM::STRBT:
|
|
case ARM::STRB_POST:
|
|
case ARM::STRHT:
|
|
case ARM::STRH_POST:
|
|
case ARM::STRT:
|
|
case ARM::STR_POST:
|
|
case ARM::t2LDRB_POST:
|
|
case ARM::t2LDRH_POST:
|
|
case ARM::t2LDRSB_POST:
|
|
case ARM::t2LDRSH_POST:
|
|
case ARM::t2LDR_POST:
|
|
case ARM::t2STRB_POST:
|
|
case ARM::t2STRH_POST:
|
|
case ARM::t2STR_POST:
|
|
O << ", [";
|
|
printOperand(MI, 2);
|
|
O << "], ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::LDC2_OPTION:
|
|
case ARM::LDC_OPTION:
|
|
case ARM::STC2_OPTION:
|
|
case ARM::STC_OPTION: printOperand(MI, 3); break;
|
|
case ARM::LDC2_POST:
|
|
case ARM::LDC_POST:
|
|
case ARM::LDRBT:
|
|
case ARM::LDRB_POST:
|
|
case ARM::LDRSBT:
|
|
case ARM::LDRT:
|
|
case ARM::LDR_POST:
|
|
case ARM::STC2_POST:
|
|
case ARM::STC_POST:
|
|
case ARM::STRBT:
|
|
case ARM::STRB_POST:
|
|
case ARM::STRT:
|
|
case ARM::STR_POST: printAddrMode2OffsetOperand(MI, 3); break;
|
|
case ARM::LDRHT:
|
|
case ARM::LDRH_POST:
|
|
case ARM::LDRSB_POST:
|
|
case ARM::LDRSHT:
|
|
case ARM::LDRSH_POST:
|
|
case ARM::STRHT:
|
|
case ARM::STRH_POST: printAddrMode3OffsetOperand(MI, 3); break;
|
|
case ARM::t2LDRB_POST:
|
|
case ARM::t2LDRH_POST:
|
|
case ARM::t2LDRSB_POST:
|
|
case ARM::t2LDRSH_POST:
|
|
case ARM::t2LDR_POST:
|
|
case ARM::t2STRB_POST:
|
|
case ARM::t2STRH_POST:
|
|
case ARM::t2STR_POST: printT2AddrModeImm8OffsetOperand(MI, 3); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::LDC2_PRE:
|
|
case ARM::LDC_PRE:
|
|
case ARM::LDRB_PRE:
|
|
case ARM::LDRH_PRE:
|
|
case ARM::LDRSB_PRE:
|
|
case ARM::LDRSH_PRE:
|
|
case ARM::LDR_PRE:
|
|
case ARM::STC2_PRE:
|
|
case ARM::STC_PRE:
|
|
case ARM::t2LDRB_PRE:
|
|
case ARM::t2LDRH_PRE:
|
|
case ARM::t2LDRSB_PRE:
|
|
case ARM::t2LDRSH_PRE:
|
|
case ARM::t2LDR_PRE:
|
|
O << ", ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::LDC2_PRE:
|
|
case ARM::LDC_PRE:
|
|
case ARM::LDRB_PRE:
|
|
case ARM::LDR_PRE:
|
|
case ARM::STC2_PRE:
|
|
case ARM::STC_PRE: printAddrMode2Operand(MI, 2); break;
|
|
case ARM::LDRH_PRE:
|
|
case ARM::LDRSB_PRE:
|
|
case ARM::LDRSH_PRE: printAddrMode3Operand(MI, 2); break;
|
|
case ARM::t2LDRB_PRE:
|
|
case ARM::t2LDRH_PRE:
|
|
case ARM::t2LDRSB_PRE:
|
|
case ARM::t2LDRSH_PRE:
|
|
case ARM::t2LDR_PRE: printT2AddrModeImm8Operand(MI, 2); break;
|
|
}
|
|
O << '!';
|
|
return;
|
|
break;
|
|
case ARM::LDM:
|
|
case ARM::LDM_RET:
|
|
case ARM::STM:
|
|
case ARM::tLDM:
|
|
case ARM::tSTM:
|
|
printAddrMode4Operand(MI, 0);
|
|
O << ", ";
|
|
printRegisterList(MI, 4);
|
|
return;
|
|
break;
|
|
case ARM::LDRD_POST:
|
|
case ARM::STRD_POST:
|
|
O << ", ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::LDRD_POST: printOperand(MI, 1); break;
|
|
case ARM::STRD_POST: printOperand(MI, 2); break;
|
|
}
|
|
O << ", [";
|
|
printOperand(MI, 3);
|
|
O << "], ";
|
|
printAddrMode3OffsetOperand(MI, 4);
|
|
return;
|
|
break;
|
|
case ARM::LDRD_PRE:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printAddrMode3Operand(MI, 3);
|
|
O << '!';
|
|
return;
|
|
break;
|
|
case ARM::LDREX:
|
|
case ARM::LDREXB:
|
|
case ARM::LDREXH:
|
|
case ARM::t2LDREX:
|
|
case ARM::t2LDREXB:
|
|
case ARM::t2LDREXH:
|
|
O << ", [";
|
|
printOperand(MI, 1);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::LDREXD:
|
|
case ARM::STREX:
|
|
case ARM::STREXB:
|
|
case ARM::STREXH:
|
|
case ARM::SWP:
|
|
case ARM::SWPB:
|
|
case ARM::t2LDREXD:
|
|
case ARM::t2STREX:
|
|
case ARM::t2STREXB:
|
|
case ARM::t2STREXH:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", [";
|
|
printOperand(MI, 2);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::MCR:
|
|
case ARM::MRC:
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 3);
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 4);
|
|
O << ", ";
|
|
printOperand(MI, 5);
|
|
return;
|
|
break;
|
|
case ARM::MCR2:
|
|
case ARM::MRC2:
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 3);
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 4);
|
|
O << ", ";
|
|
printOperand(MI, 5);
|
|
return;
|
|
break;
|
|
case ARM::MCRR:
|
|
case ARM::MRRC:
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 4);
|
|
return;
|
|
break;
|
|
case ARM::MCRR2:
|
|
case ARM::MRRC2:
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << ", cr";
|
|
printNoHashImmediate(MI, 4);
|
|
return;
|
|
break;
|
|
case ARM::MLA:
|
|
case ARM::SMLAL:
|
|
case ARM::SMULL:
|
|
case ARM::UMLAL:
|
|
case ARM::UMULL:
|
|
case ARM::VBIFd:
|
|
case ARM::VBIFq:
|
|
case ARM::VBITd:
|
|
case ARM::VBITq:
|
|
case ARM::VBSLd:
|
|
case ARM::VBSLq:
|
|
case ARM::VSLIv16i8:
|
|
case ARM::VSLIv1i64:
|
|
case ARM::VSLIv2i32:
|
|
case ARM::VSLIv2i64:
|
|
case ARM::VSLIv4i16:
|
|
case ARM::VSLIv4i32:
|
|
case ARM::VSLIv8i16:
|
|
case ARM::VSLIv8i8:
|
|
case ARM::VSRIv16i8:
|
|
case ARM::VSRIv1i64:
|
|
case ARM::VSRIv2i32:
|
|
case ARM::VSRIv2i64:
|
|
case ARM::VSRIv4i16:
|
|
case ARM::VSRIv4i32:
|
|
case ARM::VSRIv8i16:
|
|
case ARM::VSRIv8i8:
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
return;
|
|
break;
|
|
case ARM::MLS:
|
|
case ARM::PKHBT:
|
|
case ARM::PKHTB:
|
|
case ARM::SBFX:
|
|
case ARM::SMLABB:
|
|
case ARM::SMLABT:
|
|
case ARM::SMLAD:
|
|
case ARM::SMLADX:
|
|
case ARM::SMLALBB:
|
|
case ARM::SMLALBT:
|
|
case ARM::SMLALD:
|
|
case ARM::SMLALDX:
|
|
case ARM::SMLALTB:
|
|
case ARM::SMLALTT:
|
|
case ARM::SMLATB:
|
|
case ARM::SMLATT:
|
|
case ARM::SMLAWB:
|
|
case ARM::SMLAWT:
|
|
case ARM::SMLSD:
|
|
case ARM::SMLSDX:
|
|
case ARM::SMLSLD:
|
|
case ARM::SMLSLDX:
|
|
case ARM::SMMLA:
|
|
case ARM::SMMLAR:
|
|
case ARM::SMMLS:
|
|
case ARM::SMMLSR:
|
|
case ARM::SSATasr:
|
|
case ARM::SSATlsl:
|
|
case ARM::SXTAB16rr_rot:
|
|
case ARM::SXTABrr_rot:
|
|
case ARM::SXTAHrr_rot:
|
|
case ARM::UBFX:
|
|
case ARM::UMAAL:
|
|
case ARM::USADA8:
|
|
case ARM::USATasr:
|
|
case ARM::USATlsl:
|
|
case ARM::UXTAB16rr_rot:
|
|
case ARM::UXTABrr_rot:
|
|
case ARM::UXTAHrr_rot:
|
|
case ARM::VEXTd16:
|
|
case ARM::VEXTd32:
|
|
case ARM::VEXTd8:
|
|
case ARM::VEXTdf:
|
|
case ARM::VEXTq16:
|
|
case ARM::VEXTq32:
|
|
case ARM::VEXTq8:
|
|
case ARM::VEXTqf:
|
|
case ARM::VMOVRRS:
|
|
case ARM::VMOVSRR:
|
|
case ARM::t2BFI:
|
|
case ARM::t2MLA:
|
|
case ARM::t2MLS:
|
|
case ARM::t2PKHBT:
|
|
case ARM::t2PKHTB:
|
|
case ARM::t2SBFX:
|
|
case ARM::t2SMLABB:
|
|
case ARM::t2SMLABT:
|
|
case ARM::t2SMLAD:
|
|
case ARM::t2SMLADX:
|
|
case ARM::t2SMLAL:
|
|
case ARM::t2SMLALBB:
|
|
case ARM::t2SMLALBT:
|
|
case ARM::t2SMLALD:
|
|
case ARM::t2SMLALDX:
|
|
case ARM::t2SMLALTB:
|
|
case ARM::t2SMLALTT:
|
|
case ARM::t2SMLATB:
|
|
case ARM::t2SMLATT:
|
|
case ARM::t2SMLAWB:
|
|
case ARM::t2SMLAWT:
|
|
case ARM::t2SMLSD:
|
|
case ARM::t2SMLSDX:
|
|
case ARM::t2SMLSLD:
|
|
case ARM::t2SMLSLDX:
|
|
case ARM::t2SMMLA:
|
|
case ARM::t2SMMLAR:
|
|
case ARM::t2SMMLS:
|
|
case ARM::t2SMMLSR:
|
|
case ARM::t2SMULL:
|
|
case ARM::t2SSATasr:
|
|
case ARM::t2SSATlsl:
|
|
case ARM::t2SXTAB16rr_rot:
|
|
case ARM::t2SXTABrr_rot:
|
|
case ARM::t2SXTAHrr_rot:
|
|
case ARM::t2UBFX:
|
|
case ARM::t2UMAAL:
|
|
case ARM::t2UMLAL:
|
|
case ARM::t2UMULL:
|
|
case ARM::t2USADA8:
|
|
case ARM::t2USATasr:
|
|
case ARM::t2USATlsl:
|
|
case ARM::t2UXTAB16rr_rot:
|
|
case ARM::t2UXTABrr_rot:
|
|
case ARM::t2UXTAHrr_rot:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
switch (MI->getOpcode()) {
|
|
case ARM::MLS:
|
|
case ARM::SBFX:
|
|
case ARM::SMLABB:
|
|
case ARM::SMLABT:
|
|
case ARM::SMLAD:
|
|
case ARM::SMLADX:
|
|
case ARM::SMLALBB:
|
|
case ARM::SMLALBT:
|
|
case ARM::SMLALD:
|
|
case ARM::SMLALDX:
|
|
case ARM::SMLALTB:
|
|
case ARM::SMLALTT:
|
|
case ARM::SMLATB:
|
|
case ARM::SMLATT:
|
|
case ARM::SMLAWB:
|
|
case ARM::SMLAWT:
|
|
case ARM::SMLSD:
|
|
case ARM::SMLSDX:
|
|
case ARM::SMLSLD:
|
|
case ARM::SMLSLDX:
|
|
case ARM::SMMLA:
|
|
case ARM::SMMLAR:
|
|
case ARM::SMMLS:
|
|
case ARM::SMMLSR:
|
|
case ARM::UBFX:
|
|
case ARM::UMAAL:
|
|
case ARM::USADA8:
|
|
case ARM::VEXTd16:
|
|
case ARM::VEXTd32:
|
|
case ARM::VEXTd8:
|
|
case ARM::VEXTdf:
|
|
case ARM::VEXTq16:
|
|
case ARM::VEXTq32:
|
|
case ARM::VEXTq8:
|
|
case ARM::VEXTqf:
|
|
case ARM::VMOVRRS:
|
|
case ARM::VMOVSRR:
|
|
case ARM::t2BFI:
|
|
case ARM::t2MLA:
|
|
case ARM::t2MLS:
|
|
case ARM::t2SBFX:
|
|
case ARM::t2SMLABB:
|
|
case ARM::t2SMLABT:
|
|
case ARM::t2SMLAD:
|
|
case ARM::t2SMLADX:
|
|
case ARM::t2SMLAL:
|
|
case ARM::t2SMLALBB:
|
|
case ARM::t2SMLALBT:
|
|
case ARM::t2SMLALD:
|
|
case ARM::t2SMLALDX:
|
|
case ARM::t2SMLALTB:
|
|
case ARM::t2SMLALTT:
|
|
case ARM::t2SMLATB:
|
|
case ARM::t2SMLATT:
|
|
case ARM::t2SMLAWB:
|
|
case ARM::t2SMLAWT:
|
|
case ARM::t2SMLSD:
|
|
case ARM::t2SMLSDX:
|
|
case ARM::t2SMLSLD:
|
|
case ARM::t2SMLSLDX:
|
|
case ARM::t2SMMLA:
|
|
case ARM::t2SMMLAR:
|
|
case ARM::t2SMMLS:
|
|
case ARM::t2SMMLSR:
|
|
case ARM::t2SMULL:
|
|
case ARM::t2UBFX:
|
|
case ARM::t2UMAAL:
|
|
case ARM::t2UMLAL:
|
|
case ARM::t2UMULL:
|
|
case ARM::t2USADA8: O << ", "; break;
|
|
case ARM::PKHBT:
|
|
case ARM::SSATlsl:
|
|
case ARM::USATlsl:
|
|
case ARM::t2PKHBT:
|
|
case ARM::t2SSATlsl:
|
|
case ARM::t2USATlsl: O << ", lsl "; break;
|
|
case ARM::PKHTB:
|
|
case ARM::SSATasr:
|
|
case ARM::USATasr:
|
|
case ARM::t2PKHTB:
|
|
case ARM::t2SSATasr:
|
|
case ARM::t2USATasr: O << ", asr "; break;
|
|
case ARM::SXTAB16rr_rot:
|
|
case ARM::SXTABrr_rot:
|
|
case ARM::SXTAHrr_rot:
|
|
case ARM::UXTAB16rr_rot:
|
|
case ARM::UXTABrr_rot:
|
|
case ARM::UXTAHrr_rot:
|
|
case ARM::t2SXTAB16rr_rot:
|
|
case ARM::t2SXTABrr_rot:
|
|
case ARM::t2SXTAHrr_rot:
|
|
case ARM::t2UXTAB16rr_rot:
|
|
case ARM::t2UXTABrr_rot:
|
|
case ARM::t2UXTAHrr_rot: O << ", ror "; break;
|
|
}
|
|
printOperand(MI, 3);
|
|
return;
|
|
break;
|
|
case ARM::MOVi32imm:
|
|
case ARM::t2MOVi32imm:
|
|
O << ", ";
|
|
printOperand(MI, 1, "lo16");
|
|
O << "\n\tmovt";
|
|
printPredicateOperand(MI, 2);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1, "hi16");
|
|
return;
|
|
break;
|
|
case ARM::MOVsra_flag:
|
|
case ARM::MOVsrl_flag:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
switch (MI->getOpcode()) {
|
|
case ARM::MOVsra_flag: O << ", asr #1"; break;
|
|
case ARM::MOVsrl_flag: O << ", lsr #1"; break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::STRB_PRE:
|
|
case ARM::STRH_PRE:
|
|
case ARM::STR_PRE:
|
|
case ARM::t2STRB_PRE:
|
|
case ARM::t2STRH_PRE:
|
|
case ARM::t2STR_PRE:
|
|
O << ", [";
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::STRB_PRE:
|
|
case ARM::STR_PRE: printAddrMode2OffsetOperand(MI, 3); break;
|
|
case ARM::STRH_PRE: printAddrMode3OffsetOperand(MI, 3); break;
|
|
case ARM::t2STRB_PRE:
|
|
case ARM::t2STRH_PRE:
|
|
case ARM::t2STR_PRE: printT2AddrModeImm8OffsetOperand(MI, 3); break;
|
|
}
|
|
O << "]!";
|
|
return;
|
|
break;
|
|
case ARM::STRD_PRE:
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << ", [";
|
|
printOperand(MI, 3);
|
|
O << ", ";
|
|
printAddrMode3OffsetOperand(MI, 4);
|
|
O << "]!";
|
|
return;
|
|
break;
|
|
case ARM::STREXD:
|
|
case ARM::t2STREXD:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << ", [";
|
|
printOperand(MI, 3);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::SXTB16r_rot:
|
|
case ARM::SXTBr_rot:
|
|
case ARM::SXTHr_rot:
|
|
case ARM::UXTB16r_rot:
|
|
case ARM::UXTBr_rot:
|
|
case ARM::UXTHr_rot:
|
|
case ARM::t2SXTB16r_rot:
|
|
case ARM::t2UXTB16r_rot:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ror ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::VABDfd:
|
|
case ARM::VABDfq:
|
|
case ARM::VACGEd:
|
|
case ARM::VACGEq:
|
|
case ARM::VACGTd:
|
|
case ARM::VACGTq:
|
|
case ARM::VADDD:
|
|
case ARM::VADDS:
|
|
case ARM::VADDfd:
|
|
case ARM::VADDfd_sfp:
|
|
case ARM::VADDfq:
|
|
case ARM::VCEQfd:
|
|
case ARM::VCEQfq:
|
|
case ARM::VCGEfd:
|
|
case ARM::VCGEfq:
|
|
case ARM::VCGTfd:
|
|
case ARM::VCGTfq:
|
|
case ARM::VDIVD:
|
|
case ARM::VDIVS:
|
|
case ARM::VMAXfd:
|
|
case ARM::VMAXfd_sfp:
|
|
case ARM::VMAXfq:
|
|
case ARM::VMINfd:
|
|
case ARM::VMINfd_sfp:
|
|
case ARM::VMINfq:
|
|
case ARM::VMULD:
|
|
case ARM::VMULS:
|
|
case ARM::VMULfd:
|
|
case ARM::VMULfd_sfp:
|
|
case ARM::VMULfq:
|
|
case ARM::VNMULD:
|
|
case ARM::VNMULS:
|
|
case ARM::VPADDf:
|
|
case ARM::VPMAXf:
|
|
case ARM::VPMINf:
|
|
case ARM::VRECPSfd:
|
|
case ARM::VRECPSfq:
|
|
case ARM::VRSQRTSfd:
|
|
case ARM::VRSQRTSfq:
|
|
case ARM::VSUBD:
|
|
case ARM::VSUBS:
|
|
case ARM::VSUBfd:
|
|
case ARM::VSUBfd_sfp:
|
|
case ARM::VSUBfq:
|
|
case ARM::t2ADCSrr:
|
|
case ARM::t2ADCSrs:
|
|
case ARM::t2ADCrr:
|
|
case ARM::t2ADCrs:
|
|
case ARM::t2ADDSri:
|
|
case ARM::t2ADDSrr:
|
|
case ARM::t2ADDSrs:
|
|
case ARM::t2ADDrSPi:
|
|
case ARM::t2ADDrSPs:
|
|
case ARM::t2ADDri:
|
|
case ARM::t2ADDrr:
|
|
case ARM::t2ADDrs:
|
|
case ARM::t2ANDrr:
|
|
case ARM::t2ANDrs:
|
|
case ARM::t2ASRri:
|
|
case ARM::t2ASRrr:
|
|
case ARM::t2BICrr:
|
|
case ARM::t2BICrs:
|
|
case ARM::t2EORrr:
|
|
case ARM::t2EORrs:
|
|
case ARM::t2LSLri:
|
|
case ARM::t2LSLrr:
|
|
case ARM::t2LSRri:
|
|
case ARM::t2LSRrr:
|
|
case ARM::t2ORRrr:
|
|
case ARM::t2ORRrs:
|
|
case ARM::t2RORri:
|
|
case ARM::t2RORrr:
|
|
case ARM::t2RSBri:
|
|
case ARM::t2SBCSrr:
|
|
case ARM::t2SBCSrs:
|
|
case ARM::t2SBCrr:
|
|
case ARM::t2SBCrs:
|
|
case ARM::t2SUBSri:
|
|
case ARM::t2SUBSrr:
|
|
case ARM::t2SUBSrs:
|
|
case ARM::t2SUBrSPi:
|
|
case ARM::t2SUBri:
|
|
case ARM::t2SUBrr:
|
|
case ARM::t2SUBrs:
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::VABDfd:
|
|
case ARM::VABDfq:
|
|
case ARM::VACGEd:
|
|
case ARM::VACGEq:
|
|
case ARM::VACGTd:
|
|
case ARM::VACGTq:
|
|
case ARM::VADDD:
|
|
case ARM::VADDS:
|
|
case ARM::VADDfd:
|
|
case ARM::VADDfd_sfp:
|
|
case ARM::VADDfq:
|
|
case ARM::VCEQfd:
|
|
case ARM::VCEQfq:
|
|
case ARM::VCGEfd:
|
|
case ARM::VCGEfq:
|
|
case ARM::VCGTfd:
|
|
case ARM::VCGTfq:
|
|
case ARM::VDIVD:
|
|
case ARM::VDIVS:
|
|
case ARM::VMAXfd:
|
|
case ARM::VMAXfd_sfp:
|
|
case ARM::VMAXfq:
|
|
case ARM::VMINfd:
|
|
case ARM::VMINfd_sfp:
|
|
case ARM::VMINfq:
|
|
case ARM::VMULD:
|
|
case ARM::VMULS:
|
|
case ARM::VMULfd:
|
|
case ARM::VMULfd_sfp:
|
|
case ARM::VMULfq:
|
|
case ARM::VNMULD:
|
|
case ARM::VNMULS:
|
|
case ARM::VPADDf:
|
|
case ARM::VPMAXf:
|
|
case ARM::VPMINf:
|
|
case ARM::VRECPSfd:
|
|
case ARM::VRECPSfq:
|
|
case ARM::VRSQRTSfd:
|
|
case ARM::VRSQRTSfq:
|
|
case ARM::VSUBD:
|
|
case ARM::VSUBS:
|
|
case ARM::VSUBfd:
|
|
case ARM::VSUBfd_sfp:
|
|
case ARM::VSUBfq:
|
|
case ARM::t2ADCSrr:
|
|
case ARM::t2ADCrr:
|
|
case ARM::t2ADDSri:
|
|
case ARM::t2ADDSrr:
|
|
case ARM::t2ADDrSPi:
|
|
case ARM::t2ADDri:
|
|
case ARM::t2ADDrr:
|
|
case ARM::t2ANDrr:
|
|
case ARM::t2ASRri:
|
|
case ARM::t2ASRrr:
|
|
case ARM::t2BICrr:
|
|
case ARM::t2EORrr:
|
|
case ARM::t2LSLri:
|
|
case ARM::t2LSLrr:
|
|
case ARM::t2LSRri:
|
|
case ARM::t2LSRrr:
|
|
case ARM::t2ORRrr:
|
|
case ARM::t2RORri:
|
|
case ARM::t2RORrr:
|
|
case ARM::t2RSBri:
|
|
case ARM::t2SBCSrr:
|
|
case ARM::t2SBCrr:
|
|
case ARM::t2SUBSri:
|
|
case ARM::t2SUBSrr:
|
|
case ARM::t2SUBrSPi:
|
|
case ARM::t2SUBri:
|
|
case ARM::t2SUBrr: printOperand(MI, 2); break;
|
|
case ARM::t2ADCSrs:
|
|
case ARM::t2ADCrs:
|
|
case ARM::t2ADDSrs:
|
|
case ARM::t2ADDrSPs:
|
|
case ARM::t2ADDrs:
|
|
case ARM::t2ANDrs:
|
|
case ARM::t2BICrs:
|
|
case ARM::t2EORrs:
|
|
case ARM::t2ORRrs:
|
|
case ARM::t2SBCSrs:
|
|
case ARM::t2SBCrs:
|
|
case ARM::t2SUBSrs:
|
|
case ARM::t2SUBrs: printT2SOOperand(MI, 2); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::VCEQzv2f32:
|
|
case ARM::VCEQzv4f32:
|
|
case ARM::VCGEzv2f32:
|
|
case ARM::VCGEzv4f32:
|
|
case ARM::VCGTzv2f32:
|
|
case ARM::VCGTzv4f32:
|
|
case ARM::VCLEzv2f32:
|
|
case ARM::VCLEzv4f32:
|
|
case ARM::VCLTzv2f32:
|
|
case ARM::VCLTzv4f32:
|
|
printOperand(MI, 1);
|
|
O << ", #0";
|
|
return;
|
|
break;
|
|
case ARM::VDUPLN16d:
|
|
case ARM::VDUPLN16q:
|
|
case ARM::VDUPLN32d:
|
|
case ARM::VDUPLN32q:
|
|
case ARM::VDUPLN8d:
|
|
case ARM::VDUPLN8q:
|
|
case ARM::VDUPLNfd:
|
|
case ARM::VDUPLNfq:
|
|
case ARM::VGETLNi32:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 2);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::VGETLNs16:
|
|
case ARM::VGETLNs8:
|
|
case ARM::VGETLNu16:
|
|
case ARM::VGETLNu8:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 2);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::VLD1d16:
|
|
case ARM::VLD1d32:
|
|
case ARM::VLD1d64:
|
|
case ARM::VLD1d8:
|
|
case ARM::VLD1df:
|
|
case ARM::VST1d16:
|
|
case ARM::VST1d32:
|
|
case ARM::VST1d64:
|
|
case ARM::VST1d8:
|
|
case ARM::VST1df:
|
|
case ARM::VST3q16a:
|
|
case ARM::VST3q16b:
|
|
case ARM::VST3q32a:
|
|
case ARM::VST3q32b:
|
|
case ARM::VST3q8a:
|
|
case ARM::VST3q8b:
|
|
O << "}, ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::VLD1d16:
|
|
case ARM::VLD1d32:
|
|
case ARM::VLD1d64:
|
|
case ARM::VLD1d8:
|
|
case ARM::VLD1df:
|
|
case ARM::VST3q16a:
|
|
case ARM::VST3q16b:
|
|
case ARM::VST3q32a:
|
|
case ARM::VST3q32b:
|
|
case ARM::VST3q8a:
|
|
case ARM::VST3q8b: printAddrMode6Operand(MI, 1); break;
|
|
case ARM::VST1d16:
|
|
case ARM::VST1d32:
|
|
case ARM::VST1d64:
|
|
case ARM::VST1d8:
|
|
case ARM::VST1df: printAddrMode6Operand(MI, 0); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::VLD1d16Q:
|
|
case ARM::VLD1d32Q:
|
|
case ARM::VLD1d8Q:
|
|
case ARM::VLD2q16:
|
|
case ARM::VLD2q32:
|
|
case ARM::VLD2q8:
|
|
case ARM::VLD4d16:
|
|
case ARM::VLD4d32:
|
|
case ARM::VLD4d64:
|
|
case ARM::VLD4d8:
|
|
case ARM::VLD4q16a:
|
|
case ARM::VLD4q16b:
|
|
case ARM::VLD4q32a:
|
|
case ARM::VLD4q32b:
|
|
case ARM::VLD4q8a:
|
|
case ARM::VLD4q8b:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << "}, ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::VLD1d16Q:
|
|
case ARM::VLD1d32Q:
|
|
case ARM::VLD1d8Q:
|
|
case ARM::VLD2q16:
|
|
case ARM::VLD2q32:
|
|
case ARM::VLD2q8:
|
|
case ARM::VLD4d16:
|
|
case ARM::VLD4d32:
|
|
case ARM::VLD4d64:
|
|
case ARM::VLD4d8: printAddrMode6Operand(MI, 4); break;
|
|
case ARM::VLD4q16a:
|
|
case ARM::VLD4q16b:
|
|
case ARM::VLD4q32a:
|
|
case ARM::VLD4q32b:
|
|
case ARM::VLD4q8a:
|
|
case ARM::VLD4q8b: printAddrMode6Operand(MI, 5); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::VLD1d16T:
|
|
case ARM::VLD1d32T:
|
|
case ARM::VLD1d8T:
|
|
case ARM::VLD3d16:
|
|
case ARM::VLD3d32:
|
|
case ARM::VLD3d64:
|
|
case ARM::VLD3d8:
|
|
case ARM::VLD3q16a:
|
|
case ARM::VLD3q16b:
|
|
case ARM::VLD3q32a:
|
|
case ARM::VLD3q32b:
|
|
case ARM::VLD3q8a:
|
|
case ARM::VLD3q8b:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << "}, ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::VLD1d16T:
|
|
case ARM::VLD1d32T:
|
|
case ARM::VLD1d8T:
|
|
case ARM::VLD3d16:
|
|
case ARM::VLD3d32:
|
|
case ARM::VLD3d64:
|
|
case ARM::VLD3d8: printAddrMode6Operand(MI, 3); break;
|
|
case ARM::VLD3q16a:
|
|
case ARM::VLD3q16b:
|
|
case ARM::VLD3q32a:
|
|
case ARM::VLD3q32b:
|
|
case ARM::VLD3q8a:
|
|
case ARM::VLD3q8b: printAddrMode6Operand(MI, 4); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::VLD2LNd16:
|
|
case ARM::VLD2LNd32:
|
|
case ARM::VLD2LNd8:
|
|
case ARM::VLD2LNq16a:
|
|
case ARM::VLD2LNq16b:
|
|
case ARM::VLD2LNq32a:
|
|
case ARM::VLD2LNq32b:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 8);
|
|
O << "], ";
|
|
printOperand(MI, 1);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 8);
|
|
O << "]}, ";
|
|
printAddrMode6Operand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::VLD2d16:
|
|
case ARM::VLD2d16D:
|
|
case ARM::VLD2d32:
|
|
case ARM::VLD2d32D:
|
|
case ARM::VLD2d64:
|
|
case ARM::VLD2d8:
|
|
case ARM::VLD2d8D:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << "}, ";
|
|
printAddrMode6Operand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::VLD3LNd16:
|
|
case ARM::VLD3LNd32:
|
|
case ARM::VLD3LNd8:
|
|
case ARM::VLD3LNq16a:
|
|
case ARM::VLD3LNq16b:
|
|
case ARM::VLD3LNq32a:
|
|
case ARM::VLD3LNq32b:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 10);
|
|
O << "], ";
|
|
printOperand(MI, 1);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 10);
|
|
O << "], ";
|
|
printOperand(MI, 2);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 10);
|
|
O << "]}, ";
|
|
printAddrMode6Operand(MI, 3);
|
|
return;
|
|
break;
|
|
case ARM::VLD4LNd16:
|
|
case ARM::VLD4LNd32:
|
|
case ARM::VLD4LNd8:
|
|
case ARM::VLD4LNq16a:
|
|
case ARM::VLD4LNq16b:
|
|
case ARM::VLD4LNq32a:
|
|
case ARM::VLD4LNq32b:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 12);
|
|
O << "], ";
|
|
printOperand(MI, 1);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 12);
|
|
O << "], ";
|
|
printOperand(MI, 2);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 12);
|
|
O << "], ";
|
|
printOperand(MI, 3);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 12);
|
|
O << "]}, ";
|
|
printAddrMode6Operand(MI, 4);
|
|
return;
|
|
break;
|
|
case ARM::VMLAD:
|
|
case ARM::VMLAS:
|
|
case ARM::VMLAfd:
|
|
case ARM::VMLAfq:
|
|
case ARM::VMLSD:
|
|
case ARM::VMLSS:
|
|
case ARM::VMLSfd:
|
|
case ARM::VMLSfq:
|
|
case ARM::VNMLAD:
|
|
case ARM::VNMLAS:
|
|
case ARM::VNMLSD:
|
|
case ARM::VNMLSS:
|
|
case ARM::t2MOVCCasr:
|
|
case ARM::t2MOVCClsl:
|
|
case ARM::t2MOVCClsr:
|
|
case ARM::t2MOVCCror:
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
return;
|
|
break;
|
|
case ARM::VMLALslsv2i32:
|
|
case ARM::VMLALslsv4i16:
|
|
case ARM::VMLALsluv2i32:
|
|
case ARM::VMLALsluv4i16:
|
|
case ARM::VMLAslv2i32:
|
|
case ARM::VMLAslv4i16:
|
|
case ARM::VMLAslv4i32:
|
|
case ARM::VMLAslv8i16:
|
|
case ARM::VMLSLslsv2i32:
|
|
case ARM::VMLSLslsv4i16:
|
|
case ARM::VMLSLsluv2i32:
|
|
case ARM::VMLSLsluv4i16:
|
|
case ARM::VMLSslv2i32:
|
|
case ARM::VMLSslv4i16:
|
|
case ARM::VMLSslv4i32:
|
|
case ARM::VMLSslv8i16:
|
|
case ARM::VQDMLALslv2i32:
|
|
case ARM::VQDMLALslv4i16:
|
|
case ARM::VQDMLSLslv2i32:
|
|
case ARM::VQDMLSLslv4i16:
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 4);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::VMLAslfd:
|
|
case ARM::VMLAslfq:
|
|
case ARM::VMLSslfd:
|
|
case ARM::VMLSslfq:
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 4);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::VMULLslsv2i32:
|
|
case ARM::VMULLslsv4i16:
|
|
case ARM::VMULLsluv2i32:
|
|
case ARM::VMULLsluv4i16:
|
|
case ARM::VMULslv2i32:
|
|
case ARM::VMULslv4i16:
|
|
case ARM::VMULslv4i32:
|
|
case ARM::VMULslv8i16:
|
|
case ARM::VQDMULHslv2i32:
|
|
case ARM::VQDMULHslv4i16:
|
|
case ARM::VQDMULHslv4i32:
|
|
case ARM::VQDMULHslv8i16:
|
|
case ARM::VQDMULLslv2i32:
|
|
case ARM::VQDMULLslv4i16:
|
|
case ARM::VQRDMULHslv2i32:
|
|
case ARM::VQRDMULHslv4i16:
|
|
case ARM::VQRDMULHslv4i32:
|
|
case ARM::VQRDMULHslv8i16:
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 3);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::VMULslfd:
|
|
case ARM::VMULslfq:
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 3);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::VSETLNi16:
|
|
case ARM::VSETLNi32:
|
|
case ARM::VSETLNi8:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 3);
|
|
O << "], ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::VST1d16Q:
|
|
case ARM::VST1d32Q:
|
|
case ARM::VST1d8Q:
|
|
case ARM::VST2q16:
|
|
case ARM::VST2q32:
|
|
case ARM::VST2q8:
|
|
case ARM::VST4d16:
|
|
case ARM::VST4d32:
|
|
case ARM::VST4d64:
|
|
case ARM::VST4d8:
|
|
O << ", ";
|
|
printOperand(MI, 5);
|
|
O << ", ";
|
|
printOperand(MI, 6);
|
|
O << ", ";
|
|
printOperand(MI, 7);
|
|
O << "}, ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case ARM::VST1d16T:
|
|
case ARM::VST1d32T:
|
|
case ARM::VST1d8T:
|
|
case ARM::VST3d16:
|
|
case ARM::VST3d32:
|
|
case ARM::VST3d64:
|
|
case ARM::VST3d8:
|
|
O << ", ";
|
|
printOperand(MI, 5);
|
|
O << ", ";
|
|
printOperand(MI, 6);
|
|
O << "}, ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case ARM::VST2LNd16:
|
|
case ARM::VST2LNd32:
|
|
case ARM::VST2LNd8:
|
|
case ARM::VST2LNq16a:
|
|
case ARM::VST2LNq16b:
|
|
case ARM::VST2LNq32a:
|
|
case ARM::VST2LNq32b:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 6);
|
|
O << "], ";
|
|
printOperand(MI, 5);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 6);
|
|
O << "]}, ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case ARM::VST2d16:
|
|
case ARM::VST2d16D:
|
|
case ARM::VST2d32:
|
|
case ARM::VST2d32D:
|
|
case ARM::VST2d64:
|
|
case ARM::VST2d8:
|
|
case ARM::VST2d8D:
|
|
O << ", ";
|
|
printOperand(MI, 5);
|
|
O << "}, ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case ARM::VST3LNd16:
|
|
case ARM::VST3LNd32:
|
|
case ARM::VST3LNd8:
|
|
case ARM::VST3LNq16a:
|
|
case ARM::VST3LNq16b:
|
|
case ARM::VST3LNq32a:
|
|
case ARM::VST3LNq32b:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 7);
|
|
O << "], ";
|
|
printOperand(MI, 5);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 7);
|
|
O << "], ";
|
|
printOperand(MI, 6);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 7);
|
|
O << "]}, ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case ARM::VST4LNd16:
|
|
case ARM::VST4LNd32:
|
|
case ARM::VST4LNd8:
|
|
case ARM::VST4LNq16a:
|
|
case ARM::VST4LNq16b:
|
|
case ARM::VST4LNq32a:
|
|
case ARM::VST4LNq32b:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 8);
|
|
O << "], ";
|
|
printOperand(MI, 5);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 8);
|
|
O << "], ";
|
|
printOperand(MI, 6);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 8);
|
|
O << "], ";
|
|
printOperand(MI, 7);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 8);
|
|
O << "]}, ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case ARM::VST4q16a:
|
|
case ARM::VST4q16b:
|
|
case ARM::VST4q32a:
|
|
case ARM::VST4q32b:
|
|
case ARM::VST4q8a:
|
|
case ARM::VST4q8b:
|
|
O << ", ";
|
|
printOperand(MI, 8);
|
|
O << "}, ";
|
|
printAddrMode6Operand(MI, 1);
|
|
return;
|
|
break;
|
|
case ARM::VTBL1:
|
|
O << ", {";
|
|
printOperand(MI, 1);
|
|
O << "}, ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::VTBL2:
|
|
O << ", {";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << "}, ";
|
|
printOperand(MI, 3);
|
|
return;
|
|
break;
|
|
case ARM::VTBL3:
|
|
O << ", {";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << "}, ";
|
|
printOperand(MI, 4);
|
|
return;
|
|
break;
|
|
case ARM::VTBL4:
|
|
O << ", {";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << ", ";
|
|
printOperand(MI, 4);
|
|
O << "}, ";
|
|
printOperand(MI, 5);
|
|
return;
|
|
break;
|
|
case ARM::VTBX1:
|
|
O << ", {";
|
|
printOperand(MI, 2);
|
|
O << "}, ";
|
|
printOperand(MI, 3);
|
|
return;
|
|
break;
|
|
case ARM::VTBX2:
|
|
O << ", {";
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << "}, ";
|
|
printOperand(MI, 4);
|
|
return;
|
|
break;
|
|
case ARM::VTBX3:
|
|
O << ", {";
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << ", ";
|
|
printOperand(MI, 4);
|
|
O << "}, ";
|
|
printOperand(MI, 5);
|
|
return;
|
|
break;
|
|
case ARM::VTBX4:
|
|
O << ", {";
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << ", ";
|
|
printOperand(MI, 4);
|
|
O << ", ";
|
|
printOperand(MI, 5);
|
|
O << "}, ";
|
|
printOperand(MI, 6);
|
|
return;
|
|
break;
|
|
case ARM::t2LDRpci_pic:
|
|
case ARM::tLDRpci_pic:
|
|
O << "\n";
|
|
printPCLabel(MI, 2);
|
|
O << ":\n\tadd\t";
|
|
printOperand(MI, 0);
|
|
O << ", pc";
|
|
return;
|
|
break;
|
|
case ARM::t2LEApcrelJT:
|
|
O << '_';
|
|
printNoHashImmediate(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::t2MOVrx:
|
|
case ARM::t2MVNi:
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case ARM::t2SXTBr_rot:
|
|
case ARM::t2SXTHr_rot:
|
|
case ARM::t2UXTBr_rot:
|
|
case ARM::t2UXTHr_rot:
|
|
printOperand(MI, 1);
|
|
O << ", ror ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::tLEApcrel:
|
|
O << ", #";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case ARM::tLEApcrelJT:
|
|
O << ", #";
|
|
printOperand(MI, 1);
|
|
O << '_';
|
|
printNoHashImmediate(MI, 2);
|
|
return;
|
|
break;
|
|
}
|
|
return;
|
|
}
|
|
|
|
|
|
/// getRegisterName - This method is automatically generated by tblgen
|
|
/// from the register set description. This returns the assembler name
|
|
/// for the specified register.
|
|
const char *ARMAsmPrinter::getRegisterName(unsigned RegNo) {
|
|
assert(RegNo && RegNo < 100 && "Invalid register number!");
|
|
|
|
static const unsigned RegAsmOffset[] = {
|
|
0, 5, 8, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51,
|
|
54, 58, 62, 66, 70, 74, 78, 82, 86, 90, 94, 97, 101, 105,
|
|
108, 111, 114, 117, 120, 123, 129, 132, 135, 138, 141, 145, 149, 153,
|
|
157, 161, 165, 168, 171, 174, 177, 180, 183, 186, 189, 192, 195, 199,
|
|
203, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237, 241, 245,
|
|
249, 253, 257, 261, 265, 269, 273, 277, 280, 284, 288, 292, 296, 300,
|
|
304, 308, 312, 316, 320, 323, 327, 331, 334, 337, 340, 343, 346, 349,
|
|
358, 0
|
|
};
|
|
|
|
const char *AsmStrs =
|
|
"cpsr\000d0\000d1\000d10\000d11\000d12\000d13\000d14\000d15\000d16\000d1"
|
|
"7\000d18\000d19\000d2\000d20\000d21\000d22\000d23\000d24\000d25\000d26\000"
|
|
"d27\000d28\000d29\000d3\000d30\000d31\000d4\000d5\000d6\000d7\000d8\000"
|
|
"d9\000fpscr\000lr\000pc\000q0\000q1\000q10\000q11\000q12\000q13\000q14\000"
|
|
"q15\000q2\000q3\000q4\000q5\000q6\000q7\000q8\000q9\000r0\000r1\000r10\000"
|
|
"r11\000r12\000r2\000r3\000r4\000r5\000r6\000r7\000r8\000r9\000s0\000s1\000"
|
|
"s10\000s11\000s12\000s13\000s14\000s15\000s16\000s17\000s18\000s19\000s"
|
|
"2\000s20\000s21\000s22\000s23\000s24\000s25\000s26\000s27\000s28\000s29"
|
|
"\000s3\000s30\000s31\000s4\000s5\000s6\000s7\000s8\000s9\000sINVALID\000"
|
|
"sp\000";
|
|
return AsmStrs+RegAsmOffset[RegNo-1];
|
|
}
|
|
|
|
|
|
#ifdef GET_INSTRUCTION_NAME
|
|
#undef GET_INSTRUCTION_NAME
|
|
|
|
/// getInstructionName: This method is automatically generated by tblgen
|
|
/// from the instruction set description. This returns the enum name of the
|
|
/// specified instruction.
|
|
const char *ARMAsmPrinter::getInstructionName(unsigned Opcode) {
|
|
assert(Opcode < 1945 && "Invalid instruction number!");
|
|
|
|
static const unsigned InstAsmOffset[] = {
|
|
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 138,
|
|
146, 154, 160, 166, 172, 179, 186, 193, 199, 205, 211, 228, 243, 249,
|
|
255, 261, 281, 301, 320, 340, 360, 379, 399, 419, 438, 459, 480, 500,
|
|
519, 538, 556, 576, 596, 615, 635, 655, 674, 690, 706, 721, 723, 727,
|
|
731, 737, 743, 749, 754, 757, 761, 767, 775, 780, 790, 796, 805, 812,
|
|
819, 822, 826, 833, 838, 842, 846, 851, 857, 861, 868, 875, 882, 888,
|
|
894, 900, 907, 914, 921, 937, 941, 945, 952, 961, 968, 977, 984, 993,
|
|
999, 1006, 1015, 1022, 1031, 1038, 1047, 1053, 1059, 1065, 1071, 1079, 1087, 1094,
|
|
1100, 1117, 1134, 1152, 1170, 1189, 1202, 1215, 1226, 1236, 1248, 1260, 1270, 1279,
|
|
1291, 1303, 1313, 1322, 1333, 1344, 1353, 1361, 1365, 1373, 1377, 1382, 1388, 1398,
|
|
1407, 1412, 1422, 1431, 1437, 1444, 1451, 1458, 1463, 1469, 1479, 1488, 1494, 1501,
|
|
1512, 1522, 1528, 1535, 1546, 1556, 1561, 1570, 1578, 1584, 1593, 1604, 1608, 1613,
|
|
1618, 1624, 1628, 1632, 1639, 1646, 1653, 1661, 1666, 1673, 1685, 1695, 1700, 1706,
|
|
1711, 1723, 1735, 1739, 1744, 1749, 1755, 1759, 1766, 1770, 1775, 1782, 1790, 1794,
|
|
1799, 1804, 1809, 1813, 1819, 1825, 1831, 1838, 1845, 1853, 1861, 1870, 1879, 1886,
|
|
1894, 1902, 1908, 1914, 1920, 1926, 1931, 1936, 1941, 1946, 1951, 1958, 1964, 1969,
|
|
1975, 1981, 1986, 1991, 1998, 2004, 2009, 2013, 2019, 2025, 2029, 2034, 2041, 2048,
|
|
2054, 2060, 2067, 2074, 2080, 2086, 2093, 2099, 2104, 2112, 2120, 2128, 2134, 2140,
|
|
2146, 2151, 2155, 2164, 2173, 2177, 2185, 2192, 2198, 2204, 2212, 2219, 2223, 2230,
|
|
2237, 2243, 2250, 2256, 2264, 2272, 2279, 2287, 2295, 2303, 2310, 2317, 2324, 2331,
|
|
2337, 2344, 2351, 2359, 2365, 2372, 2378, 2385, 2391, 2398, 2404, 2411, 2418, 2425,
|
|
2431, 2438, 2445, 2452, 2459, 2465, 2472, 2476, 2481, 2488, 2496, 2504, 2509, 2516,
|
|
2522, 2535, 2548, 2559, 2569, 2581, 2593, 2603, 2612, 2624, 2636, 2646, 2655, 2666,
|
|
2677, 2686, 2694, 2698, 2702, 2707, 2713, 2723, 2732, 2737, 2747, 2756, 2762, 2769,
|
|
2776, 2783, 2788, 2794, 2804, 2813, 2818, 2827, 2835, 2842, 2849, 2856, 2862, 2868,
|
|
2874, 2878, 2882, 2887, 2897, 2911, 2919, 2931, 2939, 2951, 2959, 2971, 2977, 2987,
|
|
2993, 3003, 3009, 3015, 3021, 3028, 3033, 3039, 3045, 3051, 3058, 3064, 3069, 3074,
|
|
3082, 3089, 3095, 3101, 3109, 3116, 3122, 3128, 3134, 3142, 3149, 3155, 3161, 3169,
|
|
3176, 3182, 3189, 3196, 3204, 3212, 3217, 3224, 3230, 3240, 3254, 3262, 3274, 3282,
|
|
3294, 3302, 3314, 3320, 3330, 3336, 3346, 3358, 3370, 3382, 3394, 3406, 3418, 3429,
|
|
3440, 3451, 3462, 3473, 3483, 3494, 3505, 3516, 3527, 3538, 3548, 3560, 3572, 3584,
|
|
3596, 3608, 3620, 3627, 3634, 3645, 3656, 3667, 3678, 3689, 3699, 3710, 3721, 3732,
|
|
3743, 3754, 3764, 3770, 3776, 3783, 3794, 3801, 3811, 3821, 3831, 3841, 3851, 3860,
|
|
3867, 3874, 3881, 3888, 3894, 3906, 3918, 3929, 3941, 3953, 3965, 3977, 3989, 4001,
|
|
4007, 4019, 4031, 4043, 4055, 4067, 4079, 4086, 4097, 4104, 4114, 4124, 4134, 4144,
|
|
4154, 4164, 4174, 4183, 4189, 4195, 4201, 4207, 4213, 4219, 4225, 4231, 4237, 4243,
|
|
4250, 4257, 4267, 4277, 4287, 4297, 4307, 4316, 4327, 4338, 4349, 4360, 4371, 4382,
|
|
4393, 4403, 4410, 4417, 4428, 4439, 4450, 4461, 4472, 4482, 4493, 4504, 4515, 4526,
|
|
4537, 4547, 4558, 4569, 4580, 4591, 4602, 4613, 4624, 4634, 4641, 4648, 4659, 4670,
|
|
4681, 4692, 4703, 4713, 4724, 4735, 4746, 4757, 4768, 4778, 4789, 4800, 4811, 4822,
|
|
4833, 4844, 4855, 4865, 4876, 4887, 4898, 4909, 4920, 4931, 4942, 4952, 4962, 4972,
|
|
4982, 4992, 5002, 5011, 5022, 5033, 5044, 5055, 5066, 5077, 5088, 5098, 5108, 5118,
|
|
5128, 5138, 5148, 5157, 5163, 5170, 5177, 5185, 5193, 5199, 5206, 5213, 5219, 5225,
|
|
5233, 5241, 5248, 5255, 5263, 5271, 5280, 5293, 5302, 5311, 5324, 5333, 5343, 5353,
|
|
5363, 5373, 5382, 5395, 5404, 5413, 5426, 5435, 5445, 5455, 5465, 5475, 5481, 5487,
|
|
5495, 5503, 5511, 5519, 5526, 5533, 5543, 5553, 5563, 5573, 5582, 5591, 5600, 5609,
|
|
5616, 5624, 5631, 5639, 5645, 5651, 5659, 5667, 5674, 5681, 5689, 5697, 5704, 5711,
|
|
5721, 5731, 5740, 5750, 5759, 5771, 5783, 5795, 5807, 5819, 5830, 5842, 5854, 5866,
|
|
5878, 5890, 5901, 5913, 5925, 5937, 5949, 5961, 5972, 5984, 5996, 6008, 6020, 6032,
|
|
6043, 6051, 6060, 6069, 6077, 6086, 6095, 6103, 6110, 6118, 6126, 6133, 6141, 6149,
|
|
6157, 6164, 6171, 6181, 6191, 6200, 6211, 6222, 6233, 6244, 6252, 6261, 6269, 6278,
|
|
6286, 6293, 6301, 6309, 6317, 6324, 6334, 6344, 6353, 6364, 6375, 6386, 6397, 6405,
|
|
6413, 6421, 6428, 6437, 6446, 6455, 6464, 6472, 6480, 6490, 6500, 6509, 6520, 6531,
|
|
6542, 6553, 6561, 6569, 6577, 6584, 6593, 6602, 6611, 6620, 6628, 6636, 6642, 6648,
|
|
6654, 6660, 6666, 6673, 6684, 6691, 6702, 6713, 6724, 6735, 6746, 6756, 6767, 6778,
|
|
6789, 6800, 6811, 6821, 6828, 6839, 6846, 6857, 6868, 6879, 6890, 6901, 6911, 6922,
|
|
6933, 6944, 6955, 6966, 6976, 6982, 6996, 7010, 7024, 7038, 7050, 7062, 7074, 7086,
|
|
7098, 7110, 7116, 7123, 7130, 7139, 7148, 7160, 7172, 7184, 7196, 7206, 7216, 7226,
|
|
7236, 7246, 7255, 7261, 7275, 7289, 7303, 7317, 7329, 7341, 7353, 7365, 7377, 7389,
|
|
7395, 7402, 7409, 7418, 7427, 7439, 7451, 7463, 7475, 7485, 7495, 7505, 7515, 7525,
|
|
7534, 7540, 7548, 7556, 7566, 7578, 7590, 7602, 7614, 7626, 7638, 7649, 7660, 7670,
|
|
7676, 7684, 7692, 7699, 7705, 7712, 7720, 7728, 7738, 7748, 7758, 7768, 7778, 7788,
|
|
7798, 7807, 7812, 7817, 7823, 7830, 7844, 7858, 7872, 7886, 7898, 7910, 7922, 7934,
|
|
7946, 7958, 7964, 7971, 7982, 7989, 7996, 8003, 8012, 8021, 8033, 8045, 8057, 8069,
|
|
8079, 8089, 8099, 8109, 8119, 8128, 8134, 8140, 8146, 8154, 8160, 8168, 8177, 8184,
|
|
8195, 8204, 8213, 8222, 8231, 8239, 8247, 8254, 8261, 8268, 8275, 8282, 8289, 8295,
|
|
8301, 8307, 8313, 8326, 8339, 8352, 8365, 8378, 8390, 8403, 8416, 8429, 8442, 8455,
|
|
8467, 8480, 8493, 8506, 8519, 8532, 8544, 8557, 8570, 8583, 8596, 8609, 8621, 8628,
|
|
8637, 8646, 8654, 8661, 8670, 8679, 8687, 8696, 8705, 8713, 8720, 8729, 8738, 8746,
|
|
8755, 8764, 8772, 8783, 8794, 8805, 8816, 8827, 8837, 8849, 8861, 8873, 8885, 8897,
|
|
8909, 8921, 8932, 8944, 8956, 8968, 8980, 8992, 9004, 9016, 9027, 9042, 9057, 9070,
|
|
9083, 9098, 9113, 9126, 9139, 9154, 9169, 9184, 9199, 9212, 9225, 9238, 9251, 9266,
|
|
9281, 9294, 9307, 9321, 9335, 9348, 9361, 9374, 9386, 9399, 9412, 9424, 9435, 9446,
|
|
9457, 9468, 9479, 9489, 9505, 9521, 9537, 9553, 9567, 9581, 9595, 9609, 9622, 9635,
|
|
9648, 9661, 9674, 9687, 9700, 9712, 9725, 9738, 9751, 9764, 9777, 9790, 9803, 9815,
|
|
9829, 9843, 9856, 9870, 9884, 9897, 9911, 9925, 9938, 9951, 9964, 9977, 9990, 10003,
|
|
10016, 10029, 10041, 10054, 10067, 10080, 10093, 10106, 10119, 10132, 10144, 10156, 10168, 10180,
|
|
10192, 10204, 10216, 10228, 10239, 10252, 10265, 10278, 10291, 10304, 10317, 10330, 10342, 10354,
|
|
10366, 10378, 10390, 10402, 10414, 10426, 10437, 10450, 10463, 10475, 10488, 10501, 10513, 10526,
|
|
10539, 10551, 10563, 10575, 10587, 10599, 10611, 10623, 10635, 10646, 10658, 10670, 10682, 10694,
|
|
10706, 10718, 10730, 10741, 10754, 10767, 10779, 10787, 10796, 10805, 10813, 10822, 10831, 10840,
|
|
10849, 10859, 10868, 10878, 10887, 10897, 10907, 10916, 10925, 10935, 10945, 10954, 10963, 10976,
|
|
10989, 11002, 11015, 11028, 11040, 11053, 11066, 11079, 11092, 11105, 11117, 11129, 11141, 11153,
|
|
11165, 11177, 11189, 11201, 11212, 11224, 11236, 11248, 11260, 11272, 11284, 11296, 11307, 11319,
|
|
11331, 11342, 11354, 11366, 11378, 11390, 11402, 11414, 11426, 11437, 11449, 11461, 11473, 11485,
|
|
11497, 11509, 11521, 11532, 11541, 11551, 11561, 11570, 11580, 11590, 11602, 11614, 11626, 11638,
|
|
11650, 11662, 11674, 11685, 11697, 11709, 11721, 11733, 11745, 11757, 11769, 11780, 11793, 11806,
|
|
11818, 11828, 11838, 11847, 11856, 11865, 11873, 11885, 11897, 11909, 11921, 11933, 11945, 11956,
|
|
11967, 11978, 11989, 12000, 12011, 12022, 12032, 12043, 12054, 12065, 12076, 12087, 12098, 12109,
|
|
12119, 12130, 12141, 12152, 12163, 12174, 12185, 12196, 12206, 12217, 12228, 12238, 12249, 12260,
|
|
12271, 12282, 12293, 12304, 12315, 12325, 12336, 12347, 12358, 12369, 12380, 12391, 12402, 12412,
|
|
12419, 12426, 12433, 12440, 12450, 12460, 12470, 12480, 12490, 12500, 12510, 12519, 12526, 12533,
|
|
12540, 12547, 12558, 12569, 12580, 12591, 12602, 12613, 12624, 12634, 12645, 12656, 12667, 12678,
|
|
12689, 12700, 12711, 12721, 12731, 12741, 12751, 12761, 12771, 12781, 12791, 12800, 12808, 12817,
|
|
12826, 12834, 12843, 12852, 12860, 12867, 12875, 12883, 12890, 12898, 12906, 12914, 12921, 12928,
|
|
12938, 12948, 12957, 12968, 12979, 12990, 13001, 13009, 13018, 13026, 13035, 13043, 13050, 13058,
|
|
13066, 13074, 13081, 13091, 13101, 13110, 13121, 13132, 13143, 13154, 13162, 13170, 13178, 13185,
|
|
13194, 13203, 13212, 13221, 13229, 13237, 13247, 13257, 13266, 13277, 13288, 13299, 13310, 13318,
|
|
13326, 13334, 13341, 13350, 13359, 13368, 13377, 13385, 13393, 13399, 13405, 13411, 13417, 13423,
|
|
13429, 13441, 13453, 13464, 13476, 13488, 13500, 13512, 13524, 13536, 13542, 13554, 13566, 13578,
|
|
13590, 13602, 13614, 13621, 13632, 13639, 13649, 13659, 13669, 13679, 13689, 13699, 13709, 13718,
|
|
13724, 13730, 13736, 13742, 13748, 13754, 13760, 13766, 13772, 13778, 13785, 13792, 13800, 13808,
|
|
13816, 13824, 13831, 13838, 13845, 13852, 13860, 13868, 13876, 13884, 13891, 13898, 13906, 13914,
|
|
13921, 13929, 13937, 13944, 13954, 13964, 13974, 13984, 13994, 14003, 14010, 14017, 14024, 14031,
|
|
14038, 14045, 14053, 14061, 14068, 14076, 14084, 14091, 14099, 14107, 14114, 14122, 14130, 14137,
|
|
14141, 14145, 14151, 14160, 14169, 14178, 14186, 14194, 14202, 14211, 14220, 14229, 14239, 14251,
|
|
14261, 14269, 14279, 14287, 14295, 14303, 14311, 14319, 14327, 14335, 14339, 14345, 14351, 14359,
|
|
14367, 14375, 14383, 14389, 14395, 14403, 14409, 14418, 14427, 14436, 14444, 14452, 14460, 14469,
|
|
14478, 14487, 14493, 14499, 14508, 14519, 14528, 14539, 14548, 14559, 14567, 14576, 14587, 14596,
|
|
14607, 14616, 14627, 14635, 14643, 14651, 14659, 14667, 14672, 14691, 14711, 14732, 14738, 14748,
|
|
14756, 14768, 14779, 14789, 14798, 14808, 14816, 14825, 14835, 14843, 14852, 14861, 14870, 14878,
|
|
14890, 14901, 14911, 14920, 14930, 14938, 14947, 14960, 14972, 14983, 14993, 15004, 15013, 15022,
|
|
15035, 15047, 15058, 15068, 15079, 15088, 15095, 15106, 15116, 15125, 15133, 15142, 15155, 15162,
|
|
15173, 15186, 15194, 15202, 15210, 15218, 15224, 15230, 15241, 15250, 15261, 15272, 15281, 15292,
|
|
15302, 15309, 15318, 15330, 15337, 15345, 15359, 15373, 15379, 15388, 15394, 15403, 15409, 15416,
|
|
15423, 15430, 15436, 15444, 15452, 15460, 15468, 15476, 15484, 15492, 15500, 15510, 15519, 15529,
|
|
15537, 15545, 15554, 15562, 15571, 15578, 15585, 15594, 15602, 15611, 15618, 15625, 15632, 15641,
|
|
15649, 15656, 15664, 15672, 15679, 15686, 15695, 15703, 15710, 15716, 15724, 15732, 15740, 15749,
|
|
15757, 15766, 15774, 15782, 15791, 15800, 15808, 15816, 15825, 15833, 15840, 15849, 15858, 15867,
|
|
15875, 15883, 15891, 15898, 15905, 15911, 15917, 15927, 15936, 15944, 15952, 15962, 15971, 15977,
|
|
15986, 15995, 16003, 16012, 16020, 16030, 16040, 16049, 16059, 16069, 16079, 16088, 16097, 16106,
|
|
16115, 16123, 16132, 16141, 16151, 16159, 16168, 16176, 16185, 16193, 16202, 16210, 16219, 16228,
|
|
16237, 16245, 16254, 16263, 16272, 16281, 16289, 16298, 16306, 16315, 16323, 16332, 16341, 16351,
|
|
16361, 16368, 16377, 16385, 16391, 16399, 16411, 16422, 16432, 16441, 16449, 16458, 16466, 16475,
|
|
16484, 16493, 16501, 16513, 16524, 16534, 16543, 16551, 16558, 16569, 16579, 16588, 16596, 16603,
|
|
16612, 16621, 16630, 16640, 16652, 16665, 16676, 16686, 16697, 16705, 16715, 16723, 16731, 16743,
|
|
16759, 16769, 16783, 16793, 16807, 16817, 16831, 16839, 16851, 16859, 16871, 16877, 16886, 16892,
|
|
16901, 16909, 16917, 16925, 16934, 16942, 16950, 16958, 16967, 16975, 16982, 16989, 16996, 17006,
|
|
17015, 17023, 17031, 17041, 17050, 17058, 17066, 17074, 17084, 17093, 17101, 17109, 17119, 17128,
|
|
17136, 17145, 17154, 17164, 17174, 17181, 17190, 17198, 17210, 17226, 17236, 17250, 17260, 17274,
|
|
17284, 17298, 17306, 17318, 17326, 17338, 17344, 17350, 17358, 17363, 17372, 17379, 17386, 17395,
|
|
17403, 17412, 17419, 17427, 17435, 17444, 17462, 17478, 17483, 17490, 17497, 17504, 17507, 17512,
|
|
17518, 17522, 17528, 17537, 17543, 17552, 17558, 17565, 17573, 17577, 17585, 17600, 17606, 17611,
|
|
17617, 17623, 17628, 17634, 17642, 17649, 17655, 17664, 17672, 17679, 17684, 17689, 17709, 17714,
|
|
17719, 17725, 17732, 17738, 17745, 17752, 17759, 17766, 17772, 17780, 17792, 17800, 17810, 17822,
|
|
17829, 17836, 17843, 17850, 17858, 17866, 17881, 17888, 17900, 17913, 17920, 17926, 17939, 17944,
|
|
17949, 17954, 17959, 17967, 17972, 17981, 17987, 17992, 17999, 18006, 18011, 18016, 18025, 18030,
|
|
18040, 18050, 18055, 18060, 18065, 18071, 18078, 18084, 18091, 18097, 18105, 18112, 18119, 18126,
|
|
18134, 18143, 18148, 18154, 18160, 18167, 18175, 18181, 18186, 18192, 18198, 18203, 18208, 0
|
|
};
|
|
|
|
const char *Strs =
|
|
"PHI\000INLINEASM\000DBG_LABEL\000EH_LABEL\000GC_LABEL\000KILL\000EXTRAC"
|
|
"T_SUBREG\000INSERT_SUBREG\000IMPLICIT_DEF\000SUBREG_TO_REG\000COPY_TO_R"
|
|
"EGCLASS\000DBG_VALUE\000ADCSSri\000ADCSSrr\000ADCSSrs\000ADCri\000ADCrr"
|
|
"\000ADCrs\000ADDSri\000ADDSrr\000ADDSrs\000ADDri\000ADDrr\000ADDrs\000A"
|
|
"DJCALLSTACKDOWN\000ADJCALLSTACKUP\000ANDri\000ANDrr\000ANDrs\000ATOMIC_"
|
|
"CMP_SWAP_I16\000ATOMIC_CMP_SWAP_I32\000ATOMIC_CMP_SWAP_I8\000ATOMIC_LOA"
|
|
"D_ADD_I16\000ATOMIC_LOAD_ADD_I32\000ATOMIC_LOAD_ADD_I8\000ATOMIC_LOAD_A"
|
|
"ND_I16\000ATOMIC_LOAD_AND_I32\000ATOMIC_LOAD_AND_I8\000ATOMIC_LOAD_NAND"
|
|
"_I16\000ATOMIC_LOAD_NAND_I32\000ATOMIC_LOAD_NAND_I8\000ATOMIC_LOAD_OR_I"
|
|
"16\000ATOMIC_LOAD_OR_I32\000ATOMIC_LOAD_OR_I8\000ATOMIC_LOAD_SUB_I16\000"
|
|
"ATOMIC_LOAD_SUB_I32\000ATOMIC_LOAD_SUB_I8\000ATOMIC_LOAD_XOR_I16\000ATO"
|
|
"MIC_LOAD_XOR_I32\000ATOMIC_LOAD_XOR_I8\000ATOMIC_SWAP_I16\000ATOMIC_SWA"
|
|
"P_I32\000ATOMIC_SWAP_I8\000B\000BFC\000BFI\000BICri\000BICrr\000BICrs\000"
|
|
"BKPT\000BL\000BLX\000BLXr9\000BL_pred\000BLr9\000BLr9_pred\000BRIND\000"
|
|
"BR_JTadd\000BR_JTm\000BR_JTr\000BX\000BXJ\000BX_RET\000BXr9\000Bcc\000C"
|
|
"DP\000CDP2\000CLREX\000CLZ\000CMNzri\000CMNzrr\000CMNzrs\000CMPri\000CM"
|
|
"Prr\000CMPrs\000CMPzri\000CMPzrr\000CMPzrs\000CONSTPOOL_ENTRY\000CPS\000"
|
|
"DBG\000DMBish\000DMBishst\000DMBnsh\000DMBnshst\000DMBosh\000DMBoshst\000"
|
|
"DMBst\000DSBish\000DSBishst\000DSBnsh\000DSBnshst\000DSBosh\000DSBoshst"
|
|
"\000DSBst\000EORri\000EORrr\000EORrs\000FCONSTD\000FCONSTS\000FMSTAT\000"
|
|
"ISBsy\000Int_MemBarrierV6\000Int_MemBarrierV7\000Int_SyncBarrierV6\000I"
|
|
"nt_SyncBarrierV7\000Int_eh_sjlj_setjmp\000LDC2L_OFFSET\000LDC2L_OPTION\000"
|
|
"LDC2L_POST\000LDC2L_PRE\000LDC2_OFFSET\000LDC2_OPTION\000LDC2_POST\000L"
|
|
"DC2_PRE\000LDCL_OFFSET\000LDCL_OPTION\000LDCL_POST\000LDCL_PRE\000LDC_O"
|
|
"FFSET\000LDC_OPTION\000LDC_POST\000LDC_PRE\000LDM\000LDM_RET\000LDR\000"
|
|
"LDRB\000LDRBT\000LDRB_POST\000LDRB_PRE\000LDRD\000LDRD_POST\000LDRD_PRE"
|
|
"\000LDREX\000LDREXB\000LDREXD\000LDREXH\000LDRH\000LDRHT\000LDRH_POST\000"
|
|
"LDRH_PRE\000LDRSB\000LDRSBT\000LDRSB_POST\000LDRSB_PRE\000LDRSH\000LDRS"
|
|
"HT\000LDRSH_POST\000LDRSH_PRE\000LDRT\000LDR_POST\000LDR_PRE\000LDRcp\000"
|
|
"LEApcrel\000LEApcrelJT\000MCR\000MCR2\000MCRR\000MCRR2\000MLA\000MLS\000"
|
|
"MOVCCi\000MOVCCr\000MOVCCs\000MOVTi16\000MOVi\000MOVi16\000MOVi2pieces\000"
|
|
"MOVi32imm\000MOVr\000MOVrx\000MOVs\000MOVsra_flag\000MOVsrl_flag\000MRC"
|
|
"\000MRC2\000MRRC\000MRRC2\000MRS\000MRSsys\000MSR\000MSRi\000MSRsys\000"
|
|
"MSRsysi\000MUL\000MVNi\000MVNr\000MVNs\000NOP\000ORRri\000ORRrr\000ORRr"
|
|
"s\000PICADD\000PICLDR\000PICLDRB\000PICLDRH\000PICLDRSB\000PICLDRSH\000"
|
|
"PICSTR\000PICSTRB\000PICSTRH\000PKHBT\000PKHTB\000PLDWi\000PLDWr\000PLD"
|
|
"i\000PLDr\000PLIi\000PLIr\000QADD\000QADD16\000QADD8\000QASX\000QDADD\000"
|
|
"QDSUB\000QSAX\000QSUB\000QSUB16\000QSUB8\000RBIT\000REV\000REV16\000REV"
|
|
"SH\000RFE\000RFEW\000RSBSri\000RSBSrs\000RSBri\000RSBrs\000RSCSri\000RS"
|
|
"CSrs\000RSCri\000RSCrs\000SADD16\000SADD8\000SASX\000SBCSSri\000SBCSSrr"
|
|
"\000SBCSSrs\000SBCri\000SBCrr\000SBCrs\000SBFX\000SEL\000SETENDBE\000SE"
|
|
"TENDLE\000SEV\000SHADD16\000SHADD8\000SHASX\000SHSAX\000SHSUB16\000SHSU"
|
|
"B8\000SMC\000SMLABB\000SMLABT\000SMLAD\000SMLADX\000SMLAL\000SMLALBB\000"
|
|
"SMLALBT\000SMLALD\000SMLALDX\000SMLALTB\000SMLALTT\000SMLATB\000SMLATT\000"
|
|
"SMLAWB\000SMLAWT\000SMLSD\000SMLSDX\000SMLSLD\000SMLSLDX\000SMMLA\000SM"
|
|
"MLAR\000SMMLS\000SMMLSR\000SMMUL\000SMMULR\000SMUAD\000SMUADX\000SMULBB"
|
|
"\000SMULBT\000SMULL\000SMULTB\000SMULTT\000SMULWB\000SMULWT\000SMUSD\000"
|
|
"SMUSDX\000SRS\000SRSW\000SSAT16\000SSATasr\000SSATlsl\000SSAX\000SSUB16"
|
|
"\000SSUB8\000STC2L_OFFSET\000STC2L_OPTION\000STC2L_POST\000STC2L_PRE\000"
|
|
"STC2_OFFSET\000STC2_OPTION\000STC2_POST\000STC2_PRE\000STCL_OFFSET\000S"
|
|
"TCL_OPTION\000STCL_POST\000STCL_PRE\000STC_OFFSET\000STC_OPTION\000STC_"
|
|
"POST\000STC_PRE\000STM\000STR\000STRB\000STRBT\000STRB_POST\000STRB_PRE"
|
|
"\000STRD\000STRD_POST\000STRD_PRE\000STREX\000STREXB\000STREXD\000STREX"
|
|
"H\000STRH\000STRHT\000STRH_POST\000STRH_PRE\000STRT\000STR_POST\000STR_"
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"SXTAHrr\000SXTAHrr_rot\000SXTB16r\000SXTB16r_rot\000SXTBr\000SXTBr_rot\000"
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"SXTHr\000SXTHr_rot\000TEQri\000TEQrr\000TEQrs\000TPsoft\000TRAP\000TSTr"
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"ADA8\000USAT16\000USATasr\000USATlsl\000USAX\000USUB16\000USUB8\000UXTA"
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"B16rr\000UXTAB16rr_rot\000UXTABrr\000UXTABrr_rot\000UXTAHrr\000UXTAHrr_"
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"rot\000UXTB16r\000UXTB16r_rot\000UXTBr\000UXTBr_rot\000UXTHr\000UXTHr_r"
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"ot\000VABALsv2i64\000VABALsv4i32\000VABALsv8i16\000VABALuv2i64\000VABAL"
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"uv4i32\000VABALuv8i16\000VABAsv16i8\000VABAsv2i32\000VABAsv4i16\000VABA"
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"sv4i32\000VABAsv8i16\000VABAsv8i8\000VABAuv16i8\000VABAuv2i32\000VABAuv"
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"4i16\000VABAuv4i32\000VABAuv8i16\000VABAuv8i8\000VABDLsv2i64\000VABDLsv"
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"4i32\000VABDLsv8i16\000VABDLuv2i64\000VABDLuv4i32\000VABDLuv8i16\000VAB"
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"Dfd\000VABDfq\000VABDsv16i8\000VABDsv2i32\000VABDsv4i16\000VABDsv4i32\000"
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"VABDsv8i16\000VABDsv8i8\000VABDuv16i8\000VABDuv2i32\000VABDuv4i16\000VA"
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"BDuv4i32\000VABDuv8i16\000VABDuv8i8\000VABSD\000VABSS\000VABSfd\000VABS"
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"fd_sfp\000VABSfq\000VABSv16i8\000VABSv2i32\000VABSv4i16\000VABSv4i32\000"
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"VABSv8i16\000VABSv8i8\000VACGEd\000VACGEq\000VACGTd\000VACGTq\000VADDD\000"
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"VADDHNv2i32\000VADDHNv4i16\000VADDHNv8i8\000VADDLsv2i64\000VADDLsv4i32\000"
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"VADDLsv8i16\000VADDLuv2i64\000VADDLuv4i32\000VADDLuv8i16\000VADDS\000VA"
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"DDWsv2i64\000VADDWsv4i32\000VADDWsv8i16\000VADDWuv2i64\000VADDWuv4i32\000"
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"VADDWuv8i16\000VADDfd\000VADDfd_sfp\000VADDfq\000VADDv16i8\000VADDv1i64"
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"\000VADDv2i32\000VADDv2i64\000VADDv4i16\000VADDv4i32\000VADDv8i16\000VA"
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"DDv8i8\000VANDd\000VANDq\000VBICd\000VBICq\000VBIFd\000VBIFq\000VBITd\000"
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"VBITq\000VBSLd\000VBSLq\000VCEQfd\000VCEQfq\000VCEQv16i8\000VCEQv2i32\000"
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"VCEQv4i16\000VCEQv4i32\000VCEQv8i16\000VCEQv8i8\000VCEQzv16i8\000VCEQzv"
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"2f32\000VCEQzv2i32\000VCEQzv4f32\000VCEQzv4i16\000VCEQzv4i32\000VCEQzv8"
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"i16\000VCEQzv8i8\000VCGEfd\000VCGEfq\000VCGEsv16i8\000VCGEsv2i32\000VCG"
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"Esv4i16\000VCGEsv4i32\000VCGEsv8i16\000VCGEsv8i8\000VCGEuv16i8\000VCGEu"
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"v2i32\000VCGEuv4i16\000VCGEuv4i32\000VCGEuv8i16\000VCGEuv8i8\000VCGEzv1"
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"6i8\000VCGEzv2f32\000VCGEzv2i32\000VCGEzv4f32\000VCGEzv4i16\000VCGEzv4i"
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"32\000VCGEzv8i16\000VCGEzv8i8\000VCGTfd\000VCGTfq\000VCGTsv16i8\000VCGT"
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"sv2i32\000VCGTsv4i16\000VCGTsv4i32\000VCGTsv8i16\000VCGTsv8i8\000VCGTuv"
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"16i8\000VCGTuv2i32\000VCGTuv4i16\000VCGTuv4i32\000VCGTuv8i16\000VCGTuv8"
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"i8\000VCGTzv16i8\000VCGTzv2f32\000VCGTzv2i32\000VCGTzv4f32\000VCGTzv4i1"
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"6\000VCGTzv4i32\000VCGTzv8i16\000VCGTzv8i8\000VCLEzv16i8\000VCLEzv2f32\000"
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"VCLEzv2i32\000VCLEzv4f32\000VCLEzv4i16\000VCLEzv4i32\000VCLEzv8i16\000V"
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"CLEzv8i8\000VCLSv16i8\000VCLSv2i32\000VCLSv4i16\000VCLSv4i32\000VCLSv8i"
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"16\000VCLSv8i8\000VCLTzv16i8\000VCLTzv2f32\000VCLTzv2i32\000VCLTzv4f32\000"
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"VCLTzv4i16\000VCLTzv4i32\000VCLTzv8i16\000VCLTzv8i8\000VCLZv16i8\000VCL"
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"Zv2i32\000VCLZv4i16\000VCLZv4i32\000VCLZv8i16\000VCLZv8i8\000VCMPD\000V"
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"CMPED\000VCMPES\000VCMPEZD\000VCMPEZS\000VCMPS\000VCMPZD\000VCMPZS\000V"
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"CNTd\000VCNTq\000VCVTBHS\000VCVTBSH\000VCVTDS\000VCVTSD\000VCVTTHS\000V"
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"CVTTSH\000VCVTf2sd\000VCVTf2sd_sfp\000VCVTf2sq\000VCVTf2ud\000VCVTf2ud_"
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"sfp\000VCVTf2uq\000VCVTf2xsd\000VCVTf2xsq\000VCVTf2xud\000VCVTf2xuq\000"
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"VCVTs2fd\000VCVTs2fd_sfp\000VCVTs2fq\000VCVTu2fd\000VCVTu2fd_sfp\000VCV"
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"Tu2fq\000VCVTxs2fd\000VCVTxs2fq\000VCVTxu2fd\000VCVTxu2fq\000VDIVD\000V"
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"DIVS\000VDUP16d\000VDUP16q\000VDUP32d\000VDUP32q\000VDUP8d\000VDUP8q\000"
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"VDUPLN16d\000VDUPLN16q\000VDUPLN32d\000VDUPLN32q\000VDUPLN8d\000VDUPLN8"
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"q\000VDUPLNfd\000VDUPLNfq\000VDUPfd\000VDUPfdf\000VDUPfq\000VDUPfqf\000"
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"VEORd\000VEORq\000VEXTd16\000VEXTd32\000VEXTd8\000VEXTdf\000VEXTq16\000"
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"VEXTq32\000VEXTq8\000VEXTqf\000VGETLNi32\000VGETLNs16\000VGETLNs8\000VG"
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"ETLNu16\000VGETLNu8\000VHADDsv16i8\000VHADDsv2i32\000VHADDsv4i16\000VHA"
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"DDsv4i32\000VHADDsv8i16\000VHADDsv8i8\000VHADDuv16i8\000VHADDuv2i32\000"
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"VHADDuv4i16\000VHADDuv4i32\000VHADDuv8i16\000VHADDuv8i8\000VHSUBsv16i8\000"
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"VHSUBuv16i8\000VHSUBuv2i32\000VHSUBuv4i16\000VHSUBuv4i32\000VHSUBuv8i16"
|
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"\000VHSUBuv8i8\000VLD1d16\000VLD1d16Q\000VLD1d16T\000VLD1d32\000VLD1d32"
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"Q\000VLD1d32T\000VLD1d64\000VLD1d8\000VLD1d8Q\000VLD1d8T\000VLD1df\000V"
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"\000VLD2d16\000VLD2d16D\000VLD2d32\000VLD2d32D\000VLD2d64\000VLD2d8\000"
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|
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|
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"VMAXuv4i16\000VMAXuv4i32\000VMAXuv8i16\000VMAXuv8i8\000VMINfd\000VMINfd"
|
|
"_sfp\000VMINfq\000VMINsv16i8\000VMINsv2i32\000VMINsv4i16\000VMINsv4i32\000"
|
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"VMINsv8i16\000VMINsv8i8\000VMINuv16i8\000VMINuv2i32\000VMINuv4i16\000VM"
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"INuv4i32\000VMINuv8i16\000VMINuv8i8\000VMLAD\000VMLALslsv2i32\000VMLALs"
|
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"lsv4i16\000VMLALsluv2i32\000VMLALsluv4i16\000VMLALsv2i64\000VMLALsv4i32"
|
|
"\000VMLALsv8i16\000VMLALuv2i64\000VMLALuv4i32\000VMLALuv8i16\000VMLAS\000"
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"LAv4i32\000VMLAv8i16\000VMLAv8i8\000VMLSD\000VMLSLslsv2i32\000VMLSLslsv"
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"4i16\000VMLSLsluv2i32\000VMLSLsluv4i16\000VMLSLsv2i64\000VMLSLsv4i32\000"
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"VMLSLsv8i16\000VMLSLuv2i64\000VMLSLuv4i32\000VMLSLuv8i16\000VMLSS\000VM"
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"VMLSslv4i32\000VMLSslv8i16\000VMLSv16i8\000VMLSv2i32\000VMLSv4i16\000VM"
|
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"LSv4i32\000VMLSv8i16\000VMLSv8i8\000VMOVD\000VMOVDRR\000VMOVDcc\000VMOV"
|
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"Dneon\000VMOVLsv2i64\000VMOVLsv4i32\000VMOVLsv8i16\000VMOVLuv2i64\000VM"
|
|
"OVLuv4i32\000VMOVLuv8i16\000VMOVNv2i32\000VMOVNv4i16\000VMOVNv8i8\000VM"
|
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"OVQ\000VMOVRRD\000VMOVRRS\000VMOVRS\000VMOVS\000VMOVSR\000VMOVSRR\000VM"
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"VMOVv4i32\000VMOVv8i16\000VMOVv8i8\000VMRS\000VMSR\000VMULD\000VMULLp\000"
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"VMULLslsv2i32\000VMULLslsv4i16\000VMULLsluv2i32\000VMULLsluv4i16\000VMU"
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"LLsv2i64\000VMULLsv4i32\000VMULLsv8i16\000VMULLuv2i64\000VMULLuv4i32\000"
|
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"VMULLuv8i16\000VMULS\000VMULfd\000VMULfd_sfp\000VMULfq\000VMULpd\000VMU"
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"Lpq\000VMULslfd\000VMULslfq\000VMULslv2i32\000VMULslv4i16\000VMULslv4i3"
|
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"2\000VMULslv8i16\000VMULv16i8\000VMULv2i32\000VMULv4i16\000VMULv4i32\000"
|
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"VMULv8i16\000VMULv8i8\000VMVNd\000VMVNq\000VNEGD\000VNEGDcc\000VNEGS\000"
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"VNEGs32d\000VNEGs32q\000VNEGs8d\000VNEGs8q\000VNMLAD\000VNMLAS\000VNMLS"
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"D\000VNMLSS\000VNMULD\000VNMULS\000VORNd\000VORNq\000VORRd\000VORRq\000"
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|
"VPADALsv16i8\000VPADALsv2i32\000VPADALsv4i16\000VPADALsv4i32\000VPADALs"
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"v8i16\000VPADALsv8i8\000VPADALuv16i8\000VPADALuv2i32\000VPADALuv4i16\000"
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"VPADALuv4i32\000VPADALuv8i16\000VPADALuv8i8\000VPADDLsv16i8\000VPADDLsv"
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"2i32\000VPADDLsv4i16\000VPADDLsv4i32\000VPADDLsv8i16\000VPADDLsv8i8\000"
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"VPADDLuv16i8\000VPADDLuv2i32\000VPADDLuv4i16\000VPADDLuv4i32\000VPADDLu"
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"v8i16\000VPADDLuv8i8\000VPADDf\000VPADDi16\000VPADDi32\000VPADDi8\000VP"
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"MAXf\000VPMAXs16\000VPMAXs32\000VPMAXs8\000VPMAXu16\000VPMAXu32\000VPMA"
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"2\000VPMINu8\000VQABSv16i8\000VQABSv2i32\000VQABSv4i16\000VQABSv4i32\000"
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|
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"\000VQADDuv4i32\000VQADDuv8i16\000VQADDuv8i8\000VQDMLALslv2i32\000VQDML"
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"ALslv4i16\000VQDMLALv2i64\000VQDMLALv4i32\000VQDMLSLslv2i32\000VQDMLSLs"
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"lv4i16\000VQDMLSLv2i64\000VQDMLSLv4i32\000VQDMULHslv2i32\000VQDMULHslv4"
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"i16\000VQDMULHslv4i32\000VQDMULHslv8i16\000VQDMULHv2i32\000VQDMULHv4i16"
|
|
"\000VQDMULHv4i32\000VQDMULHv8i16\000VQDMULLslv2i32\000VQDMULLslv4i16\000"
|
|
"VQDMULLv2i64\000VQDMULLv4i32\000VQMOVNsuv2i32\000VQMOVNsuv4i16\000VQMOV"
|
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"Nsuv8i8\000VQMOVNsv2i32\000VQMOVNsv4i16\000VQMOVNsv8i8\000VQMOVNuv2i32\000"
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"VQMOVNuv4i16\000VQMOVNuv8i8\000VQNEGv16i8\000VQNEGv2i32\000VQNEGv4i16\000"
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"VQNEGv4i32\000VQNEGv8i16\000VQNEGv8i8\000VQRDMULHslv2i32\000VQRDMULHslv"
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"4i16\000VQRDMULHslv4i32\000VQRDMULHslv8i16\000VQRDMULHv2i32\000VQRDMULH"
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"v4i16\000VQRDMULHv4i32\000VQRDMULHv8i16\000VQRSHLsv16i8\000VQRSHLsv1i64"
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"\000VQRSHLsv2i32\000VQRSHLsv2i64\000VQRSHLsv4i16\000VQRSHLsv4i32\000VQR"
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"v2i32\000VQRSHRNuv4i16\000VQRSHRNuv8i8\000VQRSHRUNv2i32\000VQRSHRUNv4i1"
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"6\000VQRSHRUNv8i8\000VQSHLsiv16i8\000VQSHLsiv1i64\000VQSHLsiv2i32\000VQ"
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|
|
"i8\000VQSHLsuv16i8\000VQSHLsuv1i64\000VQSHLsuv2i32\000VQSHLsuv2i64\000V"
|
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"QSHLsuv4i16\000VQSHLsuv4i32\000VQSHLsuv8i16\000VQSHLsuv8i8\000VQSHLsv16"
|
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"i8\000VQSHLsv1i64\000VQSHLsv2i32\000VQSHLsv2i64\000VQSHLsv4i16\000VQSHL"
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"sv4i32\000VQSHLsv8i16\000VQSHLsv8i8\000VQSHLuiv16i8\000VQSHLuiv1i64\000"
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"VQSHLuiv2i32\000VQSHLuiv2i64\000VQSHLuiv4i16\000VQSHLuiv4i32\000VQSHLui"
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|
"v8i16\000VQSHLuiv8i8\000VQSHLuv16i8\000VQSHLuv1i64\000VQSHLuv2i32\000VQ"
|
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|
|
"VQSHRNsv2i32\000VQSHRNsv4i16\000VQSHRNsv8i8\000VQSHRNuv2i32\000VQSHRNuv"
|
|
"4i16\000VQSHRNuv8i8\000VQSHRUNv2i32\000VQSHRUNv4i16\000VQSHRUNv8i8\000V"
|
|
"QSUBsv16i8\000VQSUBsv1i64\000VQSUBsv2i32\000VQSUBsv2i64\000VQSUBsv4i16\000"
|
|
"VQSUBsv4i32\000VQSUBsv8i16\000VQSUBsv8i8\000VQSUBuv16i8\000VQSUBuv1i64\000"
|
|
"VQSUBuv2i32\000VQSUBuv2i64\000VQSUBuv4i16\000VQSUBuv4i32\000VQSUBuv8i16"
|
|
"\000VQSUBuv8i8\000VRADDHNv2i32\000VRADDHNv4i16\000VRADDHNv8i8\000VRECPE"
|
|
"d\000VRECPEfd\000VRECPEfq\000VRECPEq\000VRECPSfd\000VRECPSfq\000VREV16d"
|
|
"8\000VREV16q8\000VREV32d16\000VREV32d8\000VREV32q16\000VREV32q8\000VREV"
|
|
"64d16\000VREV64d32\000VREV64d8\000VREV64df\000VREV64q16\000VREV64q32\000"
|
|
"VREV64q8\000VREV64qf\000VRHADDsv16i8\000VRHADDsv2i32\000VRHADDsv4i16\000"
|
|
"VRHADDsv4i32\000VRHADDsv8i16\000VRHADDsv8i8\000VRHADDuv16i8\000VRHADDuv"
|
|
"2i32\000VRHADDuv4i16\000VRHADDuv4i32\000VRHADDuv8i16\000VRHADDuv8i8\000"
|
|
"VRSHLsv16i8\000VRSHLsv1i64\000VRSHLsv2i32\000VRSHLsv2i64\000VRSHLsv4i16"
|
|
"\000VRSHLsv4i32\000VRSHLsv8i16\000VRSHLsv8i8\000VRSHLuv16i8\000VRSHLuv1"
|
|
"i64\000VRSHLuv2i32\000VRSHLuv2i64\000VRSHLuv4i16\000VRSHLuv4i32\000VRSH"
|
|
"Luv8i16\000VRSHLuv8i8\000VRSHRNv2i32\000VRSHRNv4i16\000VRSHRNv8i8\000VR"
|
|
"SHRsv16i8\000VRSHRsv1i64\000VRSHRsv2i32\000VRSHRsv2i64\000VRSHRsv4i16\000"
|
|
"VRSHRsv4i32\000VRSHRsv8i16\000VRSHRsv8i8\000VRSHRuv16i8\000VRSHRuv1i64\000"
|
|
"VRSHRuv2i32\000VRSHRuv2i64\000VRSHRuv4i16\000VRSHRuv4i32\000VRSHRuv8i16"
|
|
"\000VRSHRuv8i8\000VRSQRTEd\000VRSQRTEfd\000VRSQRTEfq\000VRSQRTEq\000VRS"
|
|
"QRTSfd\000VRSQRTSfq\000VRSRAsv16i8\000VRSRAsv1i64\000VRSRAsv2i32\000VRS"
|
|
"RAsv2i64\000VRSRAsv4i16\000VRSRAsv4i32\000VRSRAsv8i16\000VRSRAsv8i8\000"
|
|
"VRSRAuv16i8\000VRSRAuv1i64\000VRSRAuv2i32\000VRSRAuv2i64\000VRSRAuv4i16"
|
|
"\000VRSRAuv4i32\000VRSRAuv8i16\000VRSRAuv8i8\000VRSUBHNv2i32\000VRSUBHN"
|
|
"v4i16\000VRSUBHNv8i8\000VSETLNi16\000VSETLNi32\000VSETLNi8\000VSHLLi16\000"
|
|
"VSHLLi32\000VSHLLi8\000VSHLLsv2i64\000VSHLLsv4i32\000VSHLLsv8i16\000VSH"
|
|
"LLuv2i64\000VSHLLuv4i32\000VSHLLuv8i16\000VSHLiv16i8\000VSHLiv1i64\000V"
|
|
"SHLiv2i32\000VSHLiv2i64\000VSHLiv4i16\000VSHLiv4i32\000VSHLiv8i16\000VS"
|
|
"HLiv8i8\000VSHLsv16i8\000VSHLsv1i64\000VSHLsv2i32\000VSHLsv2i64\000VSHL"
|
|
"sv4i16\000VSHLsv4i32\000VSHLsv8i16\000VSHLsv8i8\000VSHLuv16i8\000VSHLuv"
|
|
"1i64\000VSHLuv2i32\000VSHLuv2i64\000VSHLuv4i16\000VSHLuv4i32\000VSHLuv8"
|
|
"i16\000VSHLuv8i8\000VSHRNv2i32\000VSHRNv4i16\000VSHRNv8i8\000VSHRsv16i8"
|
|
"\000VSHRsv1i64\000VSHRsv2i32\000VSHRsv2i64\000VSHRsv4i16\000VSHRsv4i32\000"
|
|
"VSHRsv8i16\000VSHRsv8i8\000VSHRuv16i8\000VSHRuv1i64\000VSHRuv2i32\000VS"
|
|
"HRuv2i64\000VSHRuv4i16\000VSHRuv4i32\000VSHRuv8i16\000VSHRuv8i8\000VSHT"
|
|
"OD\000VSHTOS\000VSITOD\000VSITOS\000VSLIv16i8\000VSLIv1i64\000VSLIv2i32"
|
|
"\000VSLIv2i64\000VSLIv4i16\000VSLIv4i32\000VSLIv8i16\000VSLIv8i8\000VSL"
|
|
"TOD\000VSLTOS\000VSQRTD\000VSQRTS\000VSRAsv16i8\000VSRAsv1i64\000VSRAsv"
|
|
"2i32\000VSRAsv2i64\000VSRAsv4i16\000VSRAsv4i32\000VSRAsv8i16\000VSRAsv8"
|
|
"i8\000VSRAuv16i8\000VSRAuv1i64\000VSRAuv2i32\000VSRAuv2i64\000VSRAuv4i1"
|
|
"6\000VSRAuv4i32\000VSRAuv8i16\000VSRAuv8i8\000VSRIv16i8\000VSRIv1i64\000"
|
|
"VSRIv2i32\000VSRIv2i64\000VSRIv4i16\000VSRIv4i32\000VSRIv8i16\000VSRIv8"
|
|
"i8\000VST1d16\000VST1d16Q\000VST1d16T\000VST1d32\000VST1d32Q\000VST1d32"
|
|
"T\000VST1d64\000VST1d8\000VST1d8Q\000VST1d8T\000VST1df\000VST1q16\000VS"
|
|
"T1q32\000VST1q64\000VST1q8\000VST1qf\000VST2LNd16\000VST2LNd32\000VST2L"
|
|
"Nd8\000VST2LNq16a\000VST2LNq16b\000VST2LNq32a\000VST2LNq32b\000VST2d16\000"
|
|
"VST2d16D\000VST2d32\000VST2d32D\000VST2d64\000VST2d8\000VST2d8D\000VST2"
|
|
"q16\000VST2q32\000VST2q8\000VST3LNd16\000VST3LNd32\000VST3LNd8\000VST3L"
|
|
"Nq16a\000VST3LNq16b\000VST3LNq32a\000VST3LNq32b\000VST3d16\000VST3d32\000"
|
|
"VST3d64\000VST3d8\000VST3q16a\000VST3q16b\000VST3q32a\000VST3q32b\000VS"
|
|
"T3q8a\000VST3q8b\000VST4LNd16\000VST4LNd32\000VST4LNd8\000VST4LNq16a\000"
|
|
"VST4LNq16b\000VST4LNq32a\000VST4LNq32b\000VST4d16\000VST4d32\000VST4d64"
|
|
"\000VST4d8\000VST4q16a\000VST4q16b\000VST4q32a\000VST4q32b\000VST4q8a\000"
|
|
"VST4q8b\000VSTMD\000VSTMS\000VSTRD\000VSTRQ\000VSTRS\000VSUBD\000VSUBHN"
|
|
"v2i32\000VSUBHNv4i16\000VSUBHNv8i8\000VSUBLsv2i64\000VSUBLsv4i32\000VSU"
|
|
"BLsv8i16\000VSUBLuv2i64\000VSUBLuv4i32\000VSUBLuv8i16\000VSUBS\000VSUBW"
|
|
"sv2i64\000VSUBWsv4i32\000VSUBWsv8i16\000VSUBWuv2i64\000VSUBWuv4i32\000V"
|
|
"SUBWuv8i16\000VSUBfd\000VSUBfd_sfp\000VSUBfq\000VSUBv16i8\000VSUBv1i64\000"
|
|
"VSUBv2i32\000VSUBv2i64\000VSUBv4i16\000VSUBv4i32\000VSUBv8i16\000VSUBv8"
|
|
"i8\000VSWPd\000VSWPq\000VTBL1\000VTBL2\000VTBL3\000VTBL4\000VTBX1\000VT"
|
|
"BX2\000VTBX3\000VTBX4\000VTOSHD\000VTOSHS\000VTOSIRD\000VTOSIRS\000VTOS"
|
|
"IZD\000VTOSIZS\000VTOSLD\000VTOSLS\000VTOUHD\000VTOUHS\000VTOUIRD\000VT"
|
|
"OUIRS\000VTOUIZD\000VTOUIZS\000VTOULD\000VTOULS\000VTRNd16\000VTRNd32\000"
|
|
"VTRNd8\000VTRNq16\000VTRNq32\000VTRNq8\000VTSTv16i8\000VTSTv2i32\000VTS"
|
|
"Tv4i16\000VTSTv4i32\000VTSTv8i16\000VTSTv8i8\000VUHTOD\000VUHTOS\000VUI"
|
|
"TOD\000VUITOS\000VULTOD\000VULTOS\000VUZPd16\000VUZPd32\000VUZPd8\000VU"
|
|
"ZPq16\000VUZPq32\000VUZPq8\000VZIPd16\000VZIPd32\000VZIPd8\000VZIPq16\000"
|
|
"VZIPq32\000VZIPq8\000WFE\000WFI\000YIELD\000t2ADCSri\000t2ADCSrr\000t2A"
|
|
"DCSrs\000t2ADCri\000t2ADCrr\000t2ADCrs\000t2ADDSri\000t2ADDSrr\000t2ADD"
|
|
"Srs\000t2ADDrSPi\000t2ADDrSPi12\000t2ADDrSPs\000t2ADDri\000t2ADDri12\000"
|
|
"t2ADDrr\000t2ADDrs\000t2ANDri\000t2ANDrr\000t2ANDrs\000t2ASRri\000t2ASR"
|
|
"rr\000t2B\000t2BFC\000t2BFI\000t2BICri\000t2BICrr\000t2BICrs\000t2BR_JT"
|
|
"\000t2BXJ\000t2Bcc\000t2CLREX\000t2CLZ\000t2CMNzri\000t2CMNzrr\000t2CMN"
|
|
"zrs\000t2CMPri\000t2CMPrr\000t2CMPrs\000t2CMPzri\000t2CMPzrr\000t2CMPzr"
|
|
"s\000t2CPS\000t2DBG\000t2DMBish\000t2DMBishst\000t2DMBnsh\000t2DMBnshst"
|
|
"\000t2DMBosh\000t2DMBoshst\000t2DMBst\000t2DSBish\000t2DSBishst\000t2DS"
|
|
"Bnsh\000t2DSBnshst\000t2DSBosh\000t2DSBoshst\000t2DSBst\000t2EORri\000t"
|
|
"2EORrr\000t2EORrs\000t2ISBsy\000t2IT\000t2Int_MemBarrierV7\000t2Int_Syn"
|
|
"cBarrierV7\000t2Int_eh_sjlj_setjmp\000t2LDM\000t2LDM_RET\000t2LDRBT\000"
|
|
"t2LDRB_POST\000t2LDRB_PRE\000t2LDRBi12\000t2LDRBi8\000t2LDRBpci\000t2LD"
|
|
"RBs\000t2LDRDi8\000t2LDRDpci\000t2LDREX\000t2LDREXB\000t2LDREXD\000t2LD"
|
|
"REXH\000t2LDRHT\000t2LDRH_POST\000t2LDRH_PRE\000t2LDRHi12\000t2LDRHi8\000"
|
|
"t2LDRHpci\000t2LDRHs\000t2LDRSBT\000t2LDRSB_POST\000t2LDRSB_PRE\000t2LD"
|
|
"RSBi12\000t2LDRSBi8\000t2LDRSBpci\000t2LDRSBs\000t2LDRSHT\000t2LDRSH_PO"
|
|
"ST\000t2LDRSH_PRE\000t2LDRSHi12\000t2LDRSHi8\000t2LDRSHpci\000t2LDRSHs\000"
|
|
"t2LDRT\000t2LDR_POST\000t2LDR_PRE\000t2LDRi12\000t2LDRi8\000t2LDRpci\000"
|
|
"t2LDRpci_pic\000t2LDRs\000t2LEApcrel\000t2LEApcrelJT\000t2LSLri\000t2LS"
|
|
"Lrr\000t2LSRri\000t2LSRrr\000t2MLA\000t2MLS\000t2MOVCCasr\000t2MOVCCi\000"
|
|
"t2MOVCClsl\000t2MOVCClsr\000t2MOVCCr\000t2MOVCCror\000t2MOVTi16\000t2MO"
|
|
"Vi\000t2MOVi16\000t2MOVi32imm\000t2MOVr\000t2MOVrx\000t2MOVsra_flag\000"
|
|
"t2MOVsrl_flag\000t2MRS\000t2MRSsys\000t2MSR\000t2MSRsys\000t2MUL\000t2M"
|
|
"VNi\000t2MVNr\000t2MVNs\000t2NOP\000t2ORNri\000t2ORNrr\000t2ORNrs\000t2"
|
|
"ORRri\000t2ORRrr\000t2ORRrs\000t2PKHBT\000t2PKHTB\000t2PLDWi12\000t2PLD"
|
|
"Wi8\000t2PLDWpci\000t2PLDWr\000t2PLDWs\000t2PLDi12\000t2PLDi8\000t2PLDp"
|
|
"ci\000t2PLDr\000t2PLDs\000t2PLIi12\000t2PLIi8\000t2PLIpci\000t2PLIr\000"
|
|
"t2PLIs\000t2QADD\000t2QADD16\000t2QADD8\000t2QASX\000t2QDADD\000t2QDSUB"
|
|
"\000t2QSAX\000t2QSUB\000t2QSUB16\000t2QSUB8\000t2RBIT\000t2REV\000t2REV"
|
|
"16\000t2REVSH\000t2RFEDB\000t2RFEDBW\000t2RFEIA\000t2RFEIAW\000t2RORri\000"
|
|
"t2RORrr\000t2RSBSri\000t2RSBSrs\000t2RSBri\000t2RSBrs\000t2SADD16\000t2"
|
|
"SADD8\000t2SASX\000t2SBCSri\000t2SBCSrr\000t2SBCSrs\000t2SBCri\000t2SBC"
|
|
"rr\000t2SBCrs\000t2SBFX\000t2SDIV\000t2SEL\000t2SEV\000t2SHADD16\000t2S"
|
|
"HADD8\000t2SHASX\000t2SHSAX\000t2SHSUB16\000t2SHSUB8\000t2SMC\000t2SMLA"
|
|
"BB\000t2SMLABT\000t2SMLAD\000t2SMLADX\000t2SMLAL\000t2SMLALBB\000t2SMLA"
|
|
"LBT\000t2SMLALD\000t2SMLALDX\000t2SMLALTB\000t2SMLALTT\000t2SMLATB\000t"
|
|
"2SMLATT\000t2SMLAWB\000t2SMLAWT\000t2SMLSD\000t2SMLSDX\000t2SMLSLD\000t"
|
|
"2SMLSLDX\000t2SMMLA\000t2SMMLAR\000t2SMMLS\000t2SMMLSR\000t2SMMUL\000t2"
|
|
"SMMULR\000t2SMUAD\000t2SMUADX\000t2SMULBB\000t2SMULBT\000t2SMULL\000t2S"
|
|
"MULTB\000t2SMULTT\000t2SMULWB\000t2SMULWT\000t2SMUSD\000t2SMUSDX\000t2S"
|
|
"RSDB\000t2SRSDBW\000t2SRSIA\000t2SRSIAW\000t2SSAT16\000t2SSATasr\000t2S"
|
|
"SATlsl\000t2SSAX\000t2SSUB16\000t2SSUB8\000t2STM\000t2STRBT\000t2STRB_P"
|
|
"OST\000t2STRB_PRE\000t2STRBi12\000t2STRBi8\000t2STRBs\000t2STRDi8\000t2"
|
|
"STREX\000t2STREXB\000t2STREXD\000t2STREXH\000t2STRHT\000t2STRH_POST\000"
|
|
"t2STRH_PRE\000t2STRHi12\000t2STRHi8\000t2STRHs\000t2STRT\000t2STR_POST\000"
|
|
"t2STR_PRE\000t2STRi12\000t2STRi8\000t2STRs\000t2SUBSri\000t2SUBSrr\000t"
|
|
"2SUBSrs\000t2SUBrSPi\000t2SUBrSPi12\000t2SUBrSPi12_\000t2SUBrSPi_\000t2"
|
|
"SUBrSPs\000t2SUBrSPs_\000t2SUBri\000t2SUBri12\000t2SUBrr\000t2SUBrs\000"
|
|
"t2SXTAB16rr\000t2SXTAB16rr_rot\000t2SXTABrr\000t2SXTABrr_rot\000t2SXTAH"
|
|
"rr\000t2SXTAHrr_rot\000t2SXTB16r\000t2SXTB16r_rot\000t2SXTBr\000t2SXTBr"
|
|
"_rot\000t2SXTHr\000t2SXTHr_rot\000t2TBB\000t2TBBgen\000t2TBH\000t2TBHge"
|
|
"n\000t2TEQri\000t2TEQrr\000t2TEQrs\000t2TPsoft\000t2TSTri\000t2TSTrr\000"
|
|
"t2TSTrs\000t2UADD16\000t2UADD8\000t2UASX\000t2UBFX\000t2UDIV\000t2UHADD"
|
|
"16\000t2UHADD8\000t2UHASX\000t2UHSAX\000t2UHSUB16\000t2UHSUB8\000t2UMAA"
|
|
"L\000t2UMLAL\000t2UMULL\000t2UQADD16\000t2UQADD8\000t2UQASX\000t2UQSAX\000"
|
|
"t2UQSUB16\000t2UQSUB8\000t2USAD8\000t2USADA8\000t2USAT16\000t2USATasr\000"
|
|
"t2USATlsl\000t2USAX\000t2USUB16\000t2USUB8\000t2UXTAB16rr\000t2UXTAB16r"
|
|
"r_rot\000t2UXTABrr\000t2UXTABrr_rot\000t2UXTAHrr\000t2UXTAHrr_rot\000t2"
|
|
"UXTB16r\000t2UXTB16r_rot\000t2UXTBr\000t2UXTBr_rot\000t2UXTHr\000t2UXTH"
|
|
"r_rot\000t2WFE\000t2WFI\000t2YIELD\000tADC\000tADDhirr\000tADDi3\000tAD"
|
|
"Di8\000tADDrPCi\000tADDrSP\000tADDrSPi\000tADDrr\000tADDspi\000tADDspr\000"
|
|
"tADDspr_\000tADJCALLSTACKDOWN\000tADJCALLSTACKUP\000tAND\000tANDsp\000t"
|
|
"ASRri\000tASRrr\000tB\000tBIC\000tBKPT\000tBL\000tBLXi\000tBLXi_r9\000t"
|
|
"BLXr\000tBLXr_r9\000tBLr9\000tBRIND\000tBR_JTr\000tBX\000tBX_RET\000tBX"
|
|
"_RET_vararg\000tBXr9\000tBcc\000tBfar\000tCBNZ\000tCBZ\000tCMNz\000tCMP"
|
|
"hir\000tCMPi8\000tCMPr\000tCMPzhir\000tCMPzi8\000tCMPzr\000tCPS\000tEOR"
|
|
"\000tInt_eh_sjlj_setjmp\000tLDM\000tLDR\000tLDRB\000tLDRBi\000tLDRH\000"
|
|
"tLDRHi\000tLDRSB\000tLDRSH\000tLDRcp\000tLDRi\000tLDRpci\000tLDRpci_pic"
|
|
"\000tLDRspi\000tLEApcrel\000tLEApcrelJT\000tLSLri\000tLSLrr\000tLSRri\000"
|
|
"tLSRrr\000tMOVCCi\000tMOVCCr\000tMOVCCr_pseudo\000tMOVSr\000tMOVgpr2gpr"
|
|
"\000tMOVgpr2tgpr\000tMOVi8\000tMOVr\000tMOVtgpr2gpr\000tMUL\000tMVN\000"
|
|
"tNOP\000tORR\000tPICADD\000tPOP\000tPOP_RET\000tPUSH\000tREV\000tREV16\000"
|
|
"tREVSH\000tROR\000tRSB\000tRestore\000tSBC\000tSETENDBE\000tSETENDLE\000"
|
|
"tSEV\000tSTM\000tSTR\000tSTRB\000tSTRBi\000tSTRH\000tSTRHi\000tSTRi\000"
|
|
"tSTRspi\000tSUBi3\000tSUBi8\000tSUBrr\000tSUBspi\000tSUBspi_\000tSVC\000"
|
|
"tSXTB\000tSXTH\000tSpill\000tTPsoft\000tTRAP\000tTST\000tUXTB\000tUXTH\000"
|
|
"tWFE\000tWFI\000tYIELD\000";
|
|
return Strs+InstAsmOffset[Opcode];
|
|
}
|
|
|
|
#endif
|
|
|