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1407 lines
35 KiB
1407 lines
35 KiB
//===- TableGen'erated file -------------------------------------*- C++ -*-===//
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//
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// Assembly Writer Source Fragment
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//
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// Automatically generated file, do not edit!
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//
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//===----------------------------------------------------------------------===//
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/// printInstruction - This method is automatically generated by tablegen
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/// from the instruction set description.
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void PPCAsmPrinter::printInstruction(const MachineInstr *MI) {
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static const unsigned OpInfo[] = {
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0U, // PHI
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0U, // INLINEASM
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0U, // DBG_LABEL
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0U, // EH_LABEL
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0U, // GC_LABEL
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0U, // KILL
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0U, // EXTRACT_SUBREG
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0U, // INSERT_SUBREG
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0U, // IMPLICIT_DEF
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0U, // SUBREG_TO_REG
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0U, // COPY_TO_REGCLASS
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1U, // ADD4
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6U, // ADD8
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11U, // ADDC
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11U, // ADDC8
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17U, // ADDE
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17U, // ADDE8
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4119U, // ADDI
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4119U, // ADDI8
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4125U, // ADDIC
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4125U, // ADDIC8
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4132U, // ADDICo
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8236U, // ADDIS
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8236U, // ADDIS8
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32819U, // ADDME
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32819U, // ADDME8
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32826U, // ADDZE
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32826U, // ADDZE8
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272629825U, // ADJCALLSTACKDOWN
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276824129U, // ADJCALLSTACKUP
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66U, // AND
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66U, // AND8
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71U, // ANDC
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71U, // ANDC8
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12365U, // ANDISo
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12365U, // ANDISo8
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12373U, // ANDIo
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12373U, // ANDIo8
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281018433U, // ATOMIC_CMP_SWAP_I16
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285212737U, // ATOMIC_CMP_SWAP_I32
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289407041U, // ATOMIC_CMP_SWAP_I64
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293601345U, // ATOMIC_CMP_SWAP_I8
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297795649U, // ATOMIC_LOAD_ADD_I16
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301989953U, // ATOMIC_LOAD_ADD_I32
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306184257U, // ATOMIC_LOAD_ADD_I64
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310378561U, // ATOMIC_LOAD_ADD_I8
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314572865U, // ATOMIC_LOAD_AND_I16
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318767169U, // ATOMIC_LOAD_AND_I32
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322961473U, // ATOMIC_LOAD_AND_I64
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327155777U, // ATOMIC_LOAD_AND_I8
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331350081U, // ATOMIC_LOAD_NAND_I16
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335544385U, // ATOMIC_LOAD_NAND_I32
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339738689U, // ATOMIC_LOAD_NAND_I64
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343932993U, // ATOMIC_LOAD_NAND_I8
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348127297U, // ATOMIC_LOAD_OR_I16
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352321601U, // ATOMIC_LOAD_OR_I32
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356515905U, // ATOMIC_LOAD_OR_I64
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360710209U, // ATOMIC_LOAD_OR_I8
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364904513U, // ATOMIC_LOAD_SUB_I16
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369098817U, // ATOMIC_LOAD_SUB_I32
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373293121U, // ATOMIC_LOAD_SUB_I64
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377487425U, // ATOMIC_LOAD_SUB_I8
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381681729U, // ATOMIC_LOAD_XOR_I16
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385876033U, // ATOMIC_LOAD_XOR_I32
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390070337U, // ATOMIC_LOAD_XOR_I64
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394264641U, // ATOMIC_LOAD_XOR_I8
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398458945U, // ATOMIC_SWAP_I16
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402653249U, // ATOMIC_SWAP_I32
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406847553U, // ATOMIC_SWAP_I64
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411041857U, // ATOMIC_SWAP_I8
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|
536871004U, // B
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952369247U, // BCC
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1073741921U, // BCTR
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1073741926U, // BCTRL8_Darwin
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1073741926U, // BCTRL8_ELF
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1073741926U, // BCTRL_Darwin
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1073741926U, // BCTRL_SVR4
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1493172332U, // BL8_Darwin
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1493172332U, // BL8_ELF
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1761607792U, // BLA8_Darwin
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1761607792U, // BLA8_ELF
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1761607792U, // BLA_Darwin
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1761607792U, // BLA_SVR4
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960495711U, // BLR
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1493172332U, // BL_Darwin
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1493172332U, // BL_SVR4
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117U, // CMPD
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4219U, // CMPDI
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130U, // CMPLD
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12425U, // CMPLDI
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145U, // CMPLW
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12440U, // CMPLWI
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160U, // CMPW
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4262U, // CMPWI
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32941U, // CNTLZD
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32949U, // CNTLZW
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189U, // CREQV
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196U, // CROR
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524477U, // CRSET
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1879048394U, // DCBA
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1879048400U, // DCBF
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1879048406U, // DCBI
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1879048412U, // DCBST
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1879048419U, // DCBT
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1879048425U, // DCBTST
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1879048433U, // DCBZ
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1879048439U, // DCBZL
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254U, // DIVD
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260U, // DIVDU
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267U, // DIVW
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273U, // DIVWU
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2147483928U, // DSS
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1073742109U, // DSSALL
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2415919396U, // DST
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2415919396U, // DST64
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2415919401U, // DSTST
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2415919401U, // DSTST64
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2415919408U, // DSTSTT
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2415919408U, // DSTSTT64
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2415919416U, // DSTT
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2415919416U, // DSTT64
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427819073U, // DYNALLOC
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432013377U, // DYNALLOC8
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318U, // EQV
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318U, // EQV8
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33091U, // EXTSB
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33091U, // EXTSB8
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33098U, // EXTSH
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33098U, // EXTSH8
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33105U, // EXTSW
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33105U, // EXTSW_32
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33105U, // EXTSW_32_64
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33112U, // FABSD
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33112U, // FABSS
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350U, // FADD
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356U, // FADDS
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350U, // FADDrtz
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33131U, // FCFID
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370U, // FCMPUD
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370U, // FCMPUS
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33145U, // FCTIDZ
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33153U, // FCTIWZ
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393U, // FDIV
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399U, // FDIVS
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406U, // FMADD
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413U, // FMADDS
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33189U, // FMRD
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33189U, // FMRS
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33189U, // FMRSD
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426U, // FMSUB
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433U, // FMSUBS
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441U, // FMUL
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447U, // FMULS
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33222U, // FNABSD
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33222U, // FNABSS
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33229U, // FNEGD
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33229U, // FNEGS
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467U, // FNMADD
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475U, // FNMADDS
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484U, // FNMSUB
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492U, // FNMSUBS
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33269U, // FRSP
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507U, // FSELD
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507U, // FSELS
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33281U, // FSQRT
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33288U, // FSQRTS
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528U, // FSUB
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534U, // FSUBS
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852509U, // LA
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1049121U, // LBZ
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1049121U, // LBZ8
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1311270U, // LBZU
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1311270U, // LBZU8
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|
1573420U, // LBZX
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1573420U, // LBZX8
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|
1835570U, // LD
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1573430U, // LDARX
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2097725U, // LDU
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1573442U, // LDX
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2359858U, // LDtoc
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1049159U, // LFD
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1311303U, // LFDU
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1573452U, // LFDX
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|
1049170U, // LFS
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|
1311314U, // LFSU
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1573463U, // LFSX
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|
1049181U, // LHA
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|
1049181U, // LHA8
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|
1311330U, // LHAU
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|
885346U, // LHAU8
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|
1573480U, // LHAX
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|
1573480U, // LHAX8
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1573486U, // LHBRX
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1049205U, // LHZ
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|
1049205U, // LHZ8
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|
1311354U, // LHZU
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1311354U, // LHZU8
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|
1573504U, // LHZX
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1573504U, // LHZX8
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2622086U, // LI
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2622086U, // LI8
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2884234U, // LIS
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2884234U, // LIS8
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|
1573519U, // LVEBX
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1573526U, // LVEHX
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|
1573533U, // LVEWX
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|
1573540U, // LVSL
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1573546U, // LVSR
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1573552U, // LVX
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1573557U, // LVXL
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|
1835707U, // LWA
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|
1573568U, // LWARX
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|
1573575U, // LWAX
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|
1573581U, // LWBRX
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|
1049300U, // LWZ
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|
1049300U, // LWZ8
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|
1311449U, // LWZU
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|
1311449U, // LWZU8
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|
1573599U, // LWZX
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|
1573599U, // LWZX8
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|
33509U, // MCRF
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|
150995691U, // MFCR
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150995697U, // MFCTR
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150995697U, // MFCTR8
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150995704U, // MFFS
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150995710U, // MFLR
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150995710U, // MFLR8
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|
3146475U, // MFOCRF
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167772932U, // MFVRSAVE
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150995723U, // MFVSCR
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2684355347U, // MTCRF
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150995738U, // MTCTR
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150995738U, // MTCTR8
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|
2952790817U, // MTFSB0
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2952790825U, // MTFSB1
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|
3393192753U, // MTFSF
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|
150995768U, // MTLR
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150995768U, // MTLR8
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|
150995774U, // MTVRSAVE
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150995786U, // MTVSCR
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|
850U, // MULHD
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|
857U, // MULHDU
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|
865U, // MULHW
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|
872U, // MULHWU
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880U, // MULLD
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|
4983U, // MULLI
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|
894U, // MULLW
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|
3489661036U, // MovePCtoLR
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3489661036U, // MovePCtoLR8
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|
901U, // NAND
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|
901U, // NAND8
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|
33675U, // NEG
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33675U, // NEG8
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1073742736U, // NOP
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916U, // NOR
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|
916U, // NOR8
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|
921U, // OR
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|
921U, // OR4To8
|
|
921U, // OR8
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|
921U, // OR8To4
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|
925U, // ORC
|
|
925U, // ORC8
|
|
13218U, // ORI
|
|
13218U, // ORI8
|
|
13223U, // ORIS
|
|
13223U, // ORIS8
|
|
941U, // RLDCL
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|
17332U, // RLDICL
|
|
17340U, // RLDICR
|
|
3539908U, // RLDIMI
|
|
3572684U, // RLWIMI
|
|
21460U, // RLWINM
|
|
21468U, // RLWINMo
|
|
997U, // RLWNM
|
|
444596289U, // SELECT_CC_F4
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|
444596289U, // SELECT_CC_F8
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|
444596289U, // SELECT_CC_I4
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|
444596289U, // SELECT_CC_I8
|
|
444596289U, // SELECT_CC_VRRC
|
|
1004U, // SLD
|
|
1009U, // SLW
|
|
448790593U, // SPILL_CR
|
|
1014U, // SRAD
|
|
17404U, // SRADI
|
|
1027U, // SRAW
|
|
21513U, // SRAWI
|
|
1040U, // SRD
|
|
1045U, // SRW
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|
1049626U, // STB
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|
1049626U, // STB8
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|
3405775903U, // STBU
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3405775903U, // STBU8
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|
1573925U, // STBX
|
|
1573925U, // STBX8
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|
1836075U, // STD
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|
1573936U, // STDCX
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|
3409970232U, // STDU
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|
1573950U, // STDUX
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|
1573957U, // STDX
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|
1573957U, // STDX_32
|
|
1836075U, // STD_32
|
|
1049675U, // STFD
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|
3405775953U, // STFDU
|
|
1573976U, // STFDX
|
|
1573983U, // STFIWX
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|
1049703U, // STFS
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|
3405775981U, // STFSU
|
|
1574004U, // STFSX
|
|
1049723U, // STH
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|
1049723U, // STH8
|
|
1574016U, // STHBRX
|
|
3405776008U, // STHU
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|
3405776008U, // STHU8
|
|
1574030U, // STHX
|
|
1574030U, // STHX8
|
|
1574036U, // STVEBX
|
|
1574044U, // STVEHX
|
|
1574052U, // STVEWX
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|
1574060U, // STVX
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|
1574066U, // STVXL
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|
1049785U, // STW
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|
1049785U, // STW8
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|
1574078U, // STWBRX
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|
1574086U, // STWCX
|
|
3405776078U, // STWU
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|
3405776078U, // STWU8
|
|
1236U, // STWUX
|
|
1574107U, // STWX
|
|
1574107U, // STWX8
|
|
1249U, // SUBF
|
|
1249U, // SUBF8
|
|
1255U, // SUBFC
|
|
1255U, // SUBFC8
|
|
1262U, // SUBFE
|
|
1262U, // SUBFE8
|
|
5365U, // SUBFIC
|
|
5365U, // SUBFIC8
|
|
34045U, // SUBFME
|
|
34045U, // SUBFME8
|
|
34053U, // SUBFZE
|
|
34053U, // SUBFZE8
|
|
1073743117U, // SYNC
|
|
1493172316U, // TAILB
|
|
1493172316U, // TAILB8
|
|
1761608978U, // TAILBA
|
|
1761608978U, // TAILBA8
|
|
1073741921U, // TAILBCTR
|
|
1073741921U, // TAILBCTR8
|
|
1757447446U, // TCRETURNai
|
|
1757447459U, // TCRETURNai8
|
|
1489012017U, // TCRETURNdi
|
|
1489012030U, // TCRETURNdi8
|
|
146834764U, // TCRETURNri
|
|
146834777U, // TCRETURNri8
|
|
1073743207U, // TRAP
|
|
34156U, // UPDATE_VRSAVE
|
|
1403U, // VADDCUW
|
|
1412U, // VADDFP
|
|
1420U, // VADDSBS
|
|
1429U, // VADDSHS
|
|
1438U, // VADDSWS
|
|
1447U, // VADDUBM
|
|
1456U, // VADDUBS
|
|
1465U, // VADDUHM
|
|
1474U, // VADDUHS
|
|
1483U, // VADDUWM
|
|
1492U, // VADDUWS
|
|
1501U, // VAND
|
|
1507U, // VANDC
|
|
1514U, // VAVGSB
|
|
1522U, // VAVGSH
|
|
1530U, // VAVGSW
|
|
1538U, // VAVGUB
|
|
1546U, // VAVGUH
|
|
1554U, // VAVGUW
|
|
3606042U, // VCFSX
|
|
3606049U, // VCFUX
|
|
1576U, // VCMPBFP
|
|
1585U, // VCMPBFPo
|
|
1595U, // VCMPEQFP
|
|
1605U, // VCMPEQFPo
|
|
1616U, // VCMPEQUB
|
|
1626U, // VCMPEQUBo
|
|
1637U, // VCMPEQUH
|
|
1647U, // VCMPEQUHo
|
|
1658U, // VCMPEQUW
|
|
1668U, // VCMPEQUWo
|
|
1679U, // VCMPGEFP
|
|
1689U, // VCMPGEFPo
|
|
1700U, // VCMPGTFP
|
|
1710U, // VCMPGTFPo
|
|
1721U, // VCMPGTSB
|
|
1731U, // VCMPGTSBo
|
|
1742U, // VCMPGTSH
|
|
1752U, // VCMPGTSHo
|
|
1763U, // VCMPGTSW
|
|
1773U, // VCMPGTSWo
|
|
1784U, // VCMPGTUB
|
|
1794U, // VCMPGTUBo
|
|
1805U, // VCMPGTUH
|
|
1815U, // VCMPGTUHo
|
|
1826U, // VCMPGTUW
|
|
1836U, // VCMPGTUWo
|
|
3606327U, // VCTSXS
|
|
3606335U, // VCTUXS
|
|
34631U, // VEXPTEFP
|
|
34641U, // VLOGEFP
|
|
1882U, // VMADDFP
|
|
1891U, // VMAXFP
|
|
1899U, // VMAXSB
|
|
1907U, // VMAXSH
|
|
1915U, // VMAXSW
|
|
1923U, // VMAXUB
|
|
1931U, // VMAXUH
|
|
1939U, // VMAXUW
|
|
1947U, // VMHADDSHS
|
|
1958U, // VMHRADDSHS
|
|
1970U, // VMINFP
|
|
1978U, // VMINSB
|
|
1986U, // VMINSH
|
|
1994U, // VMINSW
|
|
2002U, // VMINUB
|
|
2010U, // VMINUH
|
|
2018U, // VMINUW
|
|
2026U, // VMLADDUHM
|
|
2037U, // VMRGHB
|
|
2045U, // VMRGHH
|
|
2053U, // VMRGHW
|
|
2061U, // VMRGLB
|
|
2069U, // VMRGLH
|
|
2077U, // VMRGLW
|
|
2085U, // VMSUMMBM
|
|
2095U, // VMSUMSHM
|
|
2105U, // VMSUMSHS
|
|
2115U, // VMSUMUBM
|
|
2125U, // VMSUMUHM
|
|
2135U, // VMSUMUHS
|
|
2145U, // VMULESB
|
|
2154U, // VMULESH
|
|
2163U, // VMULEUB
|
|
2172U, // VMULEUH
|
|
2181U, // VMULOSB
|
|
2190U, // VMULOSH
|
|
2199U, // VMULOUB
|
|
2208U, // VMULOUH
|
|
2217U, // VNMSUBFP
|
|
2227U, // VNOR
|
|
2233U, // VOR
|
|
2238U, // VPERM
|
|
2245U, // VPKPX
|
|
2252U, // VPKSHSS
|
|
2261U, // VPKSHUS
|
|
2270U, // VPKSWSS
|
|
2279U, // VPKSWUS
|
|
2288U, // VPKUHUM
|
|
2297U, // VPKUHUS
|
|
2306U, // VPKUWUM
|
|
2315U, // VPKUWUS
|
|
35092U, // VREFP
|
|
35099U, // VRFIM
|
|
35106U, // VRFIN
|
|
35113U, // VRFIP
|
|
35120U, // VRFIZ
|
|
2359U, // VRLB
|
|
2365U, // VRLH
|
|
2371U, // VRLW
|
|
35145U, // VRSQRTEFP
|
|
2388U, // VSEL
|
|
2394U, // VSL
|
|
2399U, // VSLB
|
|
2405U, // VSLDOI
|
|
2413U, // VSLH
|
|
2419U, // VSLO
|
|
2425U, // VSLW
|
|
3606911U, // VSPLTB
|
|
3606919U, // VSPLTH
|
|
3672463U, // VSPLTISB
|
|
3672473U, // VSPLTISH
|
|
3672483U, // VSPLTISW
|
|
3606957U, // VSPLTW
|
|
2485U, // VSR
|
|
2490U, // VSRAB
|
|
2497U, // VSRAH
|
|
2504U, // VSRAW
|
|
2511U, // VSRB
|
|
2517U, // VSRH
|
|
2523U, // VSRO
|
|
2529U, // VSRW
|
|
2535U, // VSUBCUW
|
|
2544U, // VSUBFP
|
|
2552U, // VSUBSBS
|
|
2561U, // VSUBSHS
|
|
2570U, // VSUBSWS
|
|
2579U, // VSUBUBM
|
|
2588U, // VSUBUBS
|
|
2597U, // VSUBUHM
|
|
2606U, // VSUBUHS
|
|
2615U, // VSUBUWM
|
|
2624U, // VSUBUWS
|
|
2633U, // VSUM2SWS
|
|
2643U, // VSUM4SBS
|
|
2653U, // VSUM4SHS
|
|
2663U, // VSUM4UBS
|
|
2673U, // VSUMSWS
|
|
35450U, // VUPKHPX
|
|
35459U, // VUPKHSB
|
|
35468U, // VUPKHSH
|
|
35477U, // VUPKLPX
|
|
35486U, // VUPKLSB
|
|
35495U, // VUPKLSH
|
|
2736U, // VXOR
|
|
527024U, // V_SET0
|
|
2742U, // XOR
|
|
2742U, // XOR8
|
|
15035U, // XORI
|
|
15035U, // XORI8
|
|
15041U, // XORIS
|
|
15041U, // XORIS8
|
|
0U
|
|
};
|
|
|
|
const char *AsmStrs =
|
|
"add \000add \000addc \000adde \000addi \000addic \000addic. \000addis \000"
|
|
"addme \000addze \000\000and \000andc \000andis. \000andi. \000b \000b\000"
|
|
"bctr\000bctrl\000bl \000bla \000cmpd \000cmpdi \000cmpld \000cmpldi \000"
|
|
"cmplw \000cmplwi \000cmpw \000cmpwi \000cntlzd \000cntlzw \000creqv \000"
|
|
"cror \000dcba \000dcbf \000dcbi \000dcbst \000dcbt \000dcbtst \000dcbz "
|
|
"\000dcbzl \000divd \000divdu \000divw \000divwu \000dss \000dssall\000d"
|
|
"st \000dstst \000dststt \000dstt \000eqv \000extsb \000extsh \000extsw "
|
|
"\000fabs \000fadd \000fadds \000fcfid \000fcmpu \000fctidz \000fctiwz \000"
|
|
"fdiv \000fdivs \000fmadd \000fmadds \000fmr \000fmsub \000fmsubs \000fm"
|
|
"ul \000fmuls \000fnabs \000fneg \000fnmadd \000fnmadds \000fnmsub \000f"
|
|
"nmsubs \000frsp \000fsel \000fsqrt \000fsqrts \000fsub \000fsubs \000la"
|
|
" \000lbz \000lbzu \000lbzx \000ld \000ldarx \000ldu \000ldx \000lfd \000"
|
|
"lfdx \000lfs \000lfsx \000lha \000lhau \000lhax \000lhbrx \000lhz \000l"
|
|
"hzu \000lhzx \000li \000lis \000lvebx \000lvehx \000lvewx \000lvsl \000"
|
|
"lvsr \000lvx \000lvxl \000lwa \000lwarx \000lwax \000lwbrx \000lwz \000"
|
|
"lwzu \000lwzx \000mcrf \000mfcr \000mfctr \000mffs \000mflr \000mfspr \000"
|
|
"mfvscr \000mtcrf \000mtctr \000mtfsb0 \000mtfsb1 \000mtfsf \000mtlr \000"
|
|
"mtspr 256, \000mtvscr \000mulhd \000mulhdu \000mulhw \000mulhwu \000mul"
|
|
"ld \000mulli \000mullw \000nand \000neg \000nop\000nor \000or \000orc \000"
|
|
"ori \000oris \000rldcl \000rldicl \000rldicr \000rldimi \000rlwimi \000"
|
|
"rlwinm \000rlwinm. \000rlwnm \000sld \000slw \000srad \000sradi \000sra"
|
|
"w \000srawi \000srd \000srw \000stb \000stbu \000stbx \000std \000stdcx"
|
|
". \000stdu \000stdux \000stdx \000stfd \000stfdu \000stfdx \000stfiwx \000"
|
|
"stfs \000stfsu \000stfsx \000sth \000sthbrx \000sthu \000sthx \000stveb"
|
|
"x \000stvehx \000stvewx \000stvx \000stvxl \000stw \000stwbrx \000stwcx"
|
|
". \000stwu \000stwux \000stwx \000subf \000subfc \000subfe \000subfic \000"
|
|
"subfme \000subfze \000sync\000ba \000#TC_RETURNa \000#TC_RETURNa8 \000#"
|
|
"TC_RETURNd \000#TC_RETURNd8 \000#TC_RETURNr \000#TC_RETURNr8 \000trap\000"
|
|
"UPDATE_VRSAVE \000vaddcuw \000vaddfp \000vaddsbs \000vaddshs \000vaddsw"
|
|
"s \000vaddubm \000vaddubs \000vadduhm \000vadduhs \000vadduwm \000vaddu"
|
|
"ws \000vand \000vandc \000vavgsb \000vavgsh \000vavgsw \000vavgub \000v"
|
|
"avguh \000vavguw \000vcfsx \000vcfux \000vcmpbfp \000vcmpbfp. \000vcmpe"
|
|
"qfp \000vcmpeqfp. \000vcmpequb \000vcmpequb. \000vcmpequh \000vcmpequh."
|
|
" \000vcmpequw \000vcmpequw. \000vcmpgefp \000vcmpgefp. \000vcmpgtfp \000"
|
|
"vcmpgtfp. \000vcmpgtsb \000vcmpgtsb. \000vcmpgtsh \000vcmpgtsh. \000vcm"
|
|
"pgtsw \000vcmpgtsw. \000vcmpgtub \000vcmpgtub. \000vcmpgtuh \000vcmpgtu"
|
|
"h. \000vcmpgtuw \000vcmpgtuw. \000vctsxs \000vctuxs \000vexptefp \000vl"
|
|
"ogefp \000vmaddfp \000vmaxfp \000vmaxsb \000vmaxsh \000vmaxsw \000vmaxu"
|
|
"b \000vmaxuh \000vmaxuw \000vmhaddshs \000vmhraddshs \000vminfp \000vmi"
|
|
"nsb \000vminsh \000vminsw \000vminub \000vminuh \000vminuw \000vmladduh"
|
|
"m \000vmrghb \000vmrghh \000vmrghw \000vmrglb \000vmrglh \000vmrglw \000"
|
|
"vmsummbm \000vmsumshm \000vmsumshs \000vmsumubm \000vmsumuhm \000vmsumu"
|
|
"hs \000vmulesb \000vmulesh \000vmuleub \000vmuleuh \000vmulosb \000vmul"
|
|
"osh \000vmuloub \000vmulouh \000vnmsubfp \000vnor \000vor \000vperm \000"
|
|
"vpkpx \000vpkshss \000vpkshus \000vpkswss \000vpkswus \000vpkuhum \000v"
|
|
"pkuhus \000vpkuwum \000vpkuwus \000vrefp \000vrfim \000vrfin \000vrfip "
|
|
"\000vrfiz \000vrlb \000vrlh \000vrlw \000vrsqrtefp \000vsel \000vsl \000"
|
|
"vslb \000vsldoi \000vslh \000vslo \000vslw \000vspltb \000vsplth \000vs"
|
|
"pltisb \000vspltish \000vspltisw \000vspltw \000vsr \000vsrab \000vsrah"
|
|
" \000vsraw \000vsrb \000vsrh \000vsro \000vsrw \000vsubcuw \000vsubfp \000"
|
|
"vsubsbs \000vsubshs \000vsubsws \000vsububm \000vsububs \000vsubuhm \000"
|
|
"vsubuhs \000vsubuwm \000vsubuws \000vsum2sws \000vsum4sbs \000vsum4shs "
|
|
"\000vsum4ubs \000vsumsws \000vupkhpx \000vupkhsb \000vupkhsh \000vupklp"
|
|
"x \000vupklsb \000vupklsh \000vxor \000xor \000xori \000xoris \000";
|
|
|
|
|
|
#ifndef NO_ASM_WRITER_BOILERPLATE
|
|
if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
|
|
printInlineAsm(MI);
|
|
return;
|
|
} else if (MI->isLabel()) {
|
|
printLabel(MI);
|
|
return;
|
|
} else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
|
|
printImplicitDef(MI);
|
|
return;
|
|
} else if (MI->getOpcode() == TargetInstrInfo::KILL) {
|
|
printKill(MI);
|
|
return;
|
|
}
|
|
|
|
|
|
#endif
|
|
O << "\t";
|
|
|
|
// Emit the opcode for the instruction.
|
|
unsigned Bits = OpInfo[MI->getOpcode()];
|
|
assert(Bits != 0 && "Cannot print this instruction.");
|
|
O << AsmStrs+(Bits & 4095)-1;
|
|
|
|
|
|
// Fragment 0 encoded into 4 bits for 14 unique commands.
|
|
switch ((Bits >> 28) & 15) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
|
|
printOperand(MI, 0);
|
|
break;
|
|
case 1:
|
|
// ADJCALLSTACKDOWN, ADJCALLSTACKUP, ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP...
|
|
PrintSpecial(MI, "comment");
|
|
break;
|
|
case 2:
|
|
// B
|
|
printBranchOperand(MI, 0);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// BCC, BLR
|
|
printPredicateOperand(MI, 0, "cc");
|
|
break;
|
|
case 4:
|
|
// BCTR, BCTRL8_Darwin, BCTRL8_ELF, BCTRL_Darwin, BCTRL_SVR4, DSSALL, NOP...
|
|
return;
|
|
break;
|
|
case 5:
|
|
// BL8_Darwin, BL8_ELF, BL_Darwin, BL_SVR4, TAILB, TAILB8, TCRETURNdi, TC...
|
|
printCallOperand(MI, 0);
|
|
break;
|
|
case 6:
|
|
// BLA8_Darwin, BLA8_ELF, BLA_Darwin, BLA_SVR4, TAILBA, TAILBA8, TCRETURN...
|
|
printAbsAddrOperand(MI, 0);
|
|
break;
|
|
case 7:
|
|
// DCBA, DCBF, DCBI, DCBST, DCBT, DCBTST, DCBZ, DCBZL
|
|
printMemRegReg(MI, 0);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// DSS
|
|
printU5ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << ", ";
|
|
printU5ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 10:
|
|
// MTCRF
|
|
printcrbitm(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// MTFSB0, MTFSB1
|
|
printU5ImmOperand(MI, 0);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// MTFSF, STBU, STBU8, STDU, STFDU, STFSU, STHU, STHU8, STWU, STWU8
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
break;
|
|
case 13:
|
|
// MovePCtoLR, MovePCtoLR8
|
|
printPICLabel(MI, 0);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 1 encoded into 6 bits for 46 unique commands.
|
|
switch ((Bits >> 22) & 63) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
|
|
O << ", ";
|
|
break;
|
|
case 1:
|
|
// ADJCALLSTACKDOWN
|
|
O << " ADJCALLSTACKDOWN";
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ADJCALLSTACKUP
|
|
O << " ADJCALLSTACKUP";
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ATOMIC_CMP_SWAP_I16
|
|
O << " ATOMIC_CMP_SWAP_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 4:
|
|
// ATOMIC_CMP_SWAP_I32
|
|
O << " ATOMIC_CMP_SWAP_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 5:
|
|
// ATOMIC_CMP_SWAP_I64
|
|
O << " ATOMIC_CMP_SWAP_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 6:
|
|
// ATOMIC_CMP_SWAP_I8
|
|
O << " ATOMIC_CMP_SWAP_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 7:
|
|
// ATOMIC_LOAD_ADD_I16
|
|
O << " ATOMIC_LOAD_ADD_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 8:
|
|
// ATOMIC_LOAD_ADD_I32
|
|
O << " ATOMIC_LOAD_ADD_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 9:
|
|
// ATOMIC_LOAD_ADD_I64
|
|
O << " ATOMIC_LOAD_ADD_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 10:
|
|
// ATOMIC_LOAD_ADD_I8
|
|
O << " ATOMIC_LOAD_ADD_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 11:
|
|
// ATOMIC_LOAD_AND_I16
|
|
O << " ATOMIC_LOAD_AND_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 12:
|
|
// ATOMIC_LOAD_AND_I32
|
|
O << " ATOMIC_LOAD_AND_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 13:
|
|
// ATOMIC_LOAD_AND_I64
|
|
O << " ATOMIC_LOAD_AND_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 14:
|
|
// ATOMIC_LOAD_AND_I8
|
|
O << " ATOMIC_LOAD_AND_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 15:
|
|
// ATOMIC_LOAD_NAND_I16
|
|
O << " ATOMIC_LOAD_NAND_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 16:
|
|
// ATOMIC_LOAD_NAND_I32
|
|
O << " ATOMIC_LOAD_NAND_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 17:
|
|
// ATOMIC_LOAD_NAND_I64
|
|
O << " ATOMIC_LOAD_NAND_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 18:
|
|
// ATOMIC_LOAD_NAND_I8
|
|
O << " ATOMIC_LOAD_NAND_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 19:
|
|
// ATOMIC_LOAD_OR_I16
|
|
O << " ATOMIC_LOAD_OR_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 20:
|
|
// ATOMIC_LOAD_OR_I32
|
|
O << " ATOMIC_LOAD_OR_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 21:
|
|
// ATOMIC_LOAD_OR_I64
|
|
O << " ATOMIC_LOAD_OR_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 22:
|
|
// ATOMIC_LOAD_OR_I8
|
|
O << " ATOMIC_LOAD_OR_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 23:
|
|
// ATOMIC_LOAD_SUB_I16
|
|
O << " ATOMIC_LOAD_SUB_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 24:
|
|
// ATOMIC_LOAD_SUB_I32
|
|
O << " ATOMIC_LOAD_SUB_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 25:
|
|
// ATOMIC_LOAD_SUB_I64
|
|
O << " ATOMIC_LOAD_SUB_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 26:
|
|
// ATOMIC_LOAD_SUB_I8
|
|
O << " ATOMIC_LOAD_SUB_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 27:
|
|
// ATOMIC_LOAD_XOR_I16
|
|
O << " ATOMIC_LOAD_XOR_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 28:
|
|
// ATOMIC_LOAD_XOR_I32
|
|
O << " ATOMIC_LOAD_XOR_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 29:
|
|
// ATOMIC_LOAD_XOR_I64
|
|
O << " ATOMIC_LOAD_XOR_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 30:
|
|
// ATOMIC_LOAD_XOR_I8
|
|
O << " ATOMIC_LOAD_XOR_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 31:
|
|
// ATOMIC_SWAP_I16
|
|
O << " ATOMIC_SWAP_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 32:
|
|
// ATOMIC_SWAP_I32
|
|
O << " ATOMIC_SWAP_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 33:
|
|
// ATOMIC_SWAP_I64
|
|
O << " ATOMIC_SWAP_I64 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 34:
|
|
// ATOMIC_SWAP_I8
|
|
O << " ATOMIC_SWAP_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 35:
|
|
// BCC, TCRETURNai, TCRETURNai8, TCRETURNdi, TCRETURNdi8, TCRETURNri, TCR...
|
|
O << ' ';
|
|
break;
|
|
case 36:
|
|
// BL8_Darwin, BL8_ELF, BLA8_Darwin, BLA8_ELF, BLA_Darwin, BLA_SVR4, BL_D...
|
|
return;
|
|
break;
|
|
case 37:
|
|
// BLR
|
|
O << "lr ";
|
|
printPredicateOperand(MI, 0, "reg");
|
|
return;
|
|
break;
|
|
case 38:
|
|
// DYNALLOC
|
|
O << " DYNALLOC ";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printMemRegImm(MI, 2);
|
|
return;
|
|
break;
|
|
case 39:
|
|
// DYNALLOC8
|
|
O << " DYNALLOC8 ";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printMemRegImm(MI, 2);
|
|
return;
|
|
break;
|
|
case 40:
|
|
// MFVRSAVE
|
|
O << ", 256";
|
|
return;
|
|
break;
|
|
case 41:
|
|
// MTFSF
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 42:
|
|
// SELECT_CC_F4, SELECT_CC_F8, SELECT_CC_I4, SELECT_CC_I8, SELECT_CC_VRRC
|
|
O << " SELECT_CC PSEUDO!";
|
|
return;
|
|
break;
|
|
case 43:
|
|
// SPILL_CR
|
|
O << " SPILL_CR ";
|
|
printOperand(MI, 0);
|
|
O << ' ';
|
|
printMemRegImm(MI, 1);
|
|
return;
|
|
break;
|
|
case 44:
|
|
// STBU, STBU8, STFDU, STFSU, STHU, STHU8, STWU, STWU8
|
|
printSymbolLo(MI, 2);
|
|
O << '(';
|
|
printOperand(MI, 3);
|
|
O << ')';
|
|
return;
|
|
break;
|
|
case 45:
|
|
// STDU
|
|
printS16X4ImmOperand(MI, 2);
|
|
O << '(';
|
|
printOperand(MI, 3);
|
|
O << ')';
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 2 encoded into 4 bits for 15 unique commands.
|
|
switch ((Bits >> 18) & 15) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 1:
|
|
// BCC
|
|
printPredicateOperand(MI, 0, "reg");
|
|
O << ", ";
|
|
printBranchOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// CRSET, V_SET0
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 0);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// LA, LHAU8
|
|
printSymbolLo(MI, 2);
|
|
O << '(';
|
|
break;
|
|
case 4:
|
|
// LBZ, LBZ8, LFD, LFS, LHA, LHA8, LHZ, LHZ8, LWZ, LWZ8, STB, STB8, STFD,...
|
|
printMemRegImm(MI, 1);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// LBZU, LBZU8, LFDU, LFSU, LHAU, LHZU, LHZU8, LWZU, LWZU8
|
|
printMemRegImm(MI, 2);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// LBZX, LBZX8, LDARX, LDX, LFDX, LFSX, LHAX, LHAX8, LHBRX, LHZX, LHZX8, ...
|
|
printMemRegReg(MI, 1);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// LD, LWA, STD, STD_32
|
|
printMemRegImmShifted(MI, 1);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// LDU
|
|
printMemRegImmShifted(MI, 2);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// LDtoc
|
|
printTOCEntryLabel(MI, 1);
|
|
O << '(';
|
|
printOperand(MI, 2);
|
|
O << ')';
|
|
return;
|
|
break;
|
|
case 10:
|
|
// LI, LI8
|
|
printSymbolLo(MI, 1);
|
|
return;
|
|
break;
|
|
case 11:
|
|
// LIS, LIS8
|
|
printSymbolHi(MI, 1);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// MFOCRF
|
|
printcrbitm(MI, 1);
|
|
return;
|
|
break;
|
|
case 13:
|
|
// RLDIMI, RLWIMI, VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTH, VSPLTW
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
break;
|
|
case 14:
|
|
// VSPLTISB, VSPLTISH, VSPLTISW
|
|
printS5ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 3 encoded into 3 bits for 7 unique commands.
|
|
switch ((Bits >> 15) & 7) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, ADDI, ADDI8, ADDIC, ADDIC8, ADDI...
|
|
O << ", ";
|
|
break;
|
|
case 1:
|
|
// ADDME, ADDME8, ADDZE, ADDZE8, CNTLZD, CNTLZW, EXTSB, EXTSB8, EXTSH, EX...
|
|
return;
|
|
break;
|
|
case 2:
|
|
// LA
|
|
printOperand(MI, 1);
|
|
O << ')';
|
|
return;
|
|
break;
|
|
case 3:
|
|
// LHAU8
|
|
printOperand(MI, 3);
|
|
O << ')';
|
|
return;
|
|
break;
|
|
case 4:
|
|
// RLDIMI
|
|
printU6ImmOperand(MI, 3);
|
|
O << ", ";
|
|
printU6ImmOperand(MI, 4);
|
|
return;
|
|
break;
|
|
case 5:
|
|
// RLWIMI
|
|
printU5ImmOperand(MI, 3);
|
|
O << ", ";
|
|
printU5ImmOperand(MI, 4);
|
|
O << ", ";
|
|
printU5ImmOperand(MI, 5);
|
|
return;
|
|
break;
|
|
case 6:
|
|
// VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTH, VSPLTW
|
|
printU5ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 4 encoded into 3 bits for 6 unique commands.
|
|
switch ((Bits >> 12) & 7) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADD4, ADD8, ADDC, ADDC8, ADDE, ADDE8, AND, AND8, ANDC, ANDC8, CMPD, CM...
|
|
printOperand(MI, 2);
|
|
break;
|
|
case 1:
|
|
// ADDI, ADDI8, ADDIC, ADDIC8, ADDICo, CMPDI, CMPWI, MULLI, SUBFIC, SUBFI...
|
|
printS16ImmOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ADDIS, ADDIS8
|
|
printSymbolHi(MI, 2);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ANDISo, ANDISo8, ANDIo, ANDIo8, CMPLDI, CMPLWI, ORI, ORI8, ORIS, ORIS8...
|
|
printU16ImmOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 4:
|
|
// RLDICL, RLDICR, SRADI
|
|
printU6ImmOperand(MI, 2);
|
|
break;
|
|
case 5:
|
|
// RLWINM, RLWINMo, SRAWI
|
|
printU5ImmOperand(MI, 2);
|
|
break;
|
|
}
|
|
|
|
switch (MI->getOpcode()) {
|
|
case PPC::ADD4:
|
|
case PPC::ADD8:
|
|
case PPC::ADDC:
|
|
case PPC::ADDC8:
|
|
case PPC::ADDE:
|
|
case PPC::ADDE8:
|
|
case PPC::AND:
|
|
case PPC::AND8:
|
|
case PPC::ANDC:
|
|
case PPC::ANDC8:
|
|
case PPC::CMPD:
|
|
case PPC::CMPLD:
|
|
case PPC::CMPLW:
|
|
case PPC::CMPW:
|
|
case PPC::CREQV:
|
|
case PPC::CROR:
|
|
case PPC::DIVD:
|
|
case PPC::DIVDU:
|
|
case PPC::DIVW:
|
|
case PPC::DIVWU:
|
|
case PPC::EQV:
|
|
case PPC::EQV8:
|
|
case PPC::FADD:
|
|
case PPC::FADDS:
|
|
case PPC::FADDrtz:
|
|
case PPC::FCMPUD:
|
|
case PPC::FCMPUS:
|
|
case PPC::FDIV:
|
|
case PPC::FDIVS:
|
|
case PPC::FMUL:
|
|
case PPC::FMULS:
|
|
case PPC::FSUB:
|
|
case PPC::FSUBS:
|
|
case PPC::MULHD:
|
|
case PPC::MULHDU:
|
|
case PPC::MULHW:
|
|
case PPC::MULHWU:
|
|
case PPC::MULLD:
|
|
case PPC::MULLW:
|
|
case PPC::NAND:
|
|
case PPC::NAND8:
|
|
case PPC::NOR:
|
|
case PPC::NOR8:
|
|
case PPC::OR:
|
|
case PPC::OR4To8:
|
|
case PPC::OR8:
|
|
case PPC::OR8To4:
|
|
case PPC::ORC:
|
|
case PPC::ORC8:
|
|
case PPC::SLD:
|
|
case PPC::SLW:
|
|
case PPC::SRAD:
|
|
case PPC::SRADI:
|
|
case PPC::SRAW:
|
|
case PPC::SRAWI:
|
|
case PPC::SRD:
|
|
case PPC::SRW:
|
|
case PPC::STWUX:
|
|
case PPC::SUBF:
|
|
case PPC::SUBF8:
|
|
case PPC::SUBFC:
|
|
case PPC::SUBFC8:
|
|
case PPC::SUBFE:
|
|
case PPC::SUBFE8:
|
|
case PPC::VADDCUW:
|
|
case PPC::VADDFP:
|
|
case PPC::VADDSBS:
|
|
case PPC::VADDSHS:
|
|
case PPC::VADDSWS:
|
|
case PPC::VADDUBM:
|
|
case PPC::VADDUBS:
|
|
case PPC::VADDUHM:
|
|
case PPC::VADDUHS:
|
|
case PPC::VADDUWM:
|
|
case PPC::VADDUWS:
|
|
case PPC::VAND:
|
|
case PPC::VANDC:
|
|
case PPC::VAVGSB:
|
|
case PPC::VAVGSH:
|
|
case PPC::VAVGSW:
|
|
case PPC::VAVGUB:
|
|
case PPC::VAVGUH:
|
|
case PPC::VAVGUW:
|
|
case PPC::VCMPBFP:
|
|
case PPC::VCMPBFPo:
|
|
case PPC::VCMPEQFP:
|
|
case PPC::VCMPEQFPo:
|
|
case PPC::VCMPEQUB:
|
|
case PPC::VCMPEQUBo:
|
|
case PPC::VCMPEQUH:
|
|
case PPC::VCMPEQUHo:
|
|
case PPC::VCMPEQUW:
|
|
case PPC::VCMPEQUWo:
|
|
case PPC::VCMPGEFP:
|
|
case PPC::VCMPGEFPo:
|
|
case PPC::VCMPGTFP:
|
|
case PPC::VCMPGTFPo:
|
|
case PPC::VCMPGTSB:
|
|
case PPC::VCMPGTSBo:
|
|
case PPC::VCMPGTSH:
|
|
case PPC::VCMPGTSHo:
|
|
case PPC::VCMPGTSW:
|
|
case PPC::VCMPGTSWo:
|
|
case PPC::VCMPGTUB:
|
|
case PPC::VCMPGTUBo:
|
|
case PPC::VCMPGTUH:
|
|
case PPC::VCMPGTUHo:
|
|
case PPC::VCMPGTUW:
|
|
case PPC::VCMPGTUWo:
|
|
case PPC::VMAXFP:
|
|
case PPC::VMAXSB:
|
|
case PPC::VMAXSH:
|
|
case PPC::VMAXSW:
|
|
case PPC::VMAXUB:
|
|
case PPC::VMAXUH:
|
|
case PPC::VMAXUW:
|
|
case PPC::VMINFP:
|
|
case PPC::VMINSB:
|
|
case PPC::VMINSH:
|
|
case PPC::VMINSW:
|
|
case PPC::VMINUB:
|
|
case PPC::VMINUH:
|
|
case PPC::VMINUW:
|
|
case PPC::VMRGHB:
|
|
case PPC::VMRGHH:
|
|
case PPC::VMRGHW:
|
|
case PPC::VMRGLB:
|
|
case PPC::VMRGLH:
|
|
case PPC::VMRGLW:
|
|
case PPC::VMULESB:
|
|
case PPC::VMULESH:
|
|
case PPC::VMULEUB:
|
|
case PPC::VMULEUH:
|
|
case PPC::VMULOSB:
|
|
case PPC::VMULOSH:
|
|
case PPC::VMULOUB:
|
|
case PPC::VMULOUH:
|
|
case PPC::VNOR:
|
|
case PPC::VOR:
|
|
case PPC::VPKPX:
|
|
case PPC::VPKSHSS:
|
|
case PPC::VPKSHUS:
|
|
case PPC::VPKSWSS:
|
|
case PPC::VPKSWUS:
|
|
case PPC::VPKUHUM:
|
|
case PPC::VPKUHUS:
|
|
case PPC::VPKUWUM:
|
|
case PPC::VPKUWUS:
|
|
case PPC::VRLB:
|
|
case PPC::VRLH:
|
|
case PPC::VRLW:
|
|
case PPC::VSL:
|
|
case PPC::VSLB:
|
|
case PPC::VSLH:
|
|
case PPC::VSLO:
|
|
case PPC::VSLW:
|
|
case PPC::VSR:
|
|
case PPC::VSRAB:
|
|
case PPC::VSRAH:
|
|
case PPC::VSRAW:
|
|
case PPC::VSRB:
|
|
case PPC::VSRH:
|
|
case PPC::VSRO:
|
|
case PPC::VSRW:
|
|
case PPC::VSUBCUW:
|
|
case PPC::VSUBFP:
|
|
case PPC::VSUBSBS:
|
|
case PPC::VSUBSHS:
|
|
case PPC::VSUBSWS:
|
|
case PPC::VSUBUBM:
|
|
case PPC::VSUBUBS:
|
|
case PPC::VSUBUHM:
|
|
case PPC::VSUBUHS:
|
|
case PPC::VSUBUWM:
|
|
case PPC::VSUBUWS:
|
|
case PPC::VSUM2SWS:
|
|
case PPC::VSUM4SBS:
|
|
case PPC::VSUM4SHS:
|
|
case PPC::VSUM4UBS:
|
|
case PPC::VSUMSWS:
|
|
case PPC::VXOR:
|
|
case PPC::XOR:
|
|
case PPC::XOR8:
|
|
return;
|
|
break;
|
|
case PPC::FMADD:
|
|
case PPC::FMADDS:
|
|
case PPC::FMSUB:
|
|
case PPC::FMSUBS:
|
|
case PPC::FNMADD:
|
|
case PPC::FNMADDS:
|
|
case PPC::FNMSUB:
|
|
case PPC::FNMSUBS:
|
|
case PPC::FSELD:
|
|
case PPC::FSELS:
|
|
case PPC::RLDCL:
|
|
case PPC::RLDICL:
|
|
case PPC::RLDICR:
|
|
case PPC::VMADDFP:
|
|
case PPC::VMHADDSHS:
|
|
case PPC::VMHRADDSHS:
|
|
case PPC::VMLADDUHM:
|
|
case PPC::VMSUMMBM:
|
|
case PPC::VMSUMSHM:
|
|
case PPC::VMSUMSHS:
|
|
case PPC::VMSUMUBM:
|
|
case PPC::VMSUMUHM:
|
|
case PPC::VMSUMUHS:
|
|
case PPC::VNMSUBFP:
|
|
case PPC::VPERM:
|
|
case PPC::VSEL:
|
|
case PPC::VSLDOI:
|
|
O << ", ";
|
|
switch (MI->getOpcode()) {
|
|
case PPC::FMADD:
|
|
case PPC::FMADDS:
|
|
case PPC::FMSUB:
|
|
case PPC::FMSUBS:
|
|
case PPC::FNMADD:
|
|
case PPC::FNMADDS:
|
|
case PPC::FNMSUB:
|
|
case PPC::FNMSUBS:
|
|
case PPC::FSELD:
|
|
case PPC::FSELS:
|
|
case PPC::VMADDFP:
|
|
case PPC::VMHADDSHS:
|
|
case PPC::VMHRADDSHS:
|
|
case PPC::VMLADDUHM:
|
|
case PPC::VMSUMMBM:
|
|
case PPC::VMSUMSHM:
|
|
case PPC::VMSUMSHS:
|
|
case PPC::VMSUMUBM:
|
|
case PPC::VMSUMUHM:
|
|
case PPC::VMSUMUHS:
|
|
case PPC::VNMSUBFP:
|
|
case PPC::VPERM:
|
|
case PPC::VSEL: printOperand(MI, 3); break;
|
|
case PPC::RLDCL:
|
|
case PPC::RLDICL:
|
|
case PPC::RLDICR: printU6ImmOperand(MI, 3); break;
|
|
case PPC::VSLDOI: printU5ImmOperand(MI, 3); break;
|
|
}
|
|
return;
|
|
break;
|
|
case PPC::RLWINM:
|
|
case PPC::RLWINMo:
|
|
case PPC::RLWNM:
|
|
O << ", ";
|
|
printU5ImmOperand(MI, 3);
|
|
O << ", ";
|
|
printU5ImmOperand(MI, 4);
|
|
return;
|
|
break;
|
|
}
|
|
return;
|
|
}
|
|
|
|
|
|
/// getRegisterName - This method is automatically generated by tblgen
|
|
/// from the register set description. This returns the assembler name
|
|
/// for the specified register.
|
|
const char *PPCAsmPrinter::getRegisterName(unsigned RegNo) {
|
|
assert(RegNo && RegNo < 176 && "Invalid register number!");
|
|
|
|
static const unsigned RegAsmOffset[] = {
|
|
0, 3, 7, 9, 11, 13, 15, 19, 21, 23, 25, 27, 31, 34,
|
|
36, 38, 41, 45, 48, 51, 54, 57, 61, 64, 67, 70, 73, 77,
|
|
80, 83, 86, 89, 93, 96, 99, 102, 105, 109, 112, 115, 118, 121,
|
|
121, 125, 128, 131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171,
|
|
174, 178, 182, 186, 190, 194, 198, 202, 206, 210, 214, 217, 221, 225,
|
|
228, 231, 234, 237, 240, 243, 243, 246, 249, 252, 256, 260, 264, 268,
|
|
272, 276, 280, 284, 288, 292, 295, 299, 303, 307, 311, 315, 319, 323,
|
|
327, 331, 335, 338, 342, 346, 349, 352, 355, 358, 361, 364, 382, 385,
|
|
388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 431, 435, 439,
|
|
443, 447, 451, 455, 459, 463, 467, 471, 474, 478, 482, 485, 488, 491,
|
|
494, 497, 500, 246, 249, 252, 256, 260, 264, 268, 272, 276, 280, 284,
|
|
288, 292, 295, 299, 303, 307, 311, 315, 319, 323, 327, 331, 335, 338,
|
|
342, 346, 349, 352, 355, 358, 361, 0
|
|
};
|
|
|
|
const char *AsmStrs =
|
|
"ca\000cr0\0002\0001\0000\0003\000cr1\0006\0005\0004\0007\000cr2\00010\000"
|
|
"9\0008\00011\000cr3\00014\00013\00012\00015\000cr4\00018\00017\00016\000"
|
|
"19\000cr5\00022\00021\00020\00023\000cr6\00026\00025\00024\00027\000cr7"
|
|
"\00030\00029\00028\00031\000ctr\000f0\000f1\000f10\000f11\000f12\000f13"
|
|
"\000f14\000f15\000f16\000f17\000f18\000f19\000f2\000f20\000f21\000f22\000"
|
|
"f23\000f24\000f25\000f26\000f27\000f28\000f29\000f3\000f30\000f31\000f4"
|
|
"\000f5\000f6\000f7\000f8\000f9\000lr\000r0\000r1\000r10\000r11\000r12\000"
|
|
"r13\000r14\000r15\000r16\000r17\000r18\000r19\000r2\000r20\000r21\000r2"
|
|
"2\000r23\000r24\000r25\000r26\000r27\000r28\000r29\000r3\000r30\000r31\000"
|
|
"r4\000r5\000r6\000r7\000r8\000r9\000**ROUNDING MODE**\000v0\000v1\000v1"
|
|
"0\000v11\000v12\000v13\000v14\000v15\000v16\000v17\000v18\000v19\000v2\000"
|
|
"v20\000v21\000v22\000v23\000v24\000v25\000v26\000v27\000v28\000v29\000v"
|
|
"3\000v30\000v31\000v4\000v5\000v6\000v7\000v8\000v9\000VRsave\000";
|
|
return AsmStrs+RegAsmOffset[RegNo-1];
|
|
}
|
|
|