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5261 lines
133 KiB
5261 lines
133 KiB
//===- TableGen'erated file -------------------------------------*- C++ -*-===//
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//
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// Assembly Writer Source Fragment
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//
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// Automatically generated file, do not edit!
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//
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//===----------------------------------------------------------------------===//
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/// printInstruction - This method is automatically generated by tablegen
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/// from the instruction set description.
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void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
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static const unsigned OpInfo[] = {
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0U, // PHI
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0U, // INLINEASM
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0U, // DBG_LABEL
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0U, // EH_LABEL
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0U, // GC_LABEL
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0U, // KILL
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0U, // EXTRACT_SUBREG
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0U, // INSERT_SUBREG
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0U, // IMPLICIT_DEF
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0U, // SUBREG_TO_REG
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0U, // COPY_TO_REGCLASS
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1U, // ADCSSri
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7U, // ADCSSrr
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7U, // ADCSSrs
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135299085U, // ADCri
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135331853U, // ADCrr
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270532621U, // ADCrs
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137461777U, // ADDSri
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137461777U, // ADDSrr
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271679505U, // ADDSrs
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135299094U, // ADDri
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135331862U, // ADDrr
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270532630U, // ADDrs
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4194330U, // ADJCALLSTACKDOWN
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4194350U, // ADJCALLSTACKUP
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135299136U, // ANDri
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135331904U, // ANDrr
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270532672U, // ANDrs
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407896132U, // ATOMIC_CMP_SWAP_I16
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408944708U, // ATOMIC_CMP_SWAP_I32
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409993284U, // ATOMIC_CMP_SWAP_I8
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411041860U, // ATOMIC_LOAD_ADD_I16
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412090436U, // ATOMIC_LOAD_ADD_I32
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413139012U, // ATOMIC_LOAD_ADD_I8
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414187588U, // ATOMIC_LOAD_AND_I16
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415236164U, // ATOMIC_LOAD_AND_I32
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416284740U, // ATOMIC_LOAD_AND_I8
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417333316U, // ATOMIC_LOAD_NAND_I16
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418381892U, // ATOMIC_LOAD_NAND_I32
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419430468U, // ATOMIC_LOAD_NAND_I8
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420479044U, // ATOMIC_LOAD_OR_I16
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421527620U, // ATOMIC_LOAD_OR_I32
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422576196U, // ATOMIC_LOAD_OR_I8
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423624772U, // ATOMIC_LOAD_SUB_I16
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424673348U, // ATOMIC_LOAD_SUB_I32
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425721924U, // ATOMIC_LOAD_SUB_I8
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426770500U, // ATOMIC_LOAD_XOR_I16
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427819076U, // ATOMIC_LOAD_XOR_I32
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428867652U, // ATOMIC_LOAD_XOR_I8
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429916228U, // ATOMIC_SWAP_I16
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430964804U, // ATOMIC_SWAP_I32
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432013380U, // ATOMIC_SWAP_I8
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4194373U, // B
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137461832U, // BFC
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135299148U, // BICri
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135331916U, // BICrr
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270532684U, // BICrs
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536870992U, // BL
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4194388U, // BLX
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4194388U, // BLXr9
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674365529U, // BL_pred
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536870992U, // BLr9
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674365529U, // BLr9_pred
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4194396U, // BRIND
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96U, // BR_JTadd
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805306473U, // BR_JTm
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30408818U, // BR_JTr
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4194427U, // BX
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970981515U, // BX_RET
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4194427U, // BXr9
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674332814U, // Bcc
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1076986000U, // CLZ
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1076986004U, // CMNri
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1076986004U, // CMNrr
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1211203732U, // CMNrs
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1076986004U, // CMNzri
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1076986004U, // CMNzrr
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1211203732U, // CMNzrs
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1076986008U, // CMPri
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1076986008U, // CMPrr
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1211203736U, // CMPrs
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1076986008U, // CMPzri
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1076986008U, // CMPzrr
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1211203736U, // CMPzrs
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1342177348U, // CONSTPOOL_ENTRY
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135299228U, // EORri
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135331996U, // EORrr
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270532764U, // EORrs
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1106411680U, // FCONSTD
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1107460256U, // FCONSTS
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974127269U, // FMSTAT
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35651754U, // Int_MemBarrierV6
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1476395191U, // Int_MemBarrierV7
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36700330U, // Int_SyncBarrierV6
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1476395195U, // Int_SyncBarrierV7
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37748927U, // Int_eh_sjlj_setjmp
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1613955273U, // LDM
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1613955273U, // LDM_RET
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1211203789U, // LDR
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1211203793U, // LDRB
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271679697U, // LDRB_POST
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271679697U, // LDRB_PRE
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271679702U, // LDRD
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1076986075U, // LDREX
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1076986081U, // LDREXB
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137461992U, // LDREXD
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1076986095U, // LDREXH
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1211203830U, // LDRH
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271679734U, // LDRH_POST
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271679734U, // LDRH_PRE
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1211203835U, // LDRSB
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271679739U, // LDRSB_POST
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271679739U, // LDRSB_PRE
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1211203841U, // LDRSH
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271679745U, // LDRSH_POST
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271679745U, // LDRSH_PRE
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271679693U, // LDR_POST
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271679693U, // LDR_PRE
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1211203789U, // LDRcp
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1783628039U, // LEApcrel
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1784676615U, // LEApcrelJT
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1248854285U, // MLA
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1211203857U, // MLS
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137462037U, // MOVCCi
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137462037U, // MOVCCr
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271679765U, // MOVCCs
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137462041U, // MOVTi16
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1115914517U, // MOVi
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1076986142U, // MOVi16
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1076986133U, // MOVi2pieces
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1076986142U, // MOVi32imm
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1115685141U, // MOVr
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1115685141U, // MOVrx
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1249116437U, // MOVs
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1076986147U, // MOVsra_flag
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1076986147U, // MOVsrl_flag
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135332136U, // MUL
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1115914540U, // MVNi
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1115685164U, // MVNr
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1249116460U, // MVNs
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135299376U, // ORRri
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135332144U, // ORRrr
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270532912U, // ORRrs
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1922040116U, // PICADD
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2057306420U, // PICLDR
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2058354996U, // PICLDRB
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2059403572U, // PICLDRH
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2060452148U, // PICLDRSB
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2061500724U, // PICLDRSH
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2062549300U, // PICSTR
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2063597876U, // PICSTRB
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2064646452U, // PICSTRH
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1211203894U, // PKHBT
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1211203900U, // PKHTB
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1076986178U, // REV
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1076986182U, // REV16
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1076986188U, // REVSH
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137462098U, // RSBSri
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271679826U, // RSBSrs
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135299415U, // RSBri
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270532951U, // RSBrs
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347U, // RSCSri
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347U, // RSCSrs
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135299425U, // RSCri
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270532961U, // RSCrs
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357U, // SBCSSri
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357U, // SBCSSrr
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357U, // SBCSSrs
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135299435U, // SBCri
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135332203U, // SBCrr
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270532971U, // SBCrs
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1211203951U, // SBFX
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1211203956U, // SMLABB
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1211203963U, // SMLABT
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1248854402U, // SMLAL
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1211203976U, // SMLATB
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1211203983U, // SMLATT
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1211203990U, // SMLAWB
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1211203997U, // SMLAWT
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1211204004U, // SMMLA
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1211204010U, // SMMLS
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137462192U, // SMMUL
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137462198U, // SMULBB
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137462205U, // SMULBT
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1248854468U, // SMULL
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137462218U, // SMULTB
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137462225U, // SMULTT
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137462232U, // SMULWB
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137462239U, // SMULWT
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1613955558U, // STM
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1211204074U, // STR
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1211204078U, // STRB
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271581678U, // STRB_POST
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271581678U, // STRB_PRE
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271679987U, // STRD
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137462264U, // STREX
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137462270U, // STREXB
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1211204101U, // STREXD
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137462284U, // STREXH
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1211204115U, // STRH
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271581715U, // STRH_POST
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271581715U, // STRH_PRE
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271581674U, // STR_POST
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271581674U, // STR_PRE
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137462296U, // SUBSri
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137462296U, // SUBSrr
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271680024U, // SUBSrs
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135299613U, // SUBri
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135332381U, // SUBrr
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270533149U, // SUBrs
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137462305U, // SXTABrr
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1211204129U, // SXTABrr_rot
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137462311U, // SXTAHrr
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1211204135U, // SXTAHrr_rot
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1076986413U, // SXTBr
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137462317U, // SXTBr_rot
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1076986418U, // SXTHr
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137462322U, // SXTHr_rot
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1076986423U, // TEQri
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1076986423U, // TEQrr
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1211204151U, // TEQrs
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1476395579U, // TPsoft
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1076986446U, // TSTri
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1076986446U, // TSTrr
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1211204174U, // TSTrs
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1211204178U, // UBFX
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1211204183U, // UMAAL
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1248854621U, // UMLAL
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1248854627U, // UMULL
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137462377U, // UXTABrr
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1211204201U, // UXTABrr_rot
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137462383U, // UXTAHrr
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1211204207U, // UXTAHrr_rot
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1076986485U, // UXTB16r
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137462389U, // UXTB16r_rot
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1076986492U, // UXTBr
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137462396U, // UXTBr_rot
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1076986497U, // UXTHr
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137462401U, // UXTHr_rot
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1260454534U, // VABALsv2i64
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1261503110U, // VABALsv4i32
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1262551686U, // VABALsv8i16
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1263600262U, // VABALuv2i64
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1264648838U, // VABALuv4i32
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1265697414U, // VABALuv8i16
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1262551692U, // VABAsv16i8
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1260454540U, // VABAsv2i32
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1261503116U, // VABAsv4i16
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1260454540U, // VABAsv4i32
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1261503116U, // VABAsv8i16
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1262551692U, // VABAsv8i8
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1265697420U, // VABAuv16i8
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1263600268U, // VABAuv2i32
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1264648844U, // VABAuv4i16
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1263600268U, // VABAuv4i32
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1264648844U, // VABAuv8i16
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1265697420U, // VABAuv8i8
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186647185U, // VABDLsv2i64
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187695761U, // VABDLsv4i32
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188744337U, // VABDLsv8i16
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189792913U, // VABDLuv2i64
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190841489U, // VABDLuv4i32
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191890065U, // VABDLuv8i16
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167936663U, // VABDfd
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167936663U, // VABDfq
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188744343U, // VABDsv16i8
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186647191U, // VABDsv2i32
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187695767U, // VABDsv4i16
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186647191U, // VABDsv4i32
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187695767U, // VABDsv8i16
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188744343U, // VABDsv8i8
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191890071U, // VABDuv16i8
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189792919U, // VABDuv2i32
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190841495U, // VABDuv4i16
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189792919U, // VABDuv4i32
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190841495U, // VABDuv8i16
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191890071U, // VABDuv8i8
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1106412188U, // VABSD
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1107460764U, // VABSS
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1107460764U, // VABSfd
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1107460764U, // VABSfd_sfp
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1107460764U, // VABSfq
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1128268444U, // VABSv16i8
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1126171292U, // VABSv2i32
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1127219868U, // VABSv4i16
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1126171292U, // VABSv4i32
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1127219868U, // VABSv8i16
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1128268444U, // VABSv8i8
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167936673U, // VACGEd
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167936673U, // VACGEq
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167936679U, // VACGTd
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167936679U, // VACGTq
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166888109U, // VADDD
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|
192938674U, // VADDHNv2i32
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193987250U, // VADDHNv4i16
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195035826U, // VADDHNv8i8
|
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186647225U, // VADDLsv2i64
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187695801U, // VADDLsv4i32
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188744377U, // VADDLsv8i16
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189792953U, // VADDLuv2i64
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190841529U, // VADDLuv4i32
|
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191890105U, // VADDLuv8i16
|
|
167936685U, // VADDS
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186647231U, // VADDWsv2i64
|
|
187695807U, // VADDWsv4i32
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188744383U, // VADDWsv8i16
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|
189792959U, // VADDWuv2i64
|
|
190841535U, // VADDWuv4i32
|
|
191890111U, // VADDWuv8i16
|
|
167936685U, // VADDfd
|
|
167936685U, // VADDfd_sfp
|
|
167936685U, // VADDfq
|
|
196084397U, // VADDv16i8
|
|
192938669U, // VADDv1i64
|
|
193987245U, // VADDv2i32
|
|
192938669U, // VADDv2i64
|
|
195035821U, // VADDv4i16
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|
193987245U, // VADDv4i32
|
|
195035821U, // VADDv8i16
|
|
196084397U, // VADDv8i8
|
|
137462469U, // VANDd
|
|
137462469U, // VANDq
|
|
137462474U, // VBICd
|
|
137462474U, // VBICq
|
|
1211204303U, // VBSLd
|
|
1211204303U, // VBSLq
|
|
167936724U, // VCEQfd
|
|
167936724U, // VCEQfq
|
|
196084436U, // VCEQv16i8
|
|
193987284U, // VCEQv2i32
|
|
195035860U, // VCEQv4i16
|
|
193987284U, // VCEQv4i32
|
|
195035860U, // VCEQv8i16
|
|
196084436U, // VCEQv8i8
|
|
167936729U, // VCGEfd
|
|
167936729U, // VCGEfq
|
|
188744409U, // VCGEsv16i8
|
|
186647257U, // VCGEsv2i32
|
|
187695833U, // VCGEsv4i16
|
|
186647257U, // VCGEsv4i32
|
|
187695833U, // VCGEsv8i16
|
|
188744409U, // VCGEsv8i8
|
|
191890137U, // VCGEuv16i8
|
|
189792985U, // VCGEuv2i32
|
|
190841561U, // VCGEuv4i16
|
|
189792985U, // VCGEuv4i32
|
|
190841561U, // VCGEuv8i16
|
|
191890137U, // VCGEuv8i8
|
|
167936734U, // VCGTfd
|
|
167936734U, // VCGTfq
|
|
188744414U, // VCGTsv16i8
|
|
186647262U, // VCGTsv2i32
|
|
187695838U, // VCGTsv4i16
|
|
186647262U, // VCGTsv4i32
|
|
187695838U, // VCGTsv8i16
|
|
188744414U, // VCGTsv8i8
|
|
191890142U, // VCGTuv16i8
|
|
189792990U, // VCGTuv2i32
|
|
190841566U, // VCGTuv4i16
|
|
189792990U, // VCGTuv4i32
|
|
190841566U, // VCGTuv8i16
|
|
191890142U, // VCGTuv8i8
|
|
1128268515U, // VCLSv16i8
|
|
1126171363U, // VCLSv2i32
|
|
1127219939U, // VCLSv4i16
|
|
1126171363U, // VCLSv4i32
|
|
1127219939U, // VCLSv8i16
|
|
1128268515U, // VCLSv8i8
|
|
1135608552U, // VCLZv16i8
|
|
1133511400U, // VCLZv2i32
|
|
1134559976U, // VCLZv4i16
|
|
1133511400U, // VCLZv4i32
|
|
1134559976U, // VCLZv8i16
|
|
1135608552U, // VCLZv8i8
|
|
1106412269U, // VCMPED
|
|
1107460845U, // VCMPES
|
|
703890157U, // VCMPEZD
|
|
704938733U, // VCMPEZS
|
|
1136755443U, // VCNTd
|
|
1136755443U, // VCNTq
|
|
1137705720U, // VCVTDS
|
|
1138754296U, // VCVTSD
|
|
1140130552U, // VCVTf2sd
|
|
1140130552U, // VCVTf2sd_sfp
|
|
1140130552U, // VCVTf2sq
|
|
1141179128U, // VCVTf2ud
|
|
1141179128U, // VCVTf2ud_sfp
|
|
1141179128U, // VCVTf2uq
|
|
200442616U, // VCVTf2xsd
|
|
200442616U, // VCVTf2xsq
|
|
201491192U, // VCVTf2xud
|
|
201491192U, // VCVTf2xuq
|
|
1142227704U, // VCVTs2fd
|
|
1142227704U, // VCVTs2fd_sfp
|
|
1142227704U, // VCVTs2fq
|
|
1143276280U, // VCVTu2fd
|
|
1143276280U, // VCVTu2fd_sfp
|
|
1143276280U, // VCVTu2fq
|
|
202539768U, // VCVTxs2fd
|
|
202539768U, // VCVTxs2fq
|
|
203588344U, // VCVTxu2fd
|
|
203588344U, // VCVTxu2fq
|
|
166888189U, // VDIVD
|
|
167936765U, // VDIVS
|
|
1144095490U, // VDUP16d
|
|
1144095490U, // VDUP16q
|
|
1145144066U, // VDUP32d
|
|
1145144066U, // VDUP32q
|
|
1136755458U, // VDUP8d
|
|
1136755458U, // VDUP8q
|
|
204571394U, // VDUPLN16d
|
|
204571394U, // VDUPLN16q
|
|
205619970U, // VDUPLN32d
|
|
205619970U, // VDUPLN32q
|
|
197231362U, // VDUPLN8d
|
|
197231362U, // VDUPLN8q
|
|
205619970U, // VDUPLNfd
|
|
205619970U, // VDUPLNfq
|
|
1145144066U, // VDUPfd
|
|
1145144066U, // VDUPfdf
|
|
1145144066U, // VDUPfq
|
|
1145144066U, // VDUPfqf
|
|
137462535U, // VEORd
|
|
137462535U, // VEORq
|
|
1278313228U, // VEXTd16
|
|
1279361804U, // VEXTd32
|
|
1270973196U, // VEXTd8
|
|
1279361804U, // VEXTdf
|
|
1278313228U, // VEXTq16
|
|
1279361804U, // VEXTq32
|
|
1270973196U, // VEXTq8
|
|
1279361804U, // VEXTqf
|
|
205619360U, // VGETLNi32
|
|
187695264U, // VGETLNs16
|
|
188743840U, // VGETLNs8
|
|
190840992U, // VGETLNu16
|
|
191889568U, // VGETLNu8
|
|
188744465U, // VHADDsv16i8
|
|
186647313U, // VHADDsv2i32
|
|
187695889U, // VHADDsv4i16
|
|
186647313U, // VHADDsv4i32
|
|
187695889U, // VHADDsv8i16
|
|
188744465U, // VHADDsv8i8
|
|
191890193U, // VHADDuv16i8
|
|
189793041U, // VHADDuv2i32
|
|
190841617U, // VHADDuv4i16
|
|
189793041U, // VHADDuv4i32
|
|
190841617U, // VHADDuv8i16
|
|
191890193U, // VHADDuv8i8
|
|
188744471U, // VHSUBsv16i8
|
|
186647319U, // VHSUBsv2i32
|
|
187695895U, // VHSUBsv4i16
|
|
186647319U, // VHSUBsv4i32
|
|
187695895U, // VHSUBsv8i16
|
|
188744471U, // VHSUBsv8i8
|
|
191890199U, // VHSUBuv16i8
|
|
189793047U, // VHSUBuv2i32
|
|
190841623U, // VHSUBuv4i16
|
|
189793047U, // VHSUBuv4i32
|
|
190841623U, // VHSUBuv8i16
|
|
191890199U, // VHSUBuv8i8
|
|
340886301U, // VLD1d16
|
|
341934877U, // VLD1d32
|
|
342983453U, // VLD1d64
|
|
344032029U, // VLD1d8
|
|
341934877U, // VLD1df
|
|
339051293U, // VLD1q16
|
|
340099869U, // VLD1q32
|
|
345342749U, // VLD1q64
|
|
331711261U, // VLD1q8
|
|
340099869U, // VLD1qf
|
|
2219934498U, // VLD2LNd16
|
|
2220983074U, // VLD2LNd32
|
|
2223080226U, // VLD2LNd8
|
|
2219934498U, // VLD2LNq16a
|
|
2219934498U, // VLD2LNq16b
|
|
2220983074U, // VLD2LNq32a
|
|
2220983074U, // VLD2LNq32b
|
|
2354152226U, // VLD2d16
|
|
2355200802U, // VLD2d32
|
|
2356249373U, // VLD2d64
|
|
2357297954U, // VLD2d8
|
|
2488369954U, // VLD2q16
|
|
2489418530U, // VLD2q32
|
|
2491515682U, // VLD2q8
|
|
2622587687U, // VLD3LNd16
|
|
2623636263U, // VLD3LNd32
|
|
2625733415U, // VLD3LNd8
|
|
2622587687U, // VLD3LNq16a
|
|
2622587687U, // VLD3LNq16b
|
|
2623636263U, // VLD3LNq32a
|
|
2623636263U, // VLD3LNq32b
|
|
2756805415U, // VLD3d16
|
|
2757853991U, // VLD3d32
|
|
2758902557U, // VLD3d64
|
|
2759951143U, // VLD3d8
|
|
2488369959U, // VLD3q16a
|
|
2488369959U, // VLD3q16b
|
|
2489418535U, // VLD3q32a
|
|
2489418535U, // VLD3q32b
|
|
2491515687U, // VLD3q8a
|
|
2491515687U, // VLD3q8b
|
|
2891023148U, // VLD4LNd16
|
|
2892071724U, // VLD4LNd32
|
|
2894168876U, // VLD4LNd8
|
|
2891023148U, // VLD4LNq16a
|
|
2891023148U, // VLD4LNq16b
|
|
2892071724U, // VLD4LNq32a
|
|
2892071724U, // VLD4LNq32b
|
|
2488369964U, // VLD4d16
|
|
2489418540U, // VLD4d32
|
|
2490467101U, // VLD4d64
|
|
2491515692U, // VLD4d8
|
|
2219934508U, // VLD4q16a
|
|
2219934508U, // VLD4q16b
|
|
2220983084U, // VLD4q32a
|
|
2220983084U, // VLD4q32b
|
|
2223080236U, // VLD4q8a
|
|
2223080236U, // VLD4q8b
|
|
2952790833U, // VLDMD
|
|
2952790833U, // VLDMS
|
|
210862902U, // VLDRD
|
|
137757499U, // VLDRQ
|
|
205620022U, // VLDRS
|
|
167936834U, // VMAXfd
|
|
167936834U, // VMAXfq
|
|
188744514U, // VMAXsv16i8
|
|
186647362U, // VMAXsv2i32
|
|
187695938U, // VMAXsv4i16
|
|
186647362U, // VMAXsv4i32
|
|
187695938U, // VMAXsv8i16
|
|
188744514U, // VMAXsv8i8
|
|
191890242U, // VMAXuv16i8
|
|
189793090U, // VMAXuv2i32
|
|
190841666U, // VMAXuv4i16
|
|
189793090U, // VMAXuv4i32
|
|
190841666U, // VMAXuv8i16
|
|
191890242U, // VMAXuv8i8
|
|
167936839U, // VMINfd
|
|
167936839U, // VMINfq
|
|
188744519U, // VMINsv16i8
|
|
186647367U, // VMINsv2i32
|
|
187695943U, // VMINsv4i16
|
|
186647367U, // VMINsv4i32
|
|
187695943U, // VMINsv8i16
|
|
188744519U, // VMINsv8i8
|
|
191890247U, // VMINuv16i8
|
|
189793095U, // VMINuv2i32
|
|
190841671U, // VMINuv4i16
|
|
189793095U, // VMINuv4i32
|
|
190841671U, // VMINuv8i16
|
|
191890247U, // VMINuv8i8
|
|
1240630092U, // VMLAD
|
|
320930641U, // VMLALslsv2i32
|
|
321979217U, // VMLALslsv4i16
|
|
324076369U, // VMLALsluv2i32
|
|
325124945U, // VMLALsluv4i16
|
|
1260454737U, // VMLALsv2i64
|
|
1261503313U, // VMLALsv4i32
|
|
1262551889U, // VMLALsv8i16
|
|
1263600465U, // VMLALuv2i64
|
|
1264649041U, // VMLALuv4i32
|
|
1265697617U, // VMLALuv8i16
|
|
1241678668U, // VMLAS
|
|
1241678668U, // VMLAfd
|
|
1241678668U, // VMLAfq
|
|
302154572U, // VMLAslfd
|
|
302154572U, // VMLAslfq
|
|
328270668U, // VMLAslv2i32
|
|
329319244U, // VMLAslv4i16
|
|
328270668U, // VMLAslv4i32
|
|
329319244U, // VMLAslv8i16
|
|
1269891916U, // VMLAv16i8
|
|
1267794764U, // VMLAv2i32
|
|
1268843340U, // VMLAv4i16
|
|
1267794764U, // VMLAv4i32
|
|
1268843340U, // VMLAv8i16
|
|
1269891916U, // VMLAv8i8
|
|
1240630103U, // VMLSD
|
|
320930652U, // VMLSLslsv2i32
|
|
321979228U, // VMLSLslsv4i16
|
|
324076380U, // VMLSLsluv2i32
|
|
325124956U, // VMLSLsluv4i16
|
|
1260454748U, // VMLSLsv2i64
|
|
1261503324U, // VMLSLsv4i32
|
|
1262551900U, // VMLSLsv8i16
|
|
1263600476U, // VMLSLuv2i64
|
|
1264649052U, // VMLSLuv4i32
|
|
1265697628U, // VMLSLuv8i16
|
|
1241678679U, // VMLSS
|
|
1241678679U, // VMLSfd
|
|
1241678679U, // VMLSfq
|
|
302154583U, // VMLSslfd
|
|
302154583U, // VMLSslfq
|
|
328270679U, // VMLSslv2i32
|
|
329319255U, // VMLSslv4i16
|
|
328270679U, // VMLSslv4i32
|
|
329319255U, // VMLSslv8i16
|
|
1269891927U, // VMLSv16i8
|
|
1267794775U, // VMLSv2i32
|
|
1268843351U, // VMLSv4i16
|
|
1267794775U, // VMLSv4i32
|
|
1268843351U, // VMLSv8i16
|
|
1269891927U, // VMLSv8i8
|
|
1106411680U, // VMOVD
|
|
137461920U, // VMOVDRR
|
|
166887584U, // VMOVDcc
|
|
1076986016U, // VMOVDneon
|
|
1126171490U, // VMOVLsv2i64
|
|
1127220066U, // VMOVLsv4i32
|
|
1128268642U, // VMOVLsv8i16
|
|
1129317218U, // VMOVLuv2i64
|
|
1130365794U, // VMOVLuv4i32
|
|
1131414370U, // VMOVLuv8i16
|
|
1132462952U, // VMOVNv2i32
|
|
1133511528U, // VMOVNv4i16
|
|
1134560104U, // VMOVNv8i8
|
|
1076986016U, // VMOVQ
|
|
137461920U, // VMOVRRD
|
|
1076986016U, // VMOVRS
|
|
1107460256U, // VMOVS
|
|
1076986016U, // VMOVSR
|
|
167936160U, // VMOVScc
|
|
1136033952U, // VMOVv16i8
|
|
1132920992U, // VMOVv1i64
|
|
1134002336U, // VMOVv2i32
|
|
1132920992U, // VMOVv2i64
|
|
1135083680U, // VMOVv4i16
|
|
1134002336U, // VMOVv4i32
|
|
1135083680U, // VMOVv8i16
|
|
1136033952U, // VMOVv8i8
|
|
166888302U, // VMULD
|
|
211813235U, // VMULLp
|
|
1260389235U, // VMULLslsv2i32
|
|
1261437811U, // VMULLslsv4i16
|
|
1263534963U, // VMULLsluv2i32
|
|
1264583539U, // VMULLsluv4i16
|
|
186647411U, // VMULLsv2i64
|
|
187695987U, // VMULLsv4i32
|
|
188744563U, // VMULLsv8i16
|
|
189793139U, // VMULLuv2i64
|
|
190841715U, // VMULLuv4i32
|
|
191890291U, // VMULLuv8i16
|
|
167936878U, // VMULS
|
|
167936878U, // VMULfd
|
|
167936878U, // VMULfd_sfp
|
|
167936878U, // VMULfq
|
|
211813230U, // VMULpd
|
|
211813230U, // VMULpq
|
|
1241678702U, // VMULslfd
|
|
1241678702U, // VMULslfq
|
|
1267729262U, // VMULslv2i32
|
|
1268777838U, // VMULslv4i16
|
|
1267729262U, // VMULslv4i32
|
|
1268777838U, // VMULslv8i16
|
|
196084590U, // VMULv16i8
|
|
193987438U, // VMULv2i32
|
|
195036014U, // VMULv4i16
|
|
193987438U, // VMULv4i32
|
|
195036014U, // VMULv8i16
|
|
196084590U, // VMULv8i8
|
|
1076986745U, // VMVNd
|
|
1076986745U, // VMVNq
|
|
1106412414U, // VNEGD
|
|
166888318U, // VNEGDcc
|
|
1107460990U, // VNEGS
|
|
167936894U, // VNEGScc
|
|
1107460990U, // VNEGf32d
|
|
1107460990U, // VNEGf32d_sfp
|
|
1107460990U, // VNEGf32q
|
|
1127220094U, // VNEGs16d
|
|
1127220094U, // VNEGs16q
|
|
1126171518U, // VNEGs32d
|
|
1126171518U, // VNEGs32q
|
|
1128268670U, // VNEGs8d
|
|
1128268670U, // VNEGs8q
|
|
1240630147U, // VNMLAD
|
|
1241678723U, // VNMLAS
|
|
1240630153U, // VNMLSD
|
|
1241678729U, // VNMLSS
|
|
166888335U, // VNMULD
|
|
167936911U, // VNMULS
|
|
137462677U, // VORNd
|
|
137462677U, // VORNq
|
|
137462682U, // VORRd
|
|
137462682U, // VORRq
|
|
188810143U, // VPADALsv16i8
|
|
186712991U, // VPADALsv2i32
|
|
187761567U, // VPADALsv4i16
|
|
186712991U, // VPADALsv4i32
|
|
187761567U, // VPADALsv8i16
|
|
188810143U, // VPADALsv8i8
|
|
191955871U, // VPADALuv16i8
|
|
189858719U, // VPADALuv2i32
|
|
190907295U, // VPADALuv4i16
|
|
189858719U, // VPADALuv4i32
|
|
190907295U, // VPADALuv8i16
|
|
191955871U, // VPADALuv8i8
|
|
1128268710U, // VPADDLsv16i8
|
|
1126171558U, // VPADDLsv2i32
|
|
1127220134U, // VPADDLsv4i16
|
|
1126171558U, // VPADDLsv4i32
|
|
1127220134U, // VPADDLsv8i16
|
|
1128268710U, // VPADDLsv8i8
|
|
1131414438U, // VPADDLuv16i8
|
|
1129317286U, // VPADDLuv2i32
|
|
1130365862U, // VPADDLuv4i16
|
|
1129317286U, // VPADDLuv4i32
|
|
1130365862U, // VPADDLuv8i16
|
|
1131414438U, // VPADDLuv8i8
|
|
167936941U, // VPADDf
|
|
195036077U, // VPADDi16
|
|
193987501U, // VPADDi32
|
|
196084653U, // VPADDi8
|
|
167936947U, // VPMAXf
|
|
187696051U, // VPMAXs16
|
|
186647475U, // VPMAXs32
|
|
188744627U, // VPMAXs8
|
|
190841779U, // VPMAXu16
|
|
189793203U, // VPMAXu32
|
|
191890355U, // VPMAXu8
|
|
167936953U, // VPMINf
|
|
187696057U, // VPMINs16
|
|
186647481U, // VPMINs32
|
|
188744633U, // VPMINs8
|
|
190841785U, // VPMINu16
|
|
189793209U, // VPMINu32
|
|
191890361U, // VPMINu8
|
|
1128268735U, // VQABSv16i8
|
|
1126171583U, // VQABSv2i32
|
|
1127220159U, // VQABSv4i16
|
|
1126171583U, // VQABSv4i32
|
|
1127220159U, // VQABSv8i16
|
|
1128268735U, // VQABSv8i8
|
|
188744645U, // VQADDsv16i8
|
|
212861893U, // VQADDsv1i64
|
|
186647493U, // VQADDsv2i32
|
|
212861893U, // VQADDsv2i64
|
|
187696069U, // VQADDsv4i16
|
|
186647493U, // VQADDsv4i32
|
|
187696069U, // VQADDsv8i16
|
|
188744645U, // VQADDsv8i8
|
|
191890373U, // VQADDuv16i8
|
|
213910469U, // VQADDuv1i64
|
|
189793221U, // VQADDuv2i32
|
|
213910469U, // VQADDuv2i64
|
|
190841797U, // VQADDuv4i16
|
|
189793221U, // VQADDuv4i32
|
|
190841797U, // VQADDuv8i16
|
|
191890373U, // VQADDuv8i8
|
|
320930763U, // VQDMLALslv2i32
|
|
321979339U, // VQDMLALslv4i16
|
|
1260454859U, // VQDMLALv2i64
|
|
1261503435U, // VQDMLALv4i32
|
|
320930771U, // VQDMLSLslv2i32
|
|
321979347U, // VQDMLSLslv4i16
|
|
1260454867U, // VQDMLSLv2i64
|
|
1261503443U, // VQDMLSLv4i32
|
|
1260389339U, // VQDMULHslv2i32
|
|
1261437915U, // VQDMULHslv4i16
|
|
1260389339U, // VQDMULHslv4i32
|
|
1261437915U, // VQDMULHslv8i16
|
|
186647515U, // VQDMULHv2i32
|
|
187696091U, // VQDMULHv4i16
|
|
186647515U, // VQDMULHv4i32
|
|
187696091U, // VQDMULHv8i16
|
|
1260389347U, // VQDMULLslv2i32
|
|
1261437923U, // VQDMULLslv4i16
|
|
186647523U, // VQDMULLv2i64
|
|
187696099U, // VQDMULLv4i32
|
|
1152386027U, // VQMOVNsuv2i32
|
|
1126171627U, // VQMOVNsuv4i16
|
|
1127220203U, // VQMOVNsuv8i8
|
|
1152386035U, // VQMOVNsv2i32
|
|
1126171635U, // VQMOVNsv4i16
|
|
1127220211U, // VQMOVNsv8i8
|
|
1153434611U, // VQMOVNuv2i32
|
|
1129317363U, // VQMOVNuv4i16
|
|
1130365939U, // VQMOVNuv8i8
|
|
1128268794U, // VQNEGv16i8
|
|
1126171642U, // VQNEGv2i32
|
|
1127220218U, // VQNEGv4i16
|
|
1126171642U, // VQNEGv4i32
|
|
1127220218U, // VQNEGv8i16
|
|
1128268794U, // VQNEGv8i8
|
|
1260389376U, // VQRDMULHslv2i32
|
|
1261437952U, // VQRDMULHslv4i16
|
|
1260389376U, // VQRDMULHslv4i32
|
|
1261437952U, // VQRDMULHslv8i16
|
|
186647552U, // VQRDMULHv2i32
|
|
187696128U, // VQRDMULHv4i16
|
|
186647552U, // VQRDMULHv4i32
|
|
187696128U, // VQRDMULHv8i16
|
|
188744713U, // VQRSHLsv16i8
|
|
212861961U, // VQRSHLsv1i64
|
|
186647561U, // VQRSHLsv2i32
|
|
212861961U, // VQRSHLsv2i64
|
|
187696137U, // VQRSHLsv4i16
|
|
186647561U, // VQRSHLsv4i32
|
|
187696137U, // VQRSHLsv8i16
|
|
188744713U, // VQRSHLsv8i8
|
|
191890441U, // VQRSHLuv16i8
|
|
213910537U, // VQRSHLuv1i64
|
|
189793289U, // VQRSHLuv2i32
|
|
213910537U, // VQRSHLuv2i64
|
|
190841865U, // VQRSHLuv4i16
|
|
189793289U, // VQRSHLuv4i32
|
|
190841865U, // VQRSHLuv8i16
|
|
191890441U, // VQRSHLuv8i8
|
|
212861968U, // VQRSHRNsv2i32
|
|
186647568U, // VQRSHRNsv4i16
|
|
187696144U, // VQRSHRNsv8i8
|
|
213910544U, // VQRSHRNuv2i32
|
|
189793296U, // VQRSHRNuv4i16
|
|
190841872U, // VQRSHRNuv8i8
|
|
212861976U, // VQRSHRUNv2i32
|
|
186647576U, // VQRSHRUNv4i16
|
|
187696152U, // VQRSHRUNv8i8
|
|
188744737U, // VQSHLsiv16i8
|
|
212861985U, // VQSHLsiv1i64
|
|
186647585U, // VQSHLsiv2i32
|
|
212861985U, // VQSHLsiv2i64
|
|
187696161U, // VQSHLsiv4i16
|
|
186647585U, // VQSHLsiv4i32
|
|
187696161U, // VQSHLsiv8i16
|
|
188744737U, // VQSHLsiv8i8
|
|
188744743U, // VQSHLsuv16i8
|
|
212861991U, // VQSHLsuv1i64
|
|
186647591U, // VQSHLsuv2i32
|
|
212861991U, // VQSHLsuv2i64
|
|
187696167U, // VQSHLsuv4i16
|
|
186647591U, // VQSHLsuv4i32
|
|
187696167U, // VQSHLsuv8i16
|
|
188744743U, // VQSHLsuv8i8
|
|
188744737U, // VQSHLsv16i8
|
|
212861985U, // VQSHLsv1i64
|
|
186647585U, // VQSHLsv2i32
|
|
212861985U, // VQSHLsv2i64
|
|
187696161U, // VQSHLsv4i16
|
|
186647585U, // VQSHLsv4i32
|
|
187696161U, // VQSHLsv8i16
|
|
188744737U, // VQSHLsv8i8
|
|
191890465U, // VQSHLuiv16i8
|
|
213910561U, // VQSHLuiv1i64
|
|
189793313U, // VQSHLuiv2i32
|
|
213910561U, // VQSHLuiv2i64
|
|
190841889U, // VQSHLuiv4i16
|
|
189793313U, // VQSHLuiv4i32
|
|
190841889U, // VQSHLuiv8i16
|
|
191890465U, // VQSHLuiv8i8
|
|
191890465U, // VQSHLuv16i8
|
|
213910561U, // VQSHLuv1i64
|
|
189793313U, // VQSHLuv2i32
|
|
213910561U, // VQSHLuv2i64
|
|
190841889U, // VQSHLuv4i16
|
|
189793313U, // VQSHLuv4i32
|
|
190841889U, // VQSHLuv8i16
|
|
191890465U, // VQSHLuv8i8
|
|
212861998U, // VQSHRNsv2i32
|
|
186647598U, // VQSHRNsv4i16
|
|
187696174U, // VQSHRNsv8i8
|
|
213910574U, // VQSHRNuv2i32
|
|
189793326U, // VQSHRNuv4i16
|
|
190841902U, // VQSHRNuv8i8
|
|
212862005U, // VQSHRUNv2i32
|
|
186647605U, // VQSHRUNv4i16
|
|
187696181U, // VQSHRUNv8i8
|
|
188744765U, // VQSUBsv16i8
|
|
212862013U, // VQSUBsv1i64
|
|
186647613U, // VQSUBsv2i32
|
|
212862013U, // VQSUBsv2i64
|
|
187696189U, // VQSUBsv4i16
|
|
186647613U, // VQSUBsv4i32
|
|
187696189U, // VQSUBsv8i16
|
|
188744765U, // VQSUBsv8i8
|
|
191890493U, // VQSUBuv16i8
|
|
213910589U, // VQSUBuv1i64
|
|
189793341U, // VQSUBuv2i32
|
|
213910589U, // VQSUBuv2i64
|
|
190841917U, // VQSUBuv4i16
|
|
189793341U, // VQSUBuv4i32
|
|
190841917U, // VQSUBuv8i16
|
|
191890493U, // VQSUBuv8i8
|
|
192939075U, // VRADDHNv2i32
|
|
193987651U, // VRADDHNv4i16
|
|
195036227U, // VRADDHNv8i8
|
|
1129317451U, // VRECPEd
|
|
1107461195U, // VRECPEfd
|
|
1107461195U, // VRECPEfq
|
|
1129317451U, // VRECPEq
|
|
167937106U, // VRECPSfd
|
|
167937106U, // VRECPSfq
|
|
1136755801U, // VREV16d8
|
|
1136755801U, // VREV16q8
|
|
1144095840U, // VREV32d16
|
|
1136755808U, // VREV32d8
|
|
1144095840U, // VREV32q16
|
|
1136755808U, // VREV32q8
|
|
1144095847U, // VREV64d16
|
|
1145144423U, // VREV64d32
|
|
1136755815U, // VREV64d8
|
|
1145144423U, // VREV64df
|
|
1144095847U, // VREV64q16
|
|
1145144423U, // VREV64q32
|
|
1136755815U, // VREV64q8
|
|
1145144423U, // VREV64qf
|
|
188744814U, // VRHADDsv16i8
|
|
186647662U, // VRHADDsv2i32
|
|
187696238U, // VRHADDsv4i16
|
|
186647662U, // VRHADDsv4i32
|
|
187696238U, // VRHADDsv8i16
|
|
188744814U, // VRHADDsv8i8
|
|
191890542U, // VRHADDuv16i8
|
|
189793390U, // VRHADDuv2i32
|
|
190841966U, // VRHADDuv4i16
|
|
189793390U, // VRHADDuv4i32
|
|
190841966U, // VRHADDuv8i16
|
|
191890542U, // VRHADDuv8i8
|
|
188744821U, // VRSHLsv16i8
|
|
212862069U, // VRSHLsv1i64
|
|
186647669U, // VRSHLsv2i32
|
|
212862069U, // VRSHLsv2i64
|
|
187696245U, // VRSHLsv4i16
|
|
186647669U, // VRSHLsv4i32
|
|
187696245U, // VRSHLsv8i16
|
|
188744821U, // VRSHLsv8i8
|
|
191890549U, // VRSHLuv16i8
|
|
213910645U, // VRSHLuv1i64
|
|
189793397U, // VRSHLuv2i32
|
|
213910645U, // VRSHLuv2i64
|
|
190841973U, // VRSHLuv4i16
|
|
189793397U, // VRSHLuv4i32
|
|
190841973U, // VRSHLuv8i16
|
|
191890549U, // VRSHLuv8i8
|
|
192939131U, // VRSHRNv2i32
|
|
193987707U, // VRSHRNv4i16
|
|
195036283U, // VRSHRNv8i8
|
|
188744834U, // VRSHRsv16i8
|
|
212862082U, // VRSHRsv1i64
|
|
186647682U, // VRSHRsv2i32
|
|
212862082U, // VRSHRsv2i64
|
|
187696258U, // VRSHRsv4i16
|
|
186647682U, // VRSHRsv4i32
|
|
187696258U, // VRSHRsv8i16
|
|
188744834U, // VRSHRsv8i8
|
|
191890562U, // VRSHRuv16i8
|
|
213910658U, // VRSHRuv1i64
|
|
189793410U, // VRSHRuv2i32
|
|
213910658U, // VRSHRuv2i64
|
|
190841986U, // VRSHRuv4i16
|
|
189793410U, // VRSHRuv4i32
|
|
190841986U, // VRSHRuv8i16
|
|
191890562U, // VRSHRuv8i8
|
|
1129317512U, // VRSQRTEd
|
|
1107461256U, // VRSQRTEfd
|
|
1107461256U, // VRSQRTEfq
|
|
1129317512U, // VRSQRTEq
|
|
167937168U, // VRSQRTSfd
|
|
167937168U, // VRSQRTSfq
|
|
1262552216U, // VRSRAsv16i8
|
|
1286669464U, // VRSRAsv1i64
|
|
1260455064U, // VRSRAsv2i32
|
|
1286669464U, // VRSRAsv2i64
|
|
1261503640U, // VRSRAsv4i16
|
|
1260455064U, // VRSRAsv4i32
|
|
1261503640U, // VRSRAsv8i16
|
|
1262552216U, // VRSRAsv8i8
|
|
1265697944U, // VRSRAuv16i8
|
|
1287718040U, // VRSRAuv1i64
|
|
1263600792U, // VRSRAuv2i32
|
|
1287718040U, // VRSRAuv2i64
|
|
1264649368U, // VRSRAuv4i16
|
|
1263600792U, // VRSRAuv4i32
|
|
1264649368U, // VRSRAuv8i16
|
|
1265697944U, // VRSRAuv8i8
|
|
192939166U, // VRSUBHNv2i32
|
|
193987742U, // VRSUBHNv4i16
|
|
195036318U, // VRSUBHNv8i8
|
|
1278312608U, // VSETLNi16
|
|
1279361184U, // VSETLNi32
|
|
1270972576U, // VSETLNi8
|
|
195036326U, // VSHLLi16
|
|
193987750U, // VSHLLi32
|
|
196084902U, // VSHLLi8
|
|
186647718U, // VSHLLsv2i64
|
|
187696294U, // VSHLLsv4i32
|
|
188744870U, // VSHLLsv8i16
|
|
189793446U, // VSHLLuv2i64
|
|
190842022U, // VSHLLuv4i32
|
|
191890598U, // VSHLLuv8i16
|
|
196084908U, // VSHLiv16i8
|
|
192939180U, // VSHLiv1i64
|
|
193987756U, // VSHLiv2i32
|
|
192939180U, // VSHLiv2i64
|
|
195036332U, // VSHLiv4i16
|
|
193987756U, // VSHLiv4i32
|
|
195036332U, // VSHLiv8i16
|
|
196084908U, // VSHLiv8i8
|
|
188744876U, // VSHLsv16i8
|
|
212862124U, // VSHLsv1i64
|
|
186647724U, // VSHLsv2i32
|
|
212862124U, // VSHLsv2i64
|
|
187696300U, // VSHLsv4i16
|
|
186647724U, // VSHLsv4i32
|
|
187696300U, // VSHLsv8i16
|
|
188744876U, // VSHLsv8i8
|
|
191890604U, // VSHLuv16i8
|
|
213910700U, // VSHLuv1i64
|
|
189793452U, // VSHLuv2i32
|
|
213910700U, // VSHLuv2i64
|
|
190842028U, // VSHLuv4i16
|
|
189793452U, // VSHLuv4i32
|
|
190842028U, // VSHLuv8i16
|
|
191890604U, // VSHLuv8i8
|
|
192939185U, // VSHRNv2i32
|
|
193987761U, // VSHRNv4i16
|
|
195036337U, // VSHRNv8i8
|
|
188744887U, // VSHRsv16i8
|
|
212862135U, // VSHRsv1i64
|
|
186647735U, // VSHRsv2i32
|
|
212862135U, // VSHRsv2i64
|
|
187696311U, // VSHRsv4i16
|
|
186647735U, // VSHRsv4i32
|
|
187696311U, // VSHRsv8i16
|
|
188744887U, // VSHRsv8i8
|
|
191890615U, // VSHRuv16i8
|
|
213910711U, // VSHRuv1i64
|
|
189793463U, // VSHRuv2i32
|
|
213910711U, // VSHRuv2i64
|
|
190842039U, // VSHRuv4i16
|
|
189793463U, // VSHRuv4i32
|
|
190842039U, // VSHRuv8i16
|
|
191890615U, // VSHRuv8i8
|
|
1154482936U, // VSITOD
|
|
1142227704U, // VSITOS
|
|
1270973628U, // VSLIv16i8
|
|
1284605116U, // VSLIv1i64
|
|
1279362236U, // VSLIv2i32
|
|
1284605116U, // VSLIv2i64
|
|
1278313660U, // VSLIv4i16
|
|
1279362236U, // VSLIv4i32
|
|
1278313660U, // VSLIv8i16
|
|
1270973628U, // VSLIv8i8
|
|
1106412737U, // VSQRTD
|
|
1107461313U, // VSQRTS
|
|
1262552263U, // VSRAsv16i8
|
|
1286669511U, // VSRAsv1i64
|
|
1260455111U, // VSRAsv2i32
|
|
1286669511U, // VSRAsv2i64
|
|
1261503687U, // VSRAsv4i16
|
|
1260455111U, // VSRAsv4i32
|
|
1261503687U, // VSRAsv8i16
|
|
1262552263U, // VSRAsv8i8
|
|
1265697991U, // VSRAuv16i8
|
|
1287718087U, // VSRAuv1i64
|
|
1263600839U, // VSRAuv2i32
|
|
1287718087U, // VSRAuv2i64
|
|
1264649415U, // VSRAuv4i16
|
|
1263600839U, // VSRAuv4i32
|
|
1264649415U, // VSRAuv8i16
|
|
1265697991U, // VSRAuv8i8
|
|
1270973644U, // VSRIv16i8
|
|
1284605132U, // VSRIv1i64
|
|
1279362252U, // VSRIv2i32
|
|
1284605132U, // VSRIv2i64
|
|
1278313676U, // VSRIv4i16
|
|
1279362252U, // VSRIv4i32
|
|
1278313676U, // VSRIv8i16
|
|
1270973644U, // VSRIv8i8
|
|
341345489U, // VST1d16
|
|
342394065U, // VST1d32
|
|
343442641U, // VST1d64
|
|
344491217U, // VST1d8
|
|
342394065U, // VST1df
|
|
339281105U, // VST1q16
|
|
340329681U, // VST1q32
|
|
345572561U, // VST1q64
|
|
331941073U, // VST1q8
|
|
340329681U, // VST1qf
|
|
2757264598U, // VST2LNd16
|
|
2758313174U, // VST2LNd32
|
|
2760410326U, // VST2LNd8
|
|
2757264598U, // VST2LNq16a
|
|
2757264598U, // VST2LNq16b
|
|
2758313174U, // VST2LNq32a
|
|
2758313174U, // VST2LNq32b
|
|
2354611414U, // VST2d16
|
|
2355659990U, // VST2d32
|
|
2356708561U, // VST2d64
|
|
2357757142U, // VST2d8
|
|
2488829142U, // VST2q16
|
|
2489877718U, // VST2q32
|
|
2491974870U, // VST2q8
|
|
2488829147U, // VST3LNd16
|
|
2489877723U, // VST3LNd32
|
|
2491974875U, // VST3LNd8
|
|
2488829147U, // VST3LNq16a
|
|
2488829147U, // VST3LNq16b
|
|
2489877723U, // VST3LNq32a
|
|
2489877723U, // VST3LNq32b
|
|
2757264603U, // VST3d16
|
|
2758313179U, // VST3d32
|
|
2759361745U, // VST3d64
|
|
2760410331U, // VST3d8
|
|
2488894683U, // VST3q16a
|
|
2488894683U, // VST3q16b
|
|
2489943259U, // VST3q32a
|
|
2489943259U, // VST3q32b
|
|
2492040411U, // VST3q8a
|
|
2492040411U, // VST3q8b
|
|
2220393696U, // VST4LNd16
|
|
2221442272U, // VST4LNd32
|
|
2223539424U, // VST4LNd8
|
|
2220393696U, // VST4LNq16a
|
|
2220393696U, // VST4LNq16b
|
|
2221442272U, // VST4LNq32a
|
|
2221442272U, // VST4LNq32b
|
|
2488829152U, // VST4d16
|
|
2489877728U, // VST4d32
|
|
2490926289U, // VST4d64
|
|
2491974880U, // VST4d8
|
|
2220459232U, // VST4q16a
|
|
2220459232U, // VST4q16b
|
|
2221507808U, // VST4q32a
|
|
2221507808U, // VST4q32b
|
|
2223604960U, // VST4q8a
|
|
2223604960U, // VST4q8b
|
|
2952791269U, // VSTMD
|
|
2952791269U, // VSTMS
|
|
210863338U, // VSTRD
|
|
137757935U, // VSTRQ
|
|
205620458U, // VSTRS
|
|
166888694U, // VSUBD
|
|
192939259U, // VSUBHNv2i32
|
|
193987835U, // VSUBHNv4i16
|
|
195036411U, // VSUBHNv8i8
|
|
186647810U, // VSUBLsv2i64
|
|
187696386U, // VSUBLsv4i32
|
|
188744962U, // VSUBLsv8i16
|
|
189793538U, // VSUBLuv2i64
|
|
190842114U, // VSUBLuv4i32
|
|
191890690U, // VSUBLuv8i16
|
|
167937270U, // VSUBS
|
|
186647816U, // VSUBWsv2i64
|
|
187696392U, // VSUBWsv4i32
|
|
188744968U, // VSUBWsv8i16
|
|
189793544U, // VSUBWuv2i64
|
|
190842120U, // VSUBWuv4i32
|
|
191890696U, // VSUBWuv8i16
|
|
167937270U, // VSUBfd
|
|
167937270U, // VSUBfd_sfp
|
|
167937270U, // VSUBfq
|
|
196084982U, // VSUBv16i8
|
|
192939254U, // VSUBv1i64
|
|
193987830U, // VSUBv2i32
|
|
192939254U, // VSUBv2i64
|
|
195036406U, // VSUBv4i16
|
|
193987830U, // VSUBv4i32
|
|
195036406U, // VSUBv8i16
|
|
196084982U, // VSUBv8i8
|
|
197231886U, // VTBL1
|
|
1270973710U, // VTBL2
|
|
331449614U, // VTBL3
|
|
2344715534U, // VTBL4
|
|
1270973715U, // VTBX1
|
|
331449619U, // VTBX2
|
|
2344715539U, // VTBX3
|
|
2747368723U, // VTBX4
|
|
1155531512U, // VTOSIZD
|
|
1140130552U, // VTOSIZS
|
|
1156580088U, // VTOUIZD
|
|
1141179128U, // VTOUIZS
|
|
1278313752U, // VTRNd16
|
|
1279362328U, // VTRNd32
|
|
1270973720U, // VTRNd8
|
|
1278313752U, // VTRNq16
|
|
1279362328U, // VTRNq32
|
|
1270973720U, // VTRNq8
|
|
196085021U, // VTSTv16i8
|
|
193987869U, // VTSTv2i32
|
|
195036445U, // VTSTv4i16
|
|
193987869U, // VTSTv4i32
|
|
195036445U, // VTSTv8i16
|
|
196085021U, // VTSTv8i8
|
|
1157628664U, // VUITOD
|
|
1143276280U, // VUITOS
|
|
1278313762U, // VUZPd16
|
|
1279362338U, // VUZPd32
|
|
1270973730U, // VUZPd8
|
|
1278313762U, // VUZPq16
|
|
1279362338U, // VUZPq32
|
|
1270973730U, // VUZPq8
|
|
1278313767U, // VZIPd16
|
|
1279362343U, // VZIPd32
|
|
1270973735U, // VZIPd8
|
|
1278313767U, // VZIPq16
|
|
1279362343U, // VZIPq32
|
|
1270973735U, // VZIPq8
|
|
7U, // t2ADCSri
|
|
1324U, // t2ADCSrr
|
|
1324U, // t2ADCSrs
|
|
3090251789U, // t2ADCri
|
|
3172106253U, // t2ADCrr
|
|
3306323981U, // t2ADCrs
|
|
219316241U, // t2ADDSri
|
|
219316241U, // t2ADDSrr
|
|
1293058065U, // t2ADDSrs
|
|
3172106262U, // t2ADDrSPi
|
|
137463092U, // t2ADDrSPi12
|
|
3306323990U, // t2ADDrSPs
|
|
3172106262U, // t2ADDri
|
|
3090253108U, // t2ADDri12
|
|
3172106262U, // t2ADDrr
|
|
3306323990U, // t2ADDrs
|
|
3090251840U, // t2ANDri
|
|
3172106304U, // t2ANDrr
|
|
3306324032U, // t2ANDrs
|
|
3172107577U, // t2ASRri
|
|
3172107577U, // t2ASRrr
|
|
4195645U, // t2B
|
|
137461832U, // t2BFC
|
|
3090251852U, // t2BICri
|
|
3172106316U, // t2BICrr
|
|
3306324044U, // t2BICrs
|
|
85983346U, // t2BR_JT
|
|
756351118U, // t2Bcc
|
|
1076986000U, // t2CLZ
|
|
1158840468U, // t2CMNri
|
|
1158840468U, // t2CMNrr
|
|
219316372U, // t2CMNrs
|
|
1158840468U, // t2CMNzri
|
|
1158840468U, // t2CMNzrr
|
|
219316372U, // t2CMNzrs
|
|
1158840472U, // t2CMPri
|
|
1158840472U, // t2CMPrr
|
|
219316376U, // t2CMPrs
|
|
1158840472U, // t2CMPzri
|
|
1158840472U, // t2CMPzrr
|
|
219316376U, // t2CMPzrs
|
|
3090251932U, // t2EORri
|
|
3172106396U, // t2EORrr
|
|
3306324124U, // t2EORrs
|
|
3355444546U, // t2IT
|
|
1476395191U, // t2Int_MemBarrierV7
|
|
1476395195U, // t2Int_SyncBarrierV7
|
|
87033157U, // t2Int_eh_sjlj_setjmp
|
|
1698693321U, // t2LDM
|
|
1698693321U, // t2LDM_RET
|
|
1211203793U, // t2LDRB_POST
|
|
1211203793U, // t2LDRB_PRE
|
|
219316433U, // t2LDRBi12
|
|
137461969U, // t2LDRBi8
|
|
1158840529U, // t2LDRBpci
|
|
1293058257U, // t2LDRBs
|
|
1211203798U, // t2LDRDi8
|
|
137461974U, // t2LDRDpci
|
|
1076986075U, // t2LDREX
|
|
1076986081U, // t2LDREXB
|
|
137461992U, // t2LDREXD
|
|
1076986095U, // t2LDREXH
|
|
1211203830U, // t2LDRH_POST
|
|
1211203830U, // t2LDRH_PRE
|
|
219316470U, // t2LDRHi12
|
|
137462006U, // t2LDRHi8
|
|
1158840566U, // t2LDRHpci
|
|
1293058294U, // t2LDRHs
|
|
1211203835U, // t2LDRSB_POST
|
|
1211203835U, // t2LDRSB_PRE
|
|
219316475U, // t2LDRSBi12
|
|
137462011U, // t2LDRSBi8
|
|
1158840571U, // t2LDRSBpci
|
|
1293058299U, // t2LDRSBs
|
|
1211203841U, // t2LDRSH_POST
|
|
1211203841U, // t2LDRSH_PRE
|
|
219316481U, // t2LDRSHi12
|
|
137462017U, // t2LDRSHi8
|
|
1158840577U, // t2LDRSHpci
|
|
1293058305U, // t2LDRSHs
|
|
1211203789U, // t2LDR_POST
|
|
1211203789U, // t2LDR_PRE
|
|
219316429U, // t2LDRi12
|
|
137461965U, // t2LDRi8
|
|
1158840525U, // t2LDRpci
|
|
1361U, // t2LDRpci_pic
|
|
1293058253U, // t2LDRs
|
|
1159333210U, // t2LEApcrel
|
|
219809114U, // t2LEApcrelJT
|
|
3172107614U, // t2LSLri
|
|
3172107614U, // t2LSLrr
|
|
3172107618U, // t2LSRri
|
|
3172107618U, // t2LSRrr
|
|
1211203853U, // t2MLA
|
|
1211203857U, // t2MLS
|
|
1293059385U, // t2MOVCCasr
|
|
219316501U, // t2MOVCCi
|
|
1293059422U, // t2MOVCClsl
|
|
1293059426U, // t2MOVCClsr
|
|
219316501U, // t2MOVCCr
|
|
1293059430U, // t2MOVCCror
|
|
137462041U, // t2MOVTi16
|
|
3579478293U, // t2MOVi
|
|
1076986142U, // t2MOVi16
|
|
1076986142U, // t2MOVi32imm
|
|
3579478293U, // t2MOVr
|
|
3579512170U, // t2MOVrx
|
|
1390U, // t2MOVsra_flag
|
|
1398U, // t2MOVsrl_flag
|
|
137462056U, // t2MUL
|
|
3579511084U, // t2MVNi
|
|
1158840620U, // t2MVNr
|
|
219316524U, // t2MVNs
|
|
3090253182U, // t2ORNri
|
|
3090253182U, // t2ORNrr
|
|
3224470910U, // t2ORNrs
|
|
3090252080U, // t2ORRri
|
|
3172106544U, // t2ORRrr
|
|
3306324272U, // t2ORRrs
|
|
1211203894U, // t2PKHBT
|
|
1211203900U, // t2PKHTB
|
|
1158840642U, // t2REV
|
|
1158840646U, // t2REV16
|
|
1158840652U, // t2REVSH
|
|
3172107622U, // t2RORri
|
|
3172107622U, // t2RORrr
|
|
3623878999U, // t2RSBSri
|
|
3492905303U, // t2RSBSrs
|
|
219316567U, // t2RSBri
|
|
1211203927U, // t2RSBrs
|
|
357U, // t2SBCSri
|
|
1410U, // t2SBCSrr
|
|
1410U, // t2SBCSrs
|
|
3090252139U, // t2SBCri
|
|
3172106603U, // t2SBCrr
|
|
3306324331U, // t2SBCrs
|
|
1211203951U, // t2SBFX
|
|
1211203956U, // t2SMLABB
|
|
1211203963U, // t2SMLABT
|
|
1211203970U, // t2SMLAL
|
|
1211203976U, // t2SMLATB
|
|
1211203983U, // t2SMLATT
|
|
1211203990U, // t2SMLAWB
|
|
1211203997U, // t2SMLAWT
|
|
1211204004U, // t2SMMLA
|
|
1211204010U, // t2SMMLS
|
|
137462192U, // t2SMMUL
|
|
137462198U, // t2SMULBB
|
|
137462205U, // t2SMULBT
|
|
1211204036U, // t2SMULL
|
|
137462218U, // t2SMULTB
|
|
137462225U, // t2SMULTT
|
|
137462232U, // t2SMULWB
|
|
137462239U, // t2SMULWT
|
|
1698693606U, // t2STM
|
|
1211105774U, // t2STRB_POST
|
|
1211105774U, // t2STRB_PRE
|
|
219316718U, // t2STRBi12
|
|
137462254U, // t2STRBi8
|
|
1293058542U, // t2STRBs
|
|
1211204083U, // t2STRDi8
|
|
137462264U, // t2STREX
|
|
137462270U, // t2STREXB
|
|
1211204101U, // t2STREXD
|
|
137462284U, // t2STREXH
|
|
1211105811U, // t2STRH_POST
|
|
1211105811U, // t2STRH_PRE
|
|
219316755U, // t2STRHi12
|
|
137462291U, // t2STRHi8
|
|
1293058579U, // t2STRHs
|
|
1211105770U, // t2STR_POST
|
|
1211105770U, // t2STR_PRE
|
|
219316714U, // t2STRi12
|
|
137462250U, // t2STRi8
|
|
1293058538U, // t2STRs
|
|
219316760U, // t2SUBSri
|
|
219316760U, // t2SUBSrr
|
|
1293058584U, // t2SUBSrs
|
|
3172106781U, // t2SUBrSPi
|
|
137463178U, // t2SUBrSPi12
|
|
1423U, // t2SUBrSPi12_
|
|
1431U, // t2SUBrSPi_
|
|
3224470045U, // t2SUBrSPs
|
|
1440U, // t2SUBrSPs_
|
|
3172106781U, // t2SUBri
|
|
3090253194U, // t2SUBri12
|
|
3172106781U, // t2SUBrr
|
|
3306324509U, // t2SUBrs
|
|
137462305U, // t2SXTABrr
|
|
1211204129U, // t2SXTABrr_rot
|
|
137462311U, // t2SXTAHrr
|
|
1211204135U, // t2SXTAHrr_rot
|
|
1158840877U, // t2SXTBr
|
|
219316781U, // t2SXTBr_rot
|
|
1158840882U, // t2SXTHr
|
|
219316786U, // t2SXTHr_rot
|
|
3758097831U, // t2TBB
|
|
3758097836U, // t2TBH
|
|
1158840887U, // t2TEQri
|
|
1158840887U, // t2TEQrr
|
|
219316791U, // t2TEQrs
|
|
1476395579U, // t2TPsoft
|
|
1158840910U, // t2TSTri
|
|
1158840910U, // t2TSTrr
|
|
219316814U, // t2TSTrs
|
|
1211204178U, // t2UBFX
|
|
1211204183U, // t2UMAAL
|
|
1211204189U, // t2UMLAL
|
|
1211204195U, // t2UMULL
|
|
137462377U, // t2UXTABrr
|
|
1211204201U, // t2UXTABrr_rot
|
|
137462383U, // t2UXTAHrr
|
|
1211204207U, // t2UXTAHrr_rot
|
|
1158840949U, // t2UXTB16r
|
|
219316853U, // t2UXTB16r_rot
|
|
1158840956U, // t2UXTBr
|
|
219316860U, // t2UXTBr_rot
|
|
1158840961U, // t2UXTHr
|
|
219316865U, // t2UXTHr_rot
|
|
3983245325U, // tADC
|
|
137461782U, // tADDhirr
|
|
3982557206U, // tADDi3
|
|
3983245334U, // tADDi8
|
|
91227569U, // tADDrPCi
|
|
66993U, // tADDrSP
|
|
1457U, // tADDrSPi
|
|
3982557206U, // tADDrr
|
|
787889U, // tADDspi
|
|
66993U, // tADDspr
|
|
66998U, // tADDspr_
|
|
4195773U, // tADJCALLSTACKDOWN
|
|
4195794U, // tADJCALLSTACKUP
|
|
3983245376U, // tAND
|
|
67045U, // tANDsp
|
|
3982558521U, // tASRri
|
|
3983246649U, // tASRrr
|
|
4194373U, // tB
|
|
3983245388U, // tBIC
|
|
536870992U, // tBL
|
|
536870996U, // tBLXi
|
|
536870996U, // tBLXi_r9
|
|
4194388U, // tBLXr
|
|
4194388U, // tBLXr_r9
|
|
536870992U, // tBLr9
|
|
4194418U, // tBRIND
|
|
92274802U, // tBR_JTr
|
|
4194427U, // tBX
|
|
1476396524U, // tBX_RET
|
|
4194396U, // tBX_RET_vararg
|
|
4194427U, // tBXr9
|
|
674332814U, // tBcc
|
|
93323344U, // tBfar
|
|
1522U, // tCBNZ
|
|
1528U, // tCBZ
|
|
1076986004U, // tCMN
|
|
1076986004U, // tCMNz
|
|
1076986008U, // tCMPhir
|
|
1076986008U, // tCMPi8
|
|
1076986008U, // tCMPr
|
|
1076986008U, // tCMPzhir
|
|
1076986008U, // tCMPzi8
|
|
1076986008U, // tCMPzr
|
|
3983245468U, // tEOR
|
|
94373373U, // tInt_eh_sjlj_setjmp
|
|
1613955273U, // tLDM
|
|
1211203789U, // tLDR
|
|
1211203793U, // tLDRB
|
|
1211203830U, // tLDRH
|
|
137462011U, // tLDRSB
|
|
137462017U, // tLDRSH
|
|
1076986061U, // tLDRcp
|
|
1169162445U, // tLDRpci
|
|
1586U, // tLDRpci_pic
|
|
137461965U, // tLDRspi
|
|
1076987226U, // tLEApcrel
|
|
137463130U, // tLEApcrelJT
|
|
3982558558U, // tLSLri
|
|
3983246686U, // tLSLrr
|
|
3982558562U, // tLSRri
|
|
3983246690U, // tLSRrr
|
|
137462037U, // tMOVCCi
|
|
137462037U, // tMOVCCr
|
|
138413627U, // tMOVCCr_pseudo
|
|
1606U, // tMOVSr
|
|
1612U, // tMOVgpr2gpr
|
|
1612U, // tMOVgpr2tgpr
|
|
3989111061U, // tMOVi8
|
|
1612U, // tMOVr
|
|
1612U, // tMOVtgpr2gpr
|
|
3983245608U, // tMUL
|
|
3989111084U, // tMVN
|
|
3983245616U, // tORR
|
|
1976566068U, // tPICADD
|
|
943490641U, // tPOP
|
|
943490641U, // tPOP_RET
|
|
943490645U, // tPUSH
|
|
1076986178U, // tREV
|
|
1076986182U, // tREV16
|
|
1076986188U, // tREVSH
|
|
3983246694U, // tROR
|
|
3989078359U, // tRSB
|
|
137461965U, // tRestore
|
|
3983245675U, // tSBC
|
|
1613955558U, // tSTM
|
|
1211204074U, // tSTR
|
|
1211204078U, // tSTRB
|
|
1211204115U, // tSTRH
|
|
137462250U, // tSTRspi
|
|
3982557725U, // tSUBi3
|
|
3983245853U, // tSUBi8
|
|
3982557725U, // tSUBrr
|
|
788058U, // tSUBspi
|
|
787872U, // tSUBspi_
|
|
1076986413U, // tSXTB
|
|
1076986418U, // tSXTH
|
|
137462250U, // tSpill
|
|
1476395579U, // tTPsoft
|
|
1076986446U, // tTST
|
|
1076986492U, // tUXTB
|
|
1076986497U, // tUXTH
|
|
0U
|
|
};
|
|
|
|
const char *AsmStrs =
|
|
"adcs\t\000adcs\t\000adc\000adds\000add\000@ ADJCALLSTACKDOWN \000@ ADJC"
|
|
"ALLSTACKUP \000and\000\000b\t\000bfc\000bic\000bl\t\000blx\t\000bl\000b"
|
|
"x\t\000add\tpc, \000ldr\tpc, \000mov\tpc, \000mov\tlr, pc\n\tbx\t\000bx"
|
|
"\000b\000clz\000cmn\000cmp\000eor\000vmov\000vmrs\000mcr\tp15, 0, \000d"
|
|
"mb\000dsb\000str\tsp, [\000ldm\000ldr\000ldrb\000ldrd\000ldrex\000ldrex"
|
|
"b\000ldrexd\000ldrexh\000ldrh\000ldrsb\000ldrsh\000.set \000mla\000mls\000"
|
|
"mov\000movt\000movw\000movs\000mul\000mvn\000orr\000\n\000pkhbt\000pkht"
|
|
"b\000rev\000rev16\000revsh\000rsbs\000rsb\000rscs\t\000rsc\000sbcs\t\000"
|
|
"sbc\000sbfx\000smlabb\000smlabt\000smlal\000smlatb\000smlatt\000smlawb\000"
|
|
"smlawt\000smmla\000smmls\000smmul\000smulbb\000smulbt\000smull\000smult"
|
|
"b\000smultt\000smulwb\000smulwt\000stm\000str\000strb\000strd\000strex\000"
|
|
"strexb\000strexd\000strexh\000strh\000subs\000sub\000sxtab\000sxtah\000"
|
|
"sxtb\000sxth\000teq\000bl\t__aeabi_read_tp\000tst\000ubfx\000umaal\000u"
|
|
"mlal\000umull\000uxtab\000uxtah\000uxtb16\000uxtb\000uxth\000vabal\000v"
|
|
"aba\000vabdl\000vabd\000vabs\000vacge\000vacgt\000vadd\000vaddhn\000vad"
|
|
"dl\000vaddw\000vand\000vbic\000vbsl\000vceq\000vcge\000vcgt\000vcls\000"
|
|
"vclz\000vcmpe\000vcnt\000vcvt\000vdiv\000vdup\000veor\000vext\000vhadd\000"
|
|
"vhsub\000vld1\000vld2\000vld3\000vld4\000vldm\000vldr\000vldmia\000vmax"
|
|
"\000vmin\000vmla\000vmlal\000vmls\000vmlsl\000vmovl\000vmovn\000vmul\000"
|
|
"vmull\000vmvn\000vneg\000vnmla\000vnmls\000vnmul\000vorn\000vorr\000vpa"
|
|
"dal\000vpaddl\000vpadd\000vpmax\000vpmin\000vqabs\000vqadd\000vqdmlal\000"
|
|
"vqdmlsl\000vqdmulh\000vqdmull\000vqmovun\000vqmovn\000vqneg\000vqrdmulh"
|
|
"\000vqrshl\000vqrshrn\000vqrshrun\000vqshl\000vqshlu\000vqshrn\000vqshr"
|
|
"un\000vqsub\000vraddhn\000vrecpe\000vrecps\000vrev16\000vrev32\000vrev6"
|
|
"4\000vrhadd\000vrshl\000vrshrn\000vrshr\000vrsqrte\000vrsqrts\000vrsra\000"
|
|
"vrsubhn\000vshll\000vshl\000vshrn\000vshr\000vsli\000vsqrt\000vsra\000v"
|
|
"sri\000vst1\000vst2\000vst3\000vst4\000vstm\000vstr\000vstmia\000vsub\000"
|
|
"vsubhn\000vsubl\000vsubw\000vtbl\000vtbx\000vtrn\000vtst\000vuzp\000vzi"
|
|
"p\000adcs.w\t\000addw\000asr\000b.w\t\000it\000str.w\tsp, [\000@ ldr.w\t"
|
|
"\000adr\000lsl\000lsr\000ror\000rrx\000asrs.w\t\000lsrs.w\t\000orn\000s"
|
|
"bcs.w\t\000subw\000@ subw\t\000@ sub.w\t\000@ sub\t\000tbb\t\000tbh\t\000"
|
|
"add\t\000@ add\t\000@ tADJCALLSTACKDOWN \000@ tADJCALLSTACKUP \000@ and"
|
|
"\t\000bx\tlr\000cbnz\t\000cbz\t\000mov\tr12, r1\t@ begin eh.setjmp\n\tm"
|
|
"ov\tr1, sp\n\tstr\tr1, [\000@ ldr.n\t\000@ tMOVCCr \000movs\t\000mov\t\000"
|
|
"pop\000push\000sub\t\000";
|
|
|
|
|
|
#ifndef NO_ASM_WRITER_BOILERPLATE
|
|
if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
|
|
printInlineAsm(MI);
|
|
return;
|
|
} else if (MI->isLabel()) {
|
|
printLabel(MI);
|
|
return;
|
|
} else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
|
|
printImplicitDef(MI);
|
|
return;
|
|
} else if (MI->getOpcode() == TargetInstrInfo::KILL) {
|
|
printKill(MI);
|
|
return;
|
|
}
|
|
|
|
|
|
#endif
|
|
O << "\t";
|
|
|
|
// Emit the opcode for the instruction.
|
|
unsigned Bits = OpInfo[MI->getOpcode()];
|
|
assert(Bits != 0 && "Cannot print this instruction.");
|
|
O << AsmStrs+(Bits & 2047)-1;
|
|
|
|
|
|
// Fragment 0 encoded into 5 bits for 30 unique commands.
|
|
switch ((Bits >> 27) & 31) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADCSSri, ADCSSrr, ADCSSrs, ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, B...
|
|
printOperand(MI, 0);
|
|
break;
|
|
case 1:
|
|
// ADCri, ADCrr, ADDSri, ADDSrr, ADDri, ADDrr, ANDri, ANDrr, BFC, BICri, ...
|
|
printPredicateOperand(MI, 3);
|
|
break;
|
|
case 2:
|
|
// ADCrs, ADDSrs, ADDrs, ANDrs, BICrs, EORrs, LDRB_POST, LDRB_PRE, LDRD, ...
|
|
printPredicateOperand(MI, 5);
|
|
break;
|
|
case 3:
|
|
// ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, ATOMIC_CMP_SWAP_I8, ATOMIC_L...
|
|
PrintSpecial(MI, "comment");
|
|
break;
|
|
case 4:
|
|
// BL, BLr9, tBL, tBLXi, tBLXi_r9, tBLr9
|
|
printOperand(MI, 0, "call");
|
|
return;
|
|
break;
|
|
case 5:
|
|
// BL_pred, BLr9_pred, Bcc, VCMPEZD, VCMPEZS, t2Bcc, tBcc
|
|
printPredicateOperand(MI, 1);
|
|
break;
|
|
case 6:
|
|
// BR_JTm
|
|
printAddrMode2Operand(MI, 0);
|
|
O << " \n";
|
|
printJTBlockOperand(MI, 3);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// BX_RET, FMSTAT, tPOP, tPOP_RET, tPUSH
|
|
printPredicateOperand(MI, 0);
|
|
break;
|
|
case 8:
|
|
// CLZ, CMNri, CMNrr, CMNzri, CMNzrr, CMPri, CMPrr, CMPzri, CMPzrr, FCONS...
|
|
printPredicateOperand(MI, 2);
|
|
break;
|
|
case 9:
|
|
// CMNrs, CMNzrs, CMPrs, CMPzrs, LDR, LDRB, LDRH, LDRSB, LDRSH, LDRcp, ML...
|
|
printPredicateOperand(MI, 4);
|
|
break;
|
|
case 10:
|
|
// CONSTPOOL_ENTRY
|
|
printCPInstOperand(MI, 0, "label");
|
|
O << ' ';
|
|
printCPInstOperand(MI, 1, "cpentry");
|
|
return;
|
|
break;
|
|
case 11:
|
|
// Int_MemBarrierV7, Int_SyncBarrierV7, TPsoft, t2Int_MemBarrierV7, t2Int...
|
|
return;
|
|
break;
|
|
case 12:
|
|
// LDM, LDM_RET, STM, t2LDM, t2LDM_RET, t2STM, tLDM, tSTM
|
|
printAddrMode4Operand(MI, 0, "submode");
|
|
printPredicateOperand(MI, 2);
|
|
break;
|
|
case 13:
|
|
// LEApcrel, LEApcrelJT
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELV";
|
|
PrintSpecial(MI, "uid");
|
|
O << ", (";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 14:
|
|
// PICADD, tPICADD
|
|
printPCLabel(MI, 2);
|
|
break;
|
|
case 15:
|
|
// PICLDR, PICLDRB, PICLDRH, PICLDRSB, PICLDRSH, PICSTR, PICSTRB, PICSTRH
|
|
printAddrModePCOperand(MI, 1, "label");
|
|
break;
|
|
case 16:
|
|
// VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16a, VLD2LNq16b, VLD2LNq32a, VL...
|
|
printPredicateOperand(MI, 9);
|
|
break;
|
|
case 17:
|
|
// VLD2d16, VLD2d32, VLD2d64, VLD2d8, VST2d16, VST2d32, VST2d64, VST2d8, ...
|
|
printPredicateOperand(MI, 6);
|
|
break;
|
|
case 18:
|
|
// VLD2q16, VLD2q32, VLD2q8, VLD3q16a, VLD3q16b, VLD3q32a, VLD3q32b, VLD3...
|
|
printPredicateOperand(MI, 8);
|
|
break;
|
|
case 19:
|
|
// VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16a, VLD3LNq16b, VLD3LNq32a, VL...
|
|
printPredicateOperand(MI, 11);
|
|
break;
|
|
case 20:
|
|
// VLD3d16, VLD3d32, VLD3d64, VLD3d8, VST2LNd16, VST2LNd32, VST2LNd8, VST...
|
|
printPredicateOperand(MI, 7);
|
|
break;
|
|
case 21:
|
|
// VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16a, VLD4LNq16b, VLD4LNq32a, VL...
|
|
printPredicateOperand(MI, 13);
|
|
break;
|
|
case 22:
|
|
// VLDMD, VLDMS, VSTMD, VSTMS
|
|
printAddrMode5Operand(MI, 0, "submode");
|
|
printPredicateOperand(MI, 2);
|
|
O << "\t";
|
|
printAddrMode5Operand(MI, 0, "base");
|
|
O << ", ";
|
|
printRegisterList(MI, 4);
|
|
return;
|
|
break;
|
|
case 23:
|
|
// t2ADCri, t2ADCrr, t2ADDrSPi, t2ADDri, t2ADDri12, t2ADDrr, t2ANDri, t2A...
|
|
printSBitModifierOperand(MI, 5);
|
|
printPredicateOperand(MI, 3);
|
|
break;
|
|
case 24:
|
|
// t2ADCrs, t2ADDrSPs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORR...
|
|
printSBitModifierOperand(MI, 6);
|
|
printPredicateOperand(MI, 4);
|
|
break;
|
|
case 25:
|
|
// t2IT
|
|
printThumbITMask(MI, 1);
|
|
O << "\t";
|
|
printPredicateOperand(MI, 0);
|
|
return;
|
|
break;
|
|
case 26:
|
|
// t2MOVi, t2MOVr, t2MOVrx, t2MVNi, t2RSBSrs
|
|
printSBitModifierOperand(MI, 4);
|
|
break;
|
|
case 27:
|
|
// t2RSBSri
|
|
printSBitModifierOperand(MI, 3);
|
|
O << ".w\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 28:
|
|
// t2TBB, t2TBH
|
|
printTBAddrMode(MI, 0);
|
|
O << "\n";
|
|
printJT2BlockOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 29:
|
|
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
|
|
printSBitModifierOperand(MI, 1);
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 1 encoded into 7 bits for 94 unique commands.
|
|
switch ((Bits >> 20) & 127) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, RSCSri, RSCSrs, SBCSSri, SBCSSrr,...
|
|
O << ", ";
|
|
break;
|
|
case 1:
|
|
// ADCri, ADCrr, ADDri, ADDrr, ANDri, ANDrr, BICri, BICrr, EORri, EORrr, ...
|
|
printSBitModifierOperand(MI, 5);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
break;
|
|
case 2:
|
|
// ADCrs, ADDrs, ANDrs, BICrs, EORrs, ORRrs, RSBrs, RSCrs, SBCrs, SUBrs
|
|
printSBitModifierOperand(MI, 7);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printSORegOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 3:
|
|
// ADDSri, ADDSrr, ADDSrs, BFC, BL_pred, BLr9_pred, Bcc, CLZ, CMNri, CMNr...
|
|
O << "\t";
|
|
break;
|
|
case 4:
|
|
// ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, BLXr9, BRIND, BX, BXr9, t2B,...
|
|
return;
|
|
break;
|
|
case 5:
|
|
// ATOMIC_CMP_SWAP_I16
|
|
O << " ATOMIC_CMP_SWAP_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 6:
|
|
// ATOMIC_CMP_SWAP_I32
|
|
O << " ATOMIC_CMP_SWAP_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 7:
|
|
// ATOMIC_CMP_SWAP_I8
|
|
O << " ATOMIC_CMP_SWAP_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 8:
|
|
// ATOMIC_LOAD_ADD_I16
|
|
O << " ATOMIC_LOAD_ADD_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 9:
|
|
// ATOMIC_LOAD_ADD_I32
|
|
O << " ATOMIC_LOAD_ADD_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 10:
|
|
// ATOMIC_LOAD_ADD_I8
|
|
O << " ATOMIC_LOAD_ADD_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 11:
|
|
// ATOMIC_LOAD_AND_I16
|
|
O << " ATOMIC_LOAD_AND_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 12:
|
|
// ATOMIC_LOAD_AND_I32
|
|
O << " ATOMIC_LOAD_AND_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 13:
|
|
// ATOMIC_LOAD_AND_I8
|
|
O << " ATOMIC_LOAD_AND_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 14:
|
|
// ATOMIC_LOAD_NAND_I16
|
|
O << " ATOMIC_LOAD_NAND_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 15:
|
|
// ATOMIC_LOAD_NAND_I32
|
|
O << " ATOMIC_LOAD_NAND_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 16:
|
|
// ATOMIC_LOAD_NAND_I8
|
|
O << " ATOMIC_LOAD_NAND_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 17:
|
|
// ATOMIC_LOAD_OR_I16
|
|
O << " ATOMIC_LOAD_OR_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 18:
|
|
// ATOMIC_LOAD_OR_I32
|
|
O << " ATOMIC_LOAD_OR_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 19:
|
|
// ATOMIC_LOAD_OR_I8
|
|
O << " ATOMIC_LOAD_OR_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 20:
|
|
// ATOMIC_LOAD_SUB_I16
|
|
O << " ATOMIC_LOAD_SUB_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 21:
|
|
// ATOMIC_LOAD_SUB_I32
|
|
O << " ATOMIC_LOAD_SUB_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 22:
|
|
// ATOMIC_LOAD_SUB_I8
|
|
O << " ATOMIC_LOAD_SUB_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 23:
|
|
// ATOMIC_LOAD_XOR_I16
|
|
O << " ATOMIC_LOAD_XOR_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 24:
|
|
// ATOMIC_LOAD_XOR_I32
|
|
O << " ATOMIC_LOAD_XOR_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 25:
|
|
// ATOMIC_LOAD_XOR_I8
|
|
O << " ATOMIC_LOAD_XOR_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 26:
|
|
// ATOMIC_SWAP_I16
|
|
O << " ATOMIC_SWAP_I16 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 27:
|
|
// ATOMIC_SWAP_I32
|
|
O << " ATOMIC_SWAP_I32 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 28:
|
|
// ATOMIC_SWAP_I8
|
|
O << " ATOMIC_SWAP_I8 PSEUDO!";
|
|
return;
|
|
break;
|
|
case 29:
|
|
// BR_JTr
|
|
O << " \n";
|
|
printJTBlockOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 30:
|
|
// BX_RET
|
|
O << "\tlr";
|
|
return;
|
|
break;
|
|
case 31:
|
|
// FCONSTD, VABSD, VADDD, VCMPED, VCMPEZD, VDIVD, VMLAD, VMLSD, VMOVD, VM...
|
|
O << ".f64\t";
|
|
printOperand(MI, 0);
|
|
break;
|
|
case 32:
|
|
// FCONSTS, VABDfd, VABDfq, VABSS, VABSfd, VABSfd_sfp, VABSfq, VACGEd, VA...
|
|
O << ".f32\t";
|
|
printOperand(MI, 0);
|
|
break;
|
|
case 33:
|
|
// FMSTAT
|
|
O << "\tapsr_nzcv, fpscr";
|
|
return;
|
|
break;
|
|
case 34:
|
|
// Int_MemBarrierV6
|
|
O << ", c7, c10, 5";
|
|
return;
|
|
break;
|
|
case 35:
|
|
// Int_SyncBarrierV6
|
|
O << ", c7, c10, 4";
|
|
return;
|
|
break;
|
|
case 36:
|
|
// Int_eh_sjlj_setjmp
|
|
O << ", #+8] @ eh_setjmp begin\n\tadd\tr12, pc, #8\n\tstr\tr12, [";
|
|
printOperand(MI, 0);
|
|
O << ", #+4]\n\tmov\tr0, #0\n\tadd\tpc, pc, #0\n\tmov\tr0, #1 @ eh_setjmp end";
|
|
return;
|
|
break;
|
|
case 37:
|
|
// LEApcrel
|
|
O << "-(";
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELL";
|
|
PrintSpecial(MI, "uid");
|
|
O << "+8))\n";
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELL";
|
|
PrintSpecial(MI, "uid");
|
|
O << ":\n\tadd";
|
|
printPredicateOperand(MI, 2);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", pc, #";
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELV";
|
|
PrintSpecial(MI, "uid");
|
|
return;
|
|
break;
|
|
case 38:
|
|
// LEApcrelJT
|
|
O << '_';
|
|
printNoHashImmediate(MI, 2);
|
|
O << "-(";
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELL";
|
|
PrintSpecial(MI, "uid");
|
|
O << "+8))\n";
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELL";
|
|
PrintSpecial(MI, "uid");
|
|
O << ":\n\tadd";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", pc, #";
|
|
PrintSpecial(MI, "private");
|
|
O << "PCRELV";
|
|
PrintSpecial(MI, "uid");
|
|
return;
|
|
break;
|
|
case 39:
|
|
// MLA, MOVs, MVNs, SMLAL, SMULL, UMLAL, UMULL
|
|
printSBitModifierOperand(MI, 6);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 40:
|
|
// MOVi, MOVr, MOVrx, MVNi, MVNr
|
|
printSBitModifierOperand(MI, 4);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 41:
|
|
// PICADD
|
|
O << ":\n\tadd";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", pc, ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 42:
|
|
// PICLDR
|
|
O << ":\n\tldr";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 43:
|
|
// PICLDRB
|
|
O << ":\n\tldrb";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 44:
|
|
// PICLDRH
|
|
O << ":\n\tldrh";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 45:
|
|
// PICLDRSB
|
|
O << ":\n\tldrsb";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 46:
|
|
// PICLDRSH
|
|
O << ":\n\tldrsh";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 47:
|
|
// PICSTR
|
|
O << ":\n\tstr";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 48:
|
|
// PICSTRB
|
|
O << ":\n\tstrb";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 49:
|
|
// PICSTRH
|
|
O << ":\n\tstrh";
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printAddrModePCOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 50:
|
|
// VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i...
|
|
O << ".s32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 51:
|
|
// VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i...
|
|
O << ".s16\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 52:
|
|
// VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8...
|
|
O << ".s8\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 53:
|
|
// VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i...
|
|
O << ".u32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 54:
|
|
// VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i...
|
|
O << ".u16\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 55:
|
|
// VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8...
|
|
O << ".u8\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 56:
|
|
// VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V...
|
|
O << ".i64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 57:
|
|
// VADDHNv4i16, VADDv2i32, VADDv4i32, VCEQv2i32, VCEQv4i32, VCLZv2i32, VC...
|
|
O << ".i32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 58:
|
|
// VADDHNv8i8, VADDv4i16, VADDv8i16, VCEQv4i16, VCEQv8i16, VCLZv4i16, VCL...
|
|
O << ".i16\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 59:
|
|
// VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCLZv16i8, VCLZv8i8, VMLAv16...
|
|
O << ".i8\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 60:
|
|
// VCNTd, VCNTq, VDUP8d, VDUP8q, VDUPLN8d, VDUPLN8q, VEXTd8, VEXTq8, VLD1...
|
|
O << ".8\t";
|
|
break;
|
|
case 61:
|
|
// VCVTDS
|
|
O << ".f64.f32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 62:
|
|
// VCVTSD
|
|
O << ".f32.f64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 63:
|
|
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIZS
|
|
O << ".s32.f32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 64:
|
|
// VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIZS
|
|
O << ".u32.f32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 65:
|
|
// VCVTs2fd, VCVTs2fd_sfp, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS
|
|
O << ".f32.s32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 66:
|
|
// VCVTu2fd, VCVTu2fd_sfp, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS
|
|
O << ".f32.u32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 67:
|
|
// VDUP16d, VDUP16q, VDUPLN16d, VDUPLN16q, VEXTd16, VEXTq16, VLD1q16, VRE...
|
|
O << ".16\t";
|
|
break;
|
|
case 68:
|
|
// VDUP32d, VDUP32q, VDUPLN32d, VDUPLN32q, VDUPLNfd, VDUPLNfq, VDUPfd, VD...
|
|
O << ".32\t";
|
|
break;
|
|
case 69:
|
|
// VLD1d16, VLD2LNd16, VLD2LNq16a, VLD2LNq16b, VLD2d16, VLD2q16, VLD3LNd1...
|
|
O << ".16\t{";
|
|
break;
|
|
case 70:
|
|
// VLD1d32, VLD1df, VLD2LNd32, VLD2LNq32a, VLD2LNq32b, VLD2d32, VLD2q32, ...
|
|
O << ".32\t{";
|
|
break;
|
|
case 71:
|
|
// VLD1d64, VLD2d64, VLD3d64, VLD4d64, VST1d64, VST2d64, VST3d64, VST4d64
|
|
O << ".64\t{";
|
|
break;
|
|
case 72:
|
|
// VLD1d8, VLD2LNd8, VLD2d8, VLD2q8, VLD3LNd8, VLD3d8, VLD3q8a, VLD3q8b, ...
|
|
O << ".8\t{";
|
|
break;
|
|
case 73:
|
|
// VLD1q64, VLDRD, VSLIv1i64, VSLIv2i64, VSRIv1i64, VSRIv2i64, VST1q64, V...
|
|
O << ".64\t";
|
|
break;
|
|
case 74:
|
|
// VMULLp, VMULpd, VMULpq
|
|
O << ".p8\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 75:
|
|
// VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
|
|
O << ".s64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 76:
|
|
// VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ...
|
|
O << ".u64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 77:
|
|
// VSITOD
|
|
O << ".f64.s32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 78:
|
|
// VTOSIZD
|
|
O << ".s32.f64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 79:
|
|
// VTOUIZD
|
|
O << ".u32.f64\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 80:
|
|
// VUITOD
|
|
O << ".f64.u32\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 81:
|
|
// t2ADCrr, t2ADCrs, t2ADDSri, t2ADDSrr, t2ADDSrs, t2ADDrSPi, t2ADDrSPs, ...
|
|
O << ".w\t";
|
|
printOperand(MI, 0);
|
|
break;
|
|
case 82:
|
|
// t2BR_JT
|
|
O << "\n";
|
|
printJT2BlockOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 83:
|
|
// t2Int_eh_sjlj_setjmp
|
|
O << ", #+8] @ eh_setjmp begin\n\tadr\tr12, 0f\n\torr.w\tr12, r12, #1\n\tstr.w\tr12, [";
|
|
printOperand(MI, 0);
|
|
O << ", #+4]\n\tmovs\tr0, #0\n\tb\t1f\n0:\tmovs\tr0, #1 @ eh_setjmp end\n1:";
|
|
return;
|
|
break;
|
|
case 84:
|
|
// t2LDM, t2LDM_RET, t2STM
|
|
printAddrMode4Operand(MI, 0, "wide");
|
|
O << "\t";
|
|
printAddrMode4Operand(MI, 0);
|
|
O << ", ";
|
|
printRegisterList(MI, 4);
|
|
return;
|
|
break;
|
|
case 85:
|
|
// t2MOVi, t2MOVr, t2MOVrx, t2MVNi
|
|
printPredicateOperand(MI, 2);
|
|
break;
|
|
case 86:
|
|
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
|
|
printPredicateOperand(MI, 4);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
break;
|
|
case 87:
|
|
// tADDrPCi
|
|
O << ", pc, ";
|
|
printThumbS4ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 88:
|
|
// tBR_JTr
|
|
O << "\n\t.align\t2\n";
|
|
printJTBlockOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 89:
|
|
// tBfar
|
|
O << "\t@ far jump";
|
|
return;
|
|
break;
|
|
case 90:
|
|
// tInt_eh_sjlj_setjmp
|
|
O << ", #8]\n\tadr\tr1, 0f\n\tadds\tr1, #1\n\tstr\tr1, [";
|
|
printOperand(MI, 0);
|
|
O << ", #4]\n\tmov\tr1, r12\n\tmovs\tr0, #0\n\tb\t1f\n.align 2\n0:\tmovs\tr0, #1\t@ end eh.setjmp\n1:";
|
|
return;
|
|
break;
|
|
case 91:
|
|
// tLDRpci
|
|
O << ".n\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 92:
|
|
// tMOVi8, tMVN, tRSB
|
|
printPredicateOperand(MI, 3);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
break;
|
|
case 93:
|
|
// tPICADD
|
|
O << ":\n\tadd\t";
|
|
printOperand(MI, 0);
|
|
O << ", pc";
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 2 encoded into 5 bits for 26 unique commands.
|
|
switch ((Bits >> 15) & 31) {
|
|
default: // unreachable.
|
|
case 0:
|
|
// ADCSSri, ADCSSrr, ADCSSrs, BR_JTadd, MLA, MOVr, MOVrx, MVNr, RSCSri, R...
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 1:
|
|
// ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri
|
|
printSOImmOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// ADCrr, ADDrr, ANDrr, BICrr, EORrr, MUL, ORRrr, SBCrr, SUBrr, VABALsv2i...
|
|
printOperand(MI, 2);
|
|
break;
|
|
case 3:
|
|
// ADDSri, ADDSrr, ADDSrs, BFC, Bcc, CLZ, CMNri, CMNrr, CMNrs, CMNzri, CM...
|
|
printOperand(MI, 0);
|
|
break;
|
|
case 4:
|
|
// BL_pred, BLr9_pred
|
|
printOperand(MI, 0, "call");
|
|
return;
|
|
break;
|
|
case 5:
|
|
// FCONSTD, FCONSTS, VABDfd, VABDfq, VABSD, VABSS, VABSfd, VABSfd_sfp, VA...
|
|
O << ", ";
|
|
break;
|
|
case 6:
|
|
// LDM, LDM_RET, STM, tLDM, tSTM
|
|
printAddrMode4Operand(MI, 0);
|
|
O << ", ";
|
|
printRegisterList(MI, 4);
|
|
return;
|
|
break;
|
|
case 7:
|
|
// MOVi, MVNi
|
|
printSOImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 8:
|
|
// MOVs, MVNs
|
|
printSORegOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 9:
|
|
// VCMPEZD, VCMPEZS, tRSB
|
|
O << ", #0";
|
|
return;
|
|
break;
|
|
case 10:
|
|
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VC...
|
|
return;
|
|
break;
|
|
case 11:
|
|
// VLD1q16, VLD1q32, VLD1q64, VLD1q8, VLD1qf
|
|
printOperand(MI, 0, "dregpair");
|
|
O << ", ";
|
|
printAddrMode6Operand(MI, 1);
|
|
return;
|
|
break;
|
|
case 12:
|
|
// VLDRQ, VSTRQ
|
|
printAddrMode4Operand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 0, "dregpair");
|
|
return;
|
|
break;
|
|
case 13:
|
|
// VMOVv16i8, VMOVv8i8
|
|
printHex8ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 14:
|
|
// VMOVv1i64, VMOVv2i64
|
|
printHex64ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 15:
|
|
// VMOVv2i32, VMOVv4i32
|
|
printHex32ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 16:
|
|
// VMOVv4i16, VMOVv8i16
|
|
printHex16ImmOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 17:
|
|
// VST1d16, VST1d32, VST1d64, VST1d8, VST1df, VST2LNd16, VST2LNd32, VST2L...
|
|
printOperand(MI, 4);
|
|
break;
|
|
case 18:
|
|
// VST1q16, VST1q32, VST1q64, VST1q8, VST1qf
|
|
printOperand(MI, 4, "dregpair");
|
|
O << ", ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case 19:
|
|
// VST3q16a, VST3q16b, VST3q32a, VST3q32b, VST3q8a, VST3q8b, VST4q16a, VS...
|
|
printOperand(MI, 5);
|
|
O << ',';
|
|
printOperand(MI, 6);
|
|
O << ',';
|
|
printOperand(MI, 7);
|
|
break;
|
|
case 20:
|
|
// t2LEApcrel, t2LEApcrelJT
|
|
O << ", #";
|
|
printOperand(MI, 1);
|
|
break;
|
|
case 21:
|
|
// t2MOVi, t2MOVr
|
|
O << ".w\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 22:
|
|
// t2MOVrx, t2MVNi
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case 23:
|
|
// tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tMUL, tORR, tR...
|
|
printOperand(MI, 3);
|
|
return;
|
|
break;
|
|
case 24:
|
|
// tADDspi, tSUBspi, tSUBspi_
|
|
printThumbS4ImmOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case 25:
|
|
// tPOP, tPOP_RET, tPUSH
|
|
printRegisterList(MI, 2);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
switch (MI->getOpcode()) {
|
|
case ARM::ADCSSri:
|
|
case ARM::ADCSSrr:
|
|
case ARM::ADCSSrs:
|
|
case ARM::BFC:
|
|
case ARM::CLZ:
|
|
case ARM::CMNri:
|
|
case ARM::CMNrr:
|
|
case ARM::CMNrs:
|
|
case ARM::CMNzri:
|
|
case ARM::CMNzrr:
|
|
case ARM::CMNzrs:
|
|
case ARM::CMPri:
|
|
case ARM::CMPrr:
|
|
case ARM::CMPrs:
|
|
case ARM::CMPzri:
|
|
case ARM::CMPzrr:
|
|
case ARM::CMPzrs:
|
|
case ARM::LDR:
|
|
case ARM::LDRB:
|
|
case ARM::LDRD:
|
|
case ARM::LDRH:
|
|
case ARM::LDRSB:
|
|
case ARM::LDRSH:
|
|
case ARM::LDRcp:
|
|
case ARM::MOVCCi:
|
|
case ARM::MOVCCr:
|
|
case ARM::MOVCCs:
|
|
case ARM::MOVTi16:
|
|
case ARM::MOVi16:
|
|
case ARM::MOVi2pieces:
|
|
case ARM::REV:
|
|
case ARM::REV16:
|
|
case ARM::REVSH:
|
|
case ARM::RSCSri:
|
|
case ARM::RSCSrs:
|
|
case ARM::SBCSSri:
|
|
case ARM::SBCSSrr:
|
|
case ARM::SBCSSrs:
|
|
case ARM::STR:
|
|
case ARM::STRB:
|
|
case ARM::STRD:
|
|
case ARM::STRH:
|
|
case ARM::SXTBr:
|
|
case ARM::SXTHr:
|
|
case ARM::TEQri:
|
|
case ARM::TEQrr:
|
|
case ARM::TEQrs:
|
|
case ARM::TSTri:
|
|
case ARM::TSTrr:
|
|
case ARM::TSTrs:
|
|
case ARM::UXTB16r:
|
|
case ARM::UXTBr:
|
|
case ARM::UXTHr:
|
|
case ARM::VABALsv2i64:
|
|
case ARM::VABALsv4i32:
|
|
case ARM::VABALsv8i16:
|
|
case ARM::VABALuv2i64:
|
|
case ARM::VABALuv4i32:
|
|
case ARM::VABALuv8i16:
|
|
case ARM::VABAsv16i8:
|
|
case ARM::VABAsv2i32:
|
|
case ARM::VABAsv4i16:
|
|
case ARM::VABAsv4i32:
|
|
case ARM::VABAsv8i16:
|
|
case ARM::VABAsv8i8:
|
|
case ARM::VABAuv16i8:
|
|
case ARM::VABAuv2i32:
|
|
case ARM::VABAuv4i16:
|
|
case ARM::VABAuv4i32:
|
|
case ARM::VABAuv8i16:
|
|
case ARM::VABAuv8i8:
|
|
case ARM::VABDLsv2i64:
|
|
case ARM::VABDLsv4i32:
|
|
case ARM::VABDLsv8i16:
|
|
case ARM::VABDLuv2i64:
|
|
case ARM::VABDLuv4i32:
|
|
case ARM::VABDLuv8i16:
|
|
case ARM::VABDsv16i8:
|
|
case ARM::VABDsv2i32:
|
|
case ARM::VABDsv4i16:
|
|
case ARM::VABDsv4i32:
|
|
case ARM::VABDsv8i16:
|
|
case ARM::VABDsv8i8:
|
|
case ARM::VABDuv16i8:
|
|
case ARM::VABDuv2i32:
|
|
case ARM::VABDuv4i16:
|
|
case ARM::VABDuv4i32:
|
|
case ARM::VABDuv8i16:
|
|
case ARM::VABDuv8i8:
|
|
case ARM::VADDHNv2i32:
|
|
case ARM::VADDHNv4i16:
|
|
case ARM::VADDHNv8i8:
|
|
case ARM::VADDLsv2i64:
|
|
case ARM::VADDLsv4i32:
|
|
case ARM::VADDLsv8i16:
|
|
case ARM::VADDLuv2i64:
|
|
case ARM::VADDLuv4i32:
|
|
case ARM::VADDLuv8i16:
|
|
case ARM::VADDWsv2i64:
|
|
case ARM::VADDWsv4i32:
|
|
case ARM::VADDWsv8i16:
|
|
case ARM::VADDWuv2i64:
|
|
case ARM::VADDWuv4i32:
|
|
case ARM::VADDWuv8i16:
|
|
case ARM::VADDv16i8:
|
|
case ARM::VADDv1i64:
|
|
case ARM::VADDv2i32:
|
|
case ARM::VADDv2i64:
|
|
case ARM::VADDv4i16:
|
|
case ARM::VADDv4i32:
|
|
case ARM::VADDv8i16:
|
|
case ARM::VADDv8i8:
|
|
case ARM::VCEQv16i8:
|
|
case ARM::VCEQv2i32:
|
|
case ARM::VCEQv4i16:
|
|
case ARM::VCEQv4i32:
|
|
case ARM::VCEQv8i16:
|
|
case ARM::VCEQv8i8:
|
|
case ARM::VCGEsv16i8:
|
|
case ARM::VCGEsv2i32:
|
|
case ARM::VCGEsv4i16:
|
|
case ARM::VCGEsv4i32:
|
|
case ARM::VCGEsv8i16:
|
|
case ARM::VCGEsv8i8:
|
|
case ARM::VCGEuv16i8:
|
|
case ARM::VCGEuv2i32:
|
|
case ARM::VCGEuv4i16:
|
|
case ARM::VCGEuv4i32:
|
|
case ARM::VCGEuv8i16:
|
|
case ARM::VCGEuv8i8:
|
|
case ARM::VCGTsv16i8:
|
|
case ARM::VCGTsv2i32:
|
|
case ARM::VCGTsv4i16:
|
|
case ARM::VCGTsv4i32:
|
|
case ARM::VCGTsv8i16:
|
|
case ARM::VCGTsv8i8:
|
|
case ARM::VCGTuv16i8:
|
|
case ARM::VCGTuv2i32:
|
|
case ARM::VCGTuv4i16:
|
|
case ARM::VCGTuv4i32:
|
|
case ARM::VCGTuv8i16:
|
|
case ARM::VCGTuv8i8:
|
|
case ARM::VCNTd:
|
|
case ARM::VCNTq:
|
|
case ARM::VDUP16d:
|
|
case ARM::VDUP16q:
|
|
case ARM::VDUP32d:
|
|
case ARM::VDUP32q:
|
|
case ARM::VDUP8d:
|
|
case ARM::VDUP8q:
|
|
case ARM::VDUPfd:
|
|
case ARM::VDUPfdf:
|
|
case ARM::VDUPfq:
|
|
case ARM::VDUPfqf:
|
|
case ARM::VHADDsv16i8:
|
|
case ARM::VHADDsv2i32:
|
|
case ARM::VHADDsv4i16:
|
|
case ARM::VHADDsv4i32:
|
|
case ARM::VHADDsv8i16:
|
|
case ARM::VHADDsv8i8:
|
|
case ARM::VHADDuv16i8:
|
|
case ARM::VHADDuv2i32:
|
|
case ARM::VHADDuv4i16:
|
|
case ARM::VHADDuv4i32:
|
|
case ARM::VHADDuv8i16:
|
|
case ARM::VHADDuv8i8:
|
|
case ARM::VHSUBsv16i8:
|
|
case ARM::VHSUBsv2i32:
|
|
case ARM::VHSUBsv4i16:
|
|
case ARM::VHSUBsv4i32:
|
|
case ARM::VHSUBsv8i16:
|
|
case ARM::VHSUBsv8i8:
|
|
case ARM::VHSUBuv16i8:
|
|
case ARM::VHSUBuv2i32:
|
|
case ARM::VHSUBuv4i16:
|
|
case ARM::VHSUBuv4i32:
|
|
case ARM::VHSUBuv8i16:
|
|
case ARM::VHSUBuv8i8:
|
|
case ARM::VLDRD:
|
|
case ARM::VLDRS:
|
|
case ARM::VMAXsv16i8:
|
|
case ARM::VMAXsv2i32:
|
|
case ARM::VMAXsv4i16:
|
|
case ARM::VMAXsv4i32:
|
|
case ARM::VMAXsv8i16:
|
|
case ARM::VMAXsv8i8:
|
|
case ARM::VMAXuv16i8:
|
|
case ARM::VMAXuv2i32:
|
|
case ARM::VMAXuv4i16:
|
|
case ARM::VMAXuv4i32:
|
|
case ARM::VMAXuv8i16:
|
|
case ARM::VMAXuv8i8:
|
|
case ARM::VMINsv16i8:
|
|
case ARM::VMINsv2i32:
|
|
case ARM::VMINsv4i16:
|
|
case ARM::VMINsv4i32:
|
|
case ARM::VMINsv8i16:
|
|
case ARM::VMINsv8i8:
|
|
case ARM::VMINuv16i8:
|
|
case ARM::VMINuv2i32:
|
|
case ARM::VMINuv4i16:
|
|
case ARM::VMINuv4i32:
|
|
case ARM::VMINuv8i16:
|
|
case ARM::VMINuv8i8:
|
|
case ARM::VMLALsv2i64:
|
|
case ARM::VMLALsv4i32:
|
|
case ARM::VMLALsv8i16:
|
|
case ARM::VMLALuv2i64:
|
|
case ARM::VMLALuv4i32:
|
|
case ARM::VMLALuv8i16:
|
|
case ARM::VMLAv16i8:
|
|
case ARM::VMLAv2i32:
|
|
case ARM::VMLAv4i16:
|
|
case ARM::VMLAv4i32:
|
|
case ARM::VMLAv8i16:
|
|
case ARM::VMLAv8i8:
|
|
case ARM::VMLSLsv2i64:
|
|
case ARM::VMLSLsv4i32:
|
|
case ARM::VMLSLsv8i16:
|
|
case ARM::VMLSLuv2i64:
|
|
case ARM::VMLSLuv4i32:
|
|
case ARM::VMLSLuv8i16:
|
|
case ARM::VMLSv16i8:
|
|
case ARM::VMLSv2i32:
|
|
case ARM::VMLSv4i16:
|
|
case ARM::VMLSv4i32:
|
|
case ARM::VMLSv8i16:
|
|
case ARM::VMLSv8i8:
|
|
case ARM::VMOVDneon:
|
|
case ARM::VMOVQ:
|
|
case ARM::VMOVRS:
|
|
case ARM::VMOVSR:
|
|
case ARM::VMULLsv2i64:
|
|
case ARM::VMULLsv4i32:
|
|
case ARM::VMULLsv8i16:
|
|
case ARM::VMULLuv2i64:
|
|
case ARM::VMULLuv4i32:
|
|
case ARM::VMULLuv8i16:
|
|
case ARM::VMULv16i8:
|
|
case ARM::VMULv2i32:
|
|
case ARM::VMULv4i16:
|
|
case ARM::VMULv4i32:
|
|
case ARM::VMULv8i16:
|
|
case ARM::VMULv8i8:
|
|
case ARM::VMVNd:
|
|
case ARM::VMVNq:
|
|
case ARM::VPADDi16:
|
|
case ARM::VPADDi32:
|
|
case ARM::VPADDi8:
|
|
case ARM::VPMAXs16:
|
|
case ARM::VPMAXs32:
|
|
case ARM::VPMAXs8:
|
|
case ARM::VPMAXu16:
|
|
case ARM::VPMAXu32:
|
|
case ARM::VPMAXu8:
|
|
case ARM::VPMINs16:
|
|
case ARM::VPMINs32:
|
|
case ARM::VPMINs8:
|
|
case ARM::VPMINu16:
|
|
case ARM::VPMINu32:
|
|
case ARM::VPMINu8:
|
|
case ARM::VQADDsv16i8:
|
|
case ARM::VQADDsv1i64:
|
|
case ARM::VQADDsv2i32:
|
|
case ARM::VQADDsv2i64:
|
|
case ARM::VQADDsv4i16:
|
|
case ARM::VQADDsv4i32:
|
|
case ARM::VQADDsv8i16:
|
|
case ARM::VQADDsv8i8:
|
|
case ARM::VQADDuv16i8:
|
|
case ARM::VQADDuv1i64:
|
|
case ARM::VQADDuv2i32:
|
|
case ARM::VQADDuv2i64:
|
|
case ARM::VQADDuv4i16:
|
|
case ARM::VQADDuv4i32:
|
|
case ARM::VQADDuv8i16:
|
|
case ARM::VQADDuv8i8:
|
|
case ARM::VQDMLALv2i64:
|
|
case ARM::VQDMLALv4i32:
|
|
case ARM::VQDMLSLv2i64:
|
|
case ARM::VQDMLSLv4i32:
|
|
case ARM::VQDMULHv2i32:
|
|
case ARM::VQDMULHv4i16:
|
|
case ARM::VQDMULHv4i32:
|
|
case ARM::VQDMULHv8i16:
|
|
case ARM::VQDMULLv2i64:
|
|
case ARM::VQDMULLv4i32:
|
|
case ARM::VQRDMULHv2i32:
|
|
case ARM::VQRDMULHv4i16:
|
|
case ARM::VQRDMULHv4i32:
|
|
case ARM::VQRDMULHv8i16:
|
|
case ARM::VQRSHLsv16i8:
|
|
case ARM::VQRSHLsv1i64:
|
|
case ARM::VQRSHLsv2i32:
|
|
case ARM::VQRSHLsv2i64:
|
|
case ARM::VQRSHLsv4i16:
|
|
case ARM::VQRSHLsv4i32:
|
|
case ARM::VQRSHLsv8i16:
|
|
case ARM::VQRSHLsv8i8:
|
|
case ARM::VQRSHLuv16i8:
|
|
case ARM::VQRSHLuv1i64:
|
|
case ARM::VQRSHLuv2i32:
|
|
case ARM::VQRSHLuv2i64:
|
|
case ARM::VQRSHLuv4i16:
|
|
case ARM::VQRSHLuv4i32:
|
|
case ARM::VQRSHLuv8i16:
|
|
case ARM::VQRSHLuv8i8:
|
|
case ARM::VQRSHRNsv2i32:
|
|
case ARM::VQRSHRNsv4i16:
|
|
case ARM::VQRSHRNsv8i8:
|
|
case ARM::VQRSHRNuv2i32:
|
|
case ARM::VQRSHRNuv4i16:
|
|
case ARM::VQRSHRNuv8i8:
|
|
case ARM::VQRSHRUNv2i32:
|
|
case ARM::VQRSHRUNv4i16:
|
|
case ARM::VQRSHRUNv8i8:
|
|
case ARM::VQSHLsiv16i8:
|
|
case ARM::VQSHLsiv1i64:
|
|
case ARM::VQSHLsiv2i32:
|
|
case ARM::VQSHLsiv2i64:
|
|
case ARM::VQSHLsiv4i16:
|
|
case ARM::VQSHLsiv4i32:
|
|
case ARM::VQSHLsiv8i16:
|
|
case ARM::VQSHLsiv8i8:
|
|
case ARM::VQSHLsuv16i8:
|
|
case ARM::VQSHLsuv1i64:
|
|
case ARM::VQSHLsuv2i32:
|
|
case ARM::VQSHLsuv2i64:
|
|
case ARM::VQSHLsuv4i16:
|
|
case ARM::VQSHLsuv4i32:
|
|
case ARM::VQSHLsuv8i16:
|
|
case ARM::VQSHLsuv8i8:
|
|
case ARM::VQSHLsv16i8:
|
|
case ARM::VQSHLsv1i64:
|
|
case ARM::VQSHLsv2i32:
|
|
case ARM::VQSHLsv2i64:
|
|
case ARM::VQSHLsv4i16:
|
|
case ARM::VQSHLsv4i32:
|
|
case ARM::VQSHLsv8i16:
|
|
case ARM::VQSHLsv8i8:
|
|
case ARM::VQSHLuiv16i8:
|
|
case ARM::VQSHLuiv1i64:
|
|
case ARM::VQSHLuiv2i32:
|
|
case ARM::VQSHLuiv2i64:
|
|
case ARM::VQSHLuiv4i16:
|
|
case ARM::VQSHLuiv4i32:
|
|
case ARM::VQSHLuiv8i16:
|
|
case ARM::VQSHLuiv8i8:
|
|
case ARM::VQSHLuv16i8:
|
|
case ARM::VQSHLuv1i64:
|
|
case ARM::VQSHLuv2i32:
|
|
case ARM::VQSHLuv2i64:
|
|
case ARM::VQSHLuv4i16:
|
|
case ARM::VQSHLuv4i32:
|
|
case ARM::VQSHLuv8i16:
|
|
case ARM::VQSHLuv8i8:
|
|
case ARM::VQSHRNsv2i32:
|
|
case ARM::VQSHRNsv4i16:
|
|
case ARM::VQSHRNsv8i8:
|
|
case ARM::VQSHRNuv2i32:
|
|
case ARM::VQSHRNuv4i16:
|
|
case ARM::VQSHRNuv8i8:
|
|
case ARM::VQSHRUNv2i32:
|
|
case ARM::VQSHRUNv4i16:
|
|
case ARM::VQSHRUNv8i8:
|
|
case ARM::VQSUBsv16i8:
|
|
case ARM::VQSUBsv1i64:
|
|
case ARM::VQSUBsv2i32:
|
|
case ARM::VQSUBsv2i64:
|
|
case ARM::VQSUBsv4i16:
|
|
case ARM::VQSUBsv4i32:
|
|
case ARM::VQSUBsv8i16:
|
|
case ARM::VQSUBsv8i8:
|
|
case ARM::VQSUBuv16i8:
|
|
case ARM::VQSUBuv1i64:
|
|
case ARM::VQSUBuv2i32:
|
|
case ARM::VQSUBuv2i64:
|
|
case ARM::VQSUBuv4i16:
|
|
case ARM::VQSUBuv4i32:
|
|
case ARM::VQSUBuv8i16:
|
|
case ARM::VQSUBuv8i8:
|
|
case ARM::VRADDHNv2i32:
|
|
case ARM::VRADDHNv4i16:
|
|
case ARM::VRADDHNv8i8:
|
|
case ARM::VREV16d8:
|
|
case ARM::VREV16q8:
|
|
case ARM::VREV32d16:
|
|
case ARM::VREV32d8:
|
|
case ARM::VREV32q16:
|
|
case ARM::VREV32q8:
|
|
case ARM::VREV64d16:
|
|
case ARM::VREV64d32:
|
|
case ARM::VREV64d8:
|
|
case ARM::VREV64df:
|
|
case ARM::VREV64q16:
|
|
case ARM::VREV64q32:
|
|
case ARM::VREV64q8:
|
|
case ARM::VREV64qf:
|
|
case ARM::VRHADDsv16i8:
|
|
case ARM::VRHADDsv2i32:
|
|
case ARM::VRHADDsv4i16:
|
|
case ARM::VRHADDsv4i32:
|
|
case ARM::VRHADDsv8i16:
|
|
case ARM::VRHADDsv8i8:
|
|
case ARM::VRHADDuv16i8:
|
|
case ARM::VRHADDuv2i32:
|
|
case ARM::VRHADDuv4i16:
|
|
case ARM::VRHADDuv4i32:
|
|
case ARM::VRHADDuv8i16:
|
|
case ARM::VRHADDuv8i8:
|
|
case ARM::VRSHLsv16i8:
|
|
case ARM::VRSHLsv1i64:
|
|
case ARM::VRSHLsv2i32:
|
|
case ARM::VRSHLsv2i64:
|
|
case ARM::VRSHLsv4i16:
|
|
case ARM::VRSHLsv4i32:
|
|
case ARM::VRSHLsv8i16:
|
|
case ARM::VRSHLsv8i8:
|
|
case ARM::VRSHLuv16i8:
|
|
case ARM::VRSHLuv1i64:
|
|
case ARM::VRSHLuv2i32:
|
|
case ARM::VRSHLuv2i64:
|
|
case ARM::VRSHLuv4i16:
|
|
case ARM::VRSHLuv4i32:
|
|
case ARM::VRSHLuv8i16:
|
|
case ARM::VRSHLuv8i8:
|
|
case ARM::VRSHRNv2i32:
|
|
case ARM::VRSHRNv4i16:
|
|
case ARM::VRSHRNv8i8:
|
|
case ARM::VRSHRsv16i8:
|
|
case ARM::VRSHRsv1i64:
|
|
case ARM::VRSHRsv2i32:
|
|
case ARM::VRSHRsv2i64:
|
|
case ARM::VRSHRsv4i16:
|
|
case ARM::VRSHRsv4i32:
|
|
case ARM::VRSHRsv8i16:
|
|
case ARM::VRSHRsv8i8:
|
|
case ARM::VRSHRuv16i8:
|
|
case ARM::VRSHRuv1i64:
|
|
case ARM::VRSHRuv2i32:
|
|
case ARM::VRSHRuv2i64:
|
|
case ARM::VRSHRuv4i16:
|
|
case ARM::VRSHRuv4i32:
|
|
case ARM::VRSHRuv8i16:
|
|
case ARM::VRSHRuv8i8:
|
|
case ARM::VRSRAsv16i8:
|
|
case ARM::VRSRAsv1i64:
|
|
case ARM::VRSRAsv2i32:
|
|
case ARM::VRSRAsv2i64:
|
|
case ARM::VRSRAsv4i16:
|
|
case ARM::VRSRAsv4i32:
|
|
case ARM::VRSRAsv8i16:
|
|
case ARM::VRSRAsv8i8:
|
|
case ARM::VRSRAuv16i8:
|
|
case ARM::VRSRAuv1i64:
|
|
case ARM::VRSRAuv2i32:
|
|
case ARM::VRSRAuv2i64:
|
|
case ARM::VRSRAuv4i16:
|
|
case ARM::VRSRAuv4i32:
|
|
case ARM::VRSRAuv8i16:
|
|
case ARM::VRSRAuv8i8:
|
|
case ARM::VRSUBHNv2i32:
|
|
case ARM::VRSUBHNv4i16:
|
|
case ARM::VRSUBHNv8i8:
|
|
case ARM::VSHLLi16:
|
|
case ARM::VSHLLi32:
|
|
case ARM::VSHLLi8:
|
|
case ARM::VSHLLsv2i64:
|
|
case ARM::VSHLLsv4i32:
|
|
case ARM::VSHLLsv8i16:
|
|
case ARM::VSHLLuv2i64:
|
|
case ARM::VSHLLuv4i32:
|
|
case ARM::VSHLLuv8i16:
|
|
case ARM::VSHLiv16i8:
|
|
case ARM::VSHLiv1i64:
|
|
case ARM::VSHLiv2i32:
|
|
case ARM::VSHLiv2i64:
|
|
case ARM::VSHLiv4i16:
|
|
case ARM::VSHLiv4i32:
|
|
case ARM::VSHLiv8i16:
|
|
case ARM::VSHLiv8i8:
|
|
case ARM::VSHLsv16i8:
|
|
case ARM::VSHLsv1i64:
|
|
case ARM::VSHLsv2i32:
|
|
case ARM::VSHLsv2i64:
|
|
case ARM::VSHLsv4i16:
|
|
case ARM::VSHLsv4i32:
|
|
case ARM::VSHLsv8i16:
|
|
case ARM::VSHLsv8i8:
|
|
case ARM::VSHLuv16i8:
|
|
case ARM::VSHLuv1i64:
|
|
case ARM::VSHLuv2i32:
|
|
case ARM::VSHLuv2i64:
|
|
case ARM::VSHLuv4i16:
|
|
case ARM::VSHLuv4i32:
|
|
case ARM::VSHLuv8i16:
|
|
case ARM::VSHLuv8i8:
|
|
case ARM::VSHRNv2i32:
|
|
case ARM::VSHRNv4i16:
|
|
case ARM::VSHRNv8i8:
|
|
case ARM::VSHRsv16i8:
|
|
case ARM::VSHRsv1i64:
|
|
case ARM::VSHRsv2i32:
|
|
case ARM::VSHRsv2i64:
|
|
case ARM::VSHRsv4i16:
|
|
case ARM::VSHRsv4i32:
|
|
case ARM::VSHRsv8i16:
|
|
case ARM::VSHRsv8i8:
|
|
case ARM::VSHRuv16i8:
|
|
case ARM::VSHRuv1i64:
|
|
case ARM::VSHRuv2i32:
|
|
case ARM::VSHRuv2i64:
|
|
case ARM::VSHRuv4i16:
|
|
case ARM::VSHRuv4i32:
|
|
case ARM::VSHRuv8i16:
|
|
case ARM::VSHRuv8i8:
|
|
case ARM::VSRAsv16i8:
|
|
case ARM::VSRAsv1i64:
|
|
case ARM::VSRAsv2i32:
|
|
case ARM::VSRAsv2i64:
|
|
case ARM::VSRAsv4i16:
|
|
case ARM::VSRAsv4i32:
|
|
case ARM::VSRAsv8i16:
|
|
case ARM::VSRAsv8i8:
|
|
case ARM::VSRAuv16i8:
|
|
case ARM::VSRAuv1i64:
|
|
case ARM::VSRAuv2i32:
|
|
case ARM::VSRAuv2i64:
|
|
case ARM::VSRAuv4i16:
|
|
case ARM::VSRAuv4i32:
|
|
case ARM::VSRAuv8i16:
|
|
case ARM::VSRAuv8i8:
|
|
case ARM::VSTRD:
|
|
case ARM::VSTRS:
|
|
case ARM::VSUBHNv2i32:
|
|
case ARM::VSUBHNv4i16:
|
|
case ARM::VSUBHNv8i8:
|
|
case ARM::VSUBLsv2i64:
|
|
case ARM::VSUBLsv4i32:
|
|
case ARM::VSUBLsv8i16:
|
|
case ARM::VSUBLuv2i64:
|
|
case ARM::VSUBLuv4i32:
|
|
case ARM::VSUBLuv8i16:
|
|
case ARM::VSUBWsv2i64:
|
|
case ARM::VSUBWsv4i32:
|
|
case ARM::VSUBWsv8i16:
|
|
case ARM::VSUBWuv2i64:
|
|
case ARM::VSUBWuv4i32:
|
|
case ARM::VSUBWuv8i16:
|
|
case ARM::VSUBv16i8:
|
|
case ARM::VSUBv1i64:
|
|
case ARM::VSUBv2i32:
|
|
case ARM::VSUBv2i64:
|
|
case ARM::VSUBv4i16:
|
|
case ARM::VSUBv4i32:
|
|
case ARM::VSUBv8i16:
|
|
case ARM::VSUBv8i8:
|
|
case ARM::VTRNd16:
|
|
case ARM::VTRNd32:
|
|
case ARM::VTRNd8:
|
|
case ARM::VTRNq16:
|
|
case ARM::VTRNq32:
|
|
case ARM::VTRNq8:
|
|
case ARM::VTSTv16i8:
|
|
case ARM::VTSTv2i32:
|
|
case ARM::VTSTv4i16:
|
|
case ARM::VTSTv4i32:
|
|
case ARM::VTSTv8i16:
|
|
case ARM::VTSTv8i8:
|
|
case ARM::VUZPd16:
|
|
case ARM::VUZPd32:
|
|
case ARM::VUZPd8:
|
|
case ARM::VUZPq16:
|
|
case ARM::VUZPq32:
|
|
case ARM::VUZPq8:
|
|
case ARM::VZIPd16:
|
|
case ARM::VZIPd32:
|
|
case ARM::VZIPd8:
|
|
case ARM::VZIPq16:
|
|
case ARM::VZIPq32:
|
|
case ARM::VZIPq8:
|
|
case ARM::t2ADCSri:
|
|
case ARM::t2ADCSrr:
|
|
case ARM::t2ADCSrs:
|
|
case ARM::t2BFC:
|
|
case ARM::t2CLZ:
|
|
case ARM::t2LDRBi8:
|
|
case ARM::t2LDRDi8:
|
|
case ARM::t2LDRDpci:
|
|
case ARM::t2LDRHi8:
|
|
case ARM::t2LDRSBi8:
|
|
case ARM::t2LDRSHi8:
|
|
case ARM::t2LDRi8:
|
|
case ARM::t2MOVTi16:
|
|
case ARM::t2MOVi16:
|
|
case ARM::t2SBCSri:
|
|
case ARM::t2SBCSrr:
|
|
case ARM::t2SBCSrs:
|
|
case ARM::t2STRBi8:
|
|
case ARM::t2STRDi8:
|
|
case ARM::t2STRHi8:
|
|
case ARM::t2STRi8:
|
|
case ARM::t2SUBrSPi12_:
|
|
case ARM::t2SUBrSPi_:
|
|
case ARM::t2SUBrSPs_:
|
|
case ARM::tADDhirr:
|
|
case ARM::tADDi3:
|
|
case ARM::tADDrSPi:
|
|
case ARM::tADDrr:
|
|
case ARM::tASRri:
|
|
case ARM::tCMN:
|
|
case ARM::tCMNz:
|
|
case ARM::tCMPhir:
|
|
case ARM::tCMPi8:
|
|
case ARM::tCMPr:
|
|
case ARM::tCMPzhir:
|
|
case ARM::tCMPzi8:
|
|
case ARM::tCMPzr:
|
|
case ARM::tLDR:
|
|
case ARM::tLDRB:
|
|
case ARM::tLDRH:
|
|
case ARM::tLDRSB:
|
|
case ARM::tLDRSH:
|
|
case ARM::tLDRcp:
|
|
case ARM::tLDRspi:
|
|
case ARM::tLSLri:
|
|
case ARM::tLSRri:
|
|
case ARM::tMOVCCi:
|
|
case ARM::tMOVCCr:
|
|
case ARM::tREV:
|
|
case ARM::tREV16:
|
|
case ARM::tREVSH:
|
|
case ARM::tRestore:
|
|
case ARM::tSTR:
|
|
case ARM::tSTRB:
|
|
case ARM::tSTRH:
|
|
case ARM::tSTRspi:
|
|
case ARM::tSUBi3:
|
|
case ARM::tSUBrr:
|
|
case ARM::tSXTB:
|
|
case ARM::tSXTH:
|
|
case ARM::tSpill:
|
|
case ARM::tTST:
|
|
case ARM::tUXTB:
|
|
case ARM::tUXTH:
|
|
O << ", ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::ADCSSri:
|
|
case ARM::MOVCCi:
|
|
case ARM::RSCSri:
|
|
case ARM::SBCSSri: printSOImmOperand(MI, 2); break;
|
|
case ARM::ADCSSrr:
|
|
case ARM::MOVCCr:
|
|
case ARM::MOVTi16:
|
|
case ARM::SBCSSrr:
|
|
case ARM::VABDLsv2i64:
|
|
case ARM::VABDLsv4i32:
|
|
case ARM::VABDLsv8i16:
|
|
case ARM::VABDLuv2i64:
|
|
case ARM::VABDLuv4i32:
|
|
case ARM::VABDLuv8i16:
|
|
case ARM::VABDsv16i8:
|
|
case ARM::VABDsv2i32:
|
|
case ARM::VABDsv4i16:
|
|
case ARM::VABDsv4i32:
|
|
case ARM::VABDsv8i16:
|
|
case ARM::VABDsv8i8:
|
|
case ARM::VABDuv16i8:
|
|
case ARM::VABDuv2i32:
|
|
case ARM::VABDuv4i16:
|
|
case ARM::VABDuv4i32:
|
|
case ARM::VABDuv8i16:
|
|
case ARM::VABDuv8i8:
|
|
case ARM::VADDHNv2i32:
|
|
case ARM::VADDHNv4i16:
|
|
case ARM::VADDHNv8i8:
|
|
case ARM::VADDLsv2i64:
|
|
case ARM::VADDLsv4i32:
|
|
case ARM::VADDLsv8i16:
|
|
case ARM::VADDLuv2i64:
|
|
case ARM::VADDLuv4i32:
|
|
case ARM::VADDLuv8i16:
|
|
case ARM::VADDWsv2i64:
|
|
case ARM::VADDWsv4i32:
|
|
case ARM::VADDWsv8i16:
|
|
case ARM::VADDWuv2i64:
|
|
case ARM::VADDWuv4i32:
|
|
case ARM::VADDWuv8i16:
|
|
case ARM::VADDv16i8:
|
|
case ARM::VADDv1i64:
|
|
case ARM::VADDv2i32:
|
|
case ARM::VADDv2i64:
|
|
case ARM::VADDv4i16:
|
|
case ARM::VADDv4i32:
|
|
case ARM::VADDv8i16:
|
|
case ARM::VADDv8i8:
|
|
case ARM::VCEQv16i8:
|
|
case ARM::VCEQv2i32:
|
|
case ARM::VCEQv4i16:
|
|
case ARM::VCEQv4i32:
|
|
case ARM::VCEQv8i16:
|
|
case ARM::VCEQv8i8:
|
|
case ARM::VCGEsv16i8:
|
|
case ARM::VCGEsv2i32:
|
|
case ARM::VCGEsv4i16:
|
|
case ARM::VCGEsv4i32:
|
|
case ARM::VCGEsv8i16:
|
|
case ARM::VCGEsv8i8:
|
|
case ARM::VCGEuv16i8:
|
|
case ARM::VCGEuv2i32:
|
|
case ARM::VCGEuv4i16:
|
|
case ARM::VCGEuv4i32:
|
|
case ARM::VCGEuv8i16:
|
|
case ARM::VCGEuv8i8:
|
|
case ARM::VCGTsv16i8:
|
|
case ARM::VCGTsv2i32:
|
|
case ARM::VCGTsv4i16:
|
|
case ARM::VCGTsv4i32:
|
|
case ARM::VCGTsv8i16:
|
|
case ARM::VCGTsv8i8:
|
|
case ARM::VCGTuv16i8:
|
|
case ARM::VCGTuv2i32:
|
|
case ARM::VCGTuv4i16:
|
|
case ARM::VCGTuv4i32:
|
|
case ARM::VCGTuv8i16:
|
|
case ARM::VCGTuv8i8:
|
|
case ARM::VHADDsv16i8:
|
|
case ARM::VHADDsv2i32:
|
|
case ARM::VHADDsv4i16:
|
|
case ARM::VHADDsv4i32:
|
|
case ARM::VHADDsv8i16:
|
|
case ARM::VHADDsv8i8:
|
|
case ARM::VHADDuv16i8:
|
|
case ARM::VHADDuv2i32:
|
|
case ARM::VHADDuv4i16:
|
|
case ARM::VHADDuv4i32:
|
|
case ARM::VHADDuv8i16:
|
|
case ARM::VHADDuv8i8:
|
|
case ARM::VHSUBsv16i8:
|
|
case ARM::VHSUBsv2i32:
|
|
case ARM::VHSUBsv4i16:
|
|
case ARM::VHSUBsv4i32:
|
|
case ARM::VHSUBsv8i16:
|
|
case ARM::VHSUBsv8i8:
|
|
case ARM::VHSUBuv16i8:
|
|
case ARM::VHSUBuv2i32:
|
|
case ARM::VHSUBuv4i16:
|
|
case ARM::VHSUBuv4i32:
|
|
case ARM::VHSUBuv8i16:
|
|
case ARM::VHSUBuv8i8:
|
|
case ARM::VMAXsv16i8:
|
|
case ARM::VMAXsv2i32:
|
|
case ARM::VMAXsv4i16:
|
|
case ARM::VMAXsv4i32:
|
|
case ARM::VMAXsv8i16:
|
|
case ARM::VMAXsv8i8:
|
|
case ARM::VMAXuv16i8:
|
|
case ARM::VMAXuv2i32:
|
|
case ARM::VMAXuv4i16:
|
|
case ARM::VMAXuv4i32:
|
|
case ARM::VMAXuv8i16:
|
|
case ARM::VMAXuv8i8:
|
|
case ARM::VMINsv16i8:
|
|
case ARM::VMINsv2i32:
|
|
case ARM::VMINsv4i16:
|
|
case ARM::VMINsv4i32:
|
|
case ARM::VMINsv8i16:
|
|
case ARM::VMINsv8i8:
|
|
case ARM::VMINuv16i8:
|
|
case ARM::VMINuv2i32:
|
|
case ARM::VMINuv4i16:
|
|
case ARM::VMINuv4i32:
|
|
case ARM::VMINuv8i16:
|
|
case ARM::VMINuv8i8:
|
|
case ARM::VMULLsv2i64:
|
|
case ARM::VMULLsv4i32:
|
|
case ARM::VMULLsv8i16:
|
|
case ARM::VMULLuv2i64:
|
|
case ARM::VMULLuv4i32:
|
|
case ARM::VMULLuv8i16:
|
|
case ARM::VMULv16i8:
|
|
case ARM::VMULv2i32:
|
|
case ARM::VMULv4i16:
|
|
case ARM::VMULv4i32:
|
|
case ARM::VMULv8i16:
|
|
case ARM::VMULv8i8:
|
|
case ARM::VPADDi16:
|
|
case ARM::VPADDi32:
|
|
case ARM::VPADDi8:
|
|
case ARM::VPMAXs16:
|
|
case ARM::VPMAXs32:
|
|
case ARM::VPMAXs8:
|
|
case ARM::VPMAXu16:
|
|
case ARM::VPMAXu32:
|
|
case ARM::VPMAXu8:
|
|
case ARM::VPMINs16:
|
|
case ARM::VPMINs32:
|
|
case ARM::VPMINs8:
|
|
case ARM::VPMINu16:
|
|
case ARM::VPMINu32:
|
|
case ARM::VPMINu8:
|
|
case ARM::VQADDsv16i8:
|
|
case ARM::VQADDsv1i64:
|
|
case ARM::VQADDsv2i32:
|
|
case ARM::VQADDsv2i64:
|
|
case ARM::VQADDsv4i16:
|
|
case ARM::VQADDsv4i32:
|
|
case ARM::VQADDsv8i16:
|
|
case ARM::VQADDsv8i8:
|
|
case ARM::VQADDuv16i8:
|
|
case ARM::VQADDuv1i64:
|
|
case ARM::VQADDuv2i32:
|
|
case ARM::VQADDuv2i64:
|
|
case ARM::VQADDuv4i16:
|
|
case ARM::VQADDuv4i32:
|
|
case ARM::VQADDuv8i16:
|
|
case ARM::VQADDuv8i8:
|
|
case ARM::VQDMULHv2i32:
|
|
case ARM::VQDMULHv4i16:
|
|
case ARM::VQDMULHv4i32:
|
|
case ARM::VQDMULHv8i16:
|
|
case ARM::VQDMULLv2i64:
|
|
case ARM::VQDMULLv4i32:
|
|
case ARM::VQRDMULHv2i32:
|
|
case ARM::VQRDMULHv4i16:
|
|
case ARM::VQRDMULHv4i32:
|
|
case ARM::VQRDMULHv8i16:
|
|
case ARM::VQRSHLsv16i8:
|
|
case ARM::VQRSHLsv1i64:
|
|
case ARM::VQRSHLsv2i32:
|
|
case ARM::VQRSHLsv2i64:
|
|
case ARM::VQRSHLsv4i16:
|
|
case ARM::VQRSHLsv4i32:
|
|
case ARM::VQRSHLsv8i16:
|
|
case ARM::VQRSHLsv8i8:
|
|
case ARM::VQRSHLuv16i8:
|
|
case ARM::VQRSHLuv1i64:
|
|
case ARM::VQRSHLuv2i32:
|
|
case ARM::VQRSHLuv2i64:
|
|
case ARM::VQRSHLuv4i16:
|
|
case ARM::VQRSHLuv4i32:
|
|
case ARM::VQRSHLuv8i16:
|
|
case ARM::VQRSHLuv8i8:
|
|
case ARM::VQRSHRNsv2i32:
|
|
case ARM::VQRSHRNsv4i16:
|
|
case ARM::VQRSHRNsv8i8:
|
|
case ARM::VQRSHRNuv2i32:
|
|
case ARM::VQRSHRNuv4i16:
|
|
case ARM::VQRSHRNuv8i8:
|
|
case ARM::VQRSHRUNv2i32:
|
|
case ARM::VQRSHRUNv4i16:
|
|
case ARM::VQRSHRUNv8i8:
|
|
case ARM::VQSHLsiv16i8:
|
|
case ARM::VQSHLsiv1i64:
|
|
case ARM::VQSHLsiv2i32:
|
|
case ARM::VQSHLsiv2i64:
|
|
case ARM::VQSHLsiv4i16:
|
|
case ARM::VQSHLsiv4i32:
|
|
case ARM::VQSHLsiv8i16:
|
|
case ARM::VQSHLsiv8i8:
|
|
case ARM::VQSHLsuv16i8:
|
|
case ARM::VQSHLsuv1i64:
|
|
case ARM::VQSHLsuv2i32:
|
|
case ARM::VQSHLsuv2i64:
|
|
case ARM::VQSHLsuv4i16:
|
|
case ARM::VQSHLsuv4i32:
|
|
case ARM::VQSHLsuv8i16:
|
|
case ARM::VQSHLsuv8i8:
|
|
case ARM::VQSHLsv16i8:
|
|
case ARM::VQSHLsv1i64:
|
|
case ARM::VQSHLsv2i32:
|
|
case ARM::VQSHLsv2i64:
|
|
case ARM::VQSHLsv4i16:
|
|
case ARM::VQSHLsv4i32:
|
|
case ARM::VQSHLsv8i16:
|
|
case ARM::VQSHLsv8i8:
|
|
case ARM::VQSHLuiv16i8:
|
|
case ARM::VQSHLuiv1i64:
|
|
case ARM::VQSHLuiv2i32:
|
|
case ARM::VQSHLuiv2i64:
|
|
case ARM::VQSHLuiv4i16:
|
|
case ARM::VQSHLuiv4i32:
|
|
case ARM::VQSHLuiv8i16:
|
|
case ARM::VQSHLuiv8i8:
|
|
case ARM::VQSHLuv16i8:
|
|
case ARM::VQSHLuv1i64:
|
|
case ARM::VQSHLuv2i32:
|
|
case ARM::VQSHLuv2i64:
|
|
case ARM::VQSHLuv4i16:
|
|
case ARM::VQSHLuv4i32:
|
|
case ARM::VQSHLuv8i16:
|
|
case ARM::VQSHLuv8i8:
|
|
case ARM::VQSHRNsv2i32:
|
|
case ARM::VQSHRNsv4i16:
|
|
case ARM::VQSHRNsv8i8:
|
|
case ARM::VQSHRNuv2i32:
|
|
case ARM::VQSHRNuv4i16:
|
|
case ARM::VQSHRNuv8i8:
|
|
case ARM::VQSHRUNv2i32:
|
|
case ARM::VQSHRUNv4i16:
|
|
case ARM::VQSHRUNv8i8:
|
|
case ARM::VQSUBsv16i8:
|
|
case ARM::VQSUBsv1i64:
|
|
case ARM::VQSUBsv2i32:
|
|
case ARM::VQSUBsv2i64:
|
|
case ARM::VQSUBsv4i16:
|
|
case ARM::VQSUBsv4i32:
|
|
case ARM::VQSUBsv8i16:
|
|
case ARM::VQSUBsv8i8:
|
|
case ARM::VQSUBuv16i8:
|
|
case ARM::VQSUBuv1i64:
|
|
case ARM::VQSUBuv2i32:
|
|
case ARM::VQSUBuv2i64:
|
|
case ARM::VQSUBuv4i16:
|
|
case ARM::VQSUBuv4i32:
|
|
case ARM::VQSUBuv8i16:
|
|
case ARM::VQSUBuv8i8:
|
|
case ARM::VRADDHNv2i32:
|
|
case ARM::VRADDHNv4i16:
|
|
case ARM::VRADDHNv8i8:
|
|
case ARM::VRHADDsv16i8:
|
|
case ARM::VRHADDsv2i32:
|
|
case ARM::VRHADDsv4i16:
|
|
case ARM::VRHADDsv4i32:
|
|
case ARM::VRHADDsv8i16:
|
|
case ARM::VRHADDsv8i8:
|
|
case ARM::VRHADDuv16i8:
|
|
case ARM::VRHADDuv2i32:
|
|
case ARM::VRHADDuv4i16:
|
|
case ARM::VRHADDuv4i32:
|
|
case ARM::VRHADDuv8i16:
|
|
case ARM::VRHADDuv8i8:
|
|
case ARM::VRSHLsv16i8:
|
|
case ARM::VRSHLsv1i64:
|
|
case ARM::VRSHLsv2i32:
|
|
case ARM::VRSHLsv2i64:
|
|
case ARM::VRSHLsv4i16:
|
|
case ARM::VRSHLsv4i32:
|
|
case ARM::VRSHLsv8i16:
|
|
case ARM::VRSHLsv8i8:
|
|
case ARM::VRSHLuv16i8:
|
|
case ARM::VRSHLuv1i64:
|
|
case ARM::VRSHLuv2i32:
|
|
case ARM::VRSHLuv2i64:
|
|
case ARM::VRSHLuv4i16:
|
|
case ARM::VRSHLuv4i32:
|
|
case ARM::VRSHLuv8i16:
|
|
case ARM::VRSHLuv8i8:
|
|
case ARM::VRSHRNv2i32:
|
|
case ARM::VRSHRNv4i16:
|
|
case ARM::VRSHRNv8i8:
|
|
case ARM::VRSHRsv16i8:
|
|
case ARM::VRSHRsv1i64:
|
|
case ARM::VRSHRsv2i32:
|
|
case ARM::VRSHRsv2i64:
|
|
case ARM::VRSHRsv4i16:
|
|
case ARM::VRSHRsv4i32:
|
|
case ARM::VRSHRsv8i16:
|
|
case ARM::VRSHRsv8i8:
|
|
case ARM::VRSHRuv16i8:
|
|
case ARM::VRSHRuv1i64:
|
|
case ARM::VRSHRuv2i32:
|
|
case ARM::VRSHRuv2i64:
|
|
case ARM::VRSHRuv4i16:
|
|
case ARM::VRSHRuv4i32:
|
|
case ARM::VRSHRuv8i16:
|
|
case ARM::VRSHRuv8i8:
|
|
case ARM::VRSUBHNv2i32:
|
|
case ARM::VRSUBHNv4i16:
|
|
case ARM::VRSUBHNv8i8:
|
|
case ARM::VSHLLi16:
|
|
case ARM::VSHLLi32:
|
|
case ARM::VSHLLi8:
|
|
case ARM::VSHLLsv2i64:
|
|
case ARM::VSHLLsv4i32:
|
|
case ARM::VSHLLsv8i16:
|
|
case ARM::VSHLLuv2i64:
|
|
case ARM::VSHLLuv4i32:
|
|
case ARM::VSHLLuv8i16:
|
|
case ARM::VSHLiv16i8:
|
|
case ARM::VSHLiv1i64:
|
|
case ARM::VSHLiv2i32:
|
|
case ARM::VSHLiv2i64:
|
|
case ARM::VSHLiv4i16:
|
|
case ARM::VSHLiv4i32:
|
|
case ARM::VSHLiv8i16:
|
|
case ARM::VSHLiv8i8:
|
|
case ARM::VSHLsv16i8:
|
|
case ARM::VSHLsv1i64:
|
|
case ARM::VSHLsv2i32:
|
|
case ARM::VSHLsv2i64:
|
|
case ARM::VSHLsv4i16:
|
|
case ARM::VSHLsv4i32:
|
|
case ARM::VSHLsv8i16:
|
|
case ARM::VSHLsv8i8:
|
|
case ARM::VSHLuv16i8:
|
|
case ARM::VSHLuv1i64:
|
|
case ARM::VSHLuv2i32:
|
|
case ARM::VSHLuv2i64:
|
|
case ARM::VSHLuv4i16:
|
|
case ARM::VSHLuv4i32:
|
|
case ARM::VSHLuv8i16:
|
|
case ARM::VSHLuv8i8:
|
|
case ARM::VSHRNv2i32:
|
|
case ARM::VSHRNv4i16:
|
|
case ARM::VSHRNv8i8:
|
|
case ARM::VSHRsv16i8:
|
|
case ARM::VSHRsv1i64:
|
|
case ARM::VSHRsv2i32:
|
|
case ARM::VSHRsv2i64:
|
|
case ARM::VSHRsv4i16:
|
|
case ARM::VSHRsv4i32:
|
|
case ARM::VSHRsv8i16:
|
|
case ARM::VSHRsv8i8:
|
|
case ARM::VSHRuv16i8:
|
|
case ARM::VSHRuv1i64:
|
|
case ARM::VSHRuv2i32:
|
|
case ARM::VSHRuv2i64:
|
|
case ARM::VSHRuv4i16:
|
|
case ARM::VSHRuv4i32:
|
|
case ARM::VSHRuv8i16:
|
|
case ARM::VSHRuv8i8:
|
|
case ARM::VSUBHNv2i32:
|
|
case ARM::VSUBHNv4i16:
|
|
case ARM::VSUBHNv8i8:
|
|
case ARM::VSUBLsv2i64:
|
|
case ARM::VSUBLsv4i32:
|
|
case ARM::VSUBLsv8i16:
|
|
case ARM::VSUBLuv2i64:
|
|
case ARM::VSUBLuv4i32:
|
|
case ARM::VSUBLuv8i16:
|
|
case ARM::VSUBWsv2i64:
|
|
case ARM::VSUBWsv4i32:
|
|
case ARM::VSUBWsv8i16:
|
|
case ARM::VSUBWuv2i64:
|
|
case ARM::VSUBWuv4i32:
|
|
case ARM::VSUBWuv8i16:
|
|
case ARM::VSUBv16i8:
|
|
case ARM::VSUBv1i64:
|
|
case ARM::VSUBv2i32:
|
|
case ARM::VSUBv2i64:
|
|
case ARM::VSUBv4i16:
|
|
case ARM::VSUBv4i32:
|
|
case ARM::VSUBv8i16:
|
|
case ARM::VSUBv8i8:
|
|
case ARM::VTSTv16i8:
|
|
case ARM::VTSTv2i32:
|
|
case ARM::VTSTv4i16:
|
|
case ARM::VTSTv4i32:
|
|
case ARM::VTSTv8i16:
|
|
case ARM::VTSTv8i8:
|
|
case ARM::t2ADCSri:
|
|
case ARM::t2ADCSrr:
|
|
case ARM::t2LDRDpci:
|
|
case ARM::t2MOVTi16:
|
|
case ARM::t2SBCSri:
|
|
case ARM::t2SBCSrr:
|
|
case ARM::t2SUBrSPi12_:
|
|
case ARM::t2SUBrSPi_:
|
|
case ARM::tADDhirr:
|
|
case ARM::tMOVCCi:
|
|
case ARM::tMOVCCr: printOperand(MI, 2); break;
|
|
case ARM::ADCSSrs:
|
|
case ARM::MOVCCs:
|
|
case ARM::RSCSrs:
|
|
case ARM::SBCSSrs: printSORegOperand(MI, 2); break;
|
|
case ARM::BFC:
|
|
case ARM::t2BFC: printBitfieldInvMaskImmOperand(MI, 2); break;
|
|
case ARM::CLZ:
|
|
case ARM::CMNrr:
|
|
case ARM::CMNzrr:
|
|
case ARM::CMPrr:
|
|
case ARM::CMPzrr:
|
|
case ARM::MOVi16:
|
|
case ARM::REV:
|
|
case ARM::REV16:
|
|
case ARM::REVSH:
|
|
case ARM::SXTBr:
|
|
case ARM::SXTHr:
|
|
case ARM::TEQrr:
|
|
case ARM::TSTrr:
|
|
case ARM::UXTB16r:
|
|
case ARM::UXTBr:
|
|
case ARM::UXTHr:
|
|
case ARM::VCNTd:
|
|
case ARM::VCNTq:
|
|
case ARM::VDUP16d:
|
|
case ARM::VDUP16q:
|
|
case ARM::VDUP32d:
|
|
case ARM::VDUP32q:
|
|
case ARM::VDUP8d:
|
|
case ARM::VDUP8q:
|
|
case ARM::VDUPfd:
|
|
case ARM::VDUPfq:
|
|
case ARM::VMOVDneon:
|
|
case ARM::VMOVQ:
|
|
case ARM::VMOVRS:
|
|
case ARM::VMOVSR:
|
|
case ARM::VMVNd:
|
|
case ARM::VMVNq:
|
|
case ARM::VREV16d8:
|
|
case ARM::VREV16q8:
|
|
case ARM::VREV32d16:
|
|
case ARM::VREV32d8:
|
|
case ARM::VREV32q16:
|
|
case ARM::VREV32q8:
|
|
case ARM::VREV64d16:
|
|
case ARM::VREV64d32:
|
|
case ARM::VREV64d8:
|
|
case ARM::VREV64df:
|
|
case ARM::VREV64q16:
|
|
case ARM::VREV64q32:
|
|
case ARM::VREV64q8:
|
|
case ARM::VREV64qf:
|
|
case ARM::VTRNd16:
|
|
case ARM::VTRNd32:
|
|
case ARM::VTRNd8:
|
|
case ARM::VTRNq16:
|
|
case ARM::VTRNq32:
|
|
case ARM::VTRNq8:
|
|
case ARM::VUZPd16:
|
|
case ARM::VUZPd32:
|
|
case ARM::VUZPd8:
|
|
case ARM::VUZPq16:
|
|
case ARM::VUZPq32:
|
|
case ARM::VUZPq8:
|
|
case ARM::VZIPd16:
|
|
case ARM::VZIPd32:
|
|
case ARM::VZIPd8:
|
|
case ARM::VZIPq16:
|
|
case ARM::VZIPq32:
|
|
case ARM::VZIPq8:
|
|
case ARM::t2CLZ:
|
|
case ARM::t2MOVi16:
|
|
case ARM::tCMN:
|
|
case ARM::tCMNz:
|
|
case ARM::tCMPhir:
|
|
case ARM::tCMPi8:
|
|
case ARM::tCMPr:
|
|
case ARM::tCMPzhir:
|
|
case ARM::tCMPzi8:
|
|
case ARM::tCMPzr:
|
|
case ARM::tLDRcp:
|
|
case ARM::tREV:
|
|
case ARM::tREV16:
|
|
case ARM::tREVSH:
|
|
case ARM::tSXTB:
|
|
case ARM::tSXTH:
|
|
case ARM::tTST:
|
|
case ARM::tUXTB:
|
|
case ARM::tUXTH: printOperand(MI, 1); break;
|
|
case ARM::CMNri:
|
|
case ARM::CMNzri:
|
|
case ARM::CMPri:
|
|
case ARM::CMPzri:
|
|
case ARM::TEQri:
|
|
case ARM::TSTri: printSOImmOperand(MI, 1); break;
|
|
case ARM::CMNrs:
|
|
case ARM::CMNzrs:
|
|
case ARM::CMPrs:
|
|
case ARM::CMPzrs:
|
|
case ARM::TEQrs:
|
|
case ARM::TSTrs: printSORegOperand(MI, 1); break;
|
|
case ARM::LDR:
|
|
case ARM::LDRB:
|
|
case ARM::LDRcp:
|
|
case ARM::STR:
|
|
case ARM::STRB: printAddrMode2Operand(MI, 1); break;
|
|
case ARM::LDRD:
|
|
case ARM::STRD: printAddrMode3Operand(MI, 2); break;
|
|
case ARM::LDRH:
|
|
case ARM::LDRSB:
|
|
case ARM::LDRSH:
|
|
case ARM::STRH: printAddrMode3Operand(MI, 1); break;
|
|
case ARM::MOVi2pieces: printSOImm2PartOperand(MI, 1); break;
|
|
case ARM::VABALsv2i64:
|
|
case ARM::VABALsv4i32:
|
|
case ARM::VABALsv8i16:
|
|
case ARM::VABALuv2i64:
|
|
case ARM::VABALuv4i32:
|
|
case ARM::VABALuv8i16:
|
|
case ARM::VABAsv16i8:
|
|
case ARM::VABAsv2i32:
|
|
case ARM::VABAsv4i16:
|
|
case ARM::VABAsv4i32:
|
|
case ARM::VABAsv8i16:
|
|
case ARM::VABAsv8i8:
|
|
case ARM::VABAuv16i8:
|
|
case ARM::VABAuv2i32:
|
|
case ARM::VABAuv4i16:
|
|
case ARM::VABAuv4i32:
|
|
case ARM::VABAuv8i16:
|
|
case ARM::VABAuv8i8:
|
|
case ARM::VMLALsv2i64:
|
|
case ARM::VMLALsv4i32:
|
|
case ARM::VMLALsv8i16:
|
|
case ARM::VMLALuv2i64:
|
|
case ARM::VMLALuv4i32:
|
|
case ARM::VMLALuv8i16:
|
|
case ARM::VMLAv16i8:
|
|
case ARM::VMLAv2i32:
|
|
case ARM::VMLAv4i16:
|
|
case ARM::VMLAv4i32:
|
|
case ARM::VMLAv8i16:
|
|
case ARM::VMLAv8i8:
|
|
case ARM::VMLSLsv2i64:
|
|
case ARM::VMLSLsv4i32:
|
|
case ARM::VMLSLsv8i16:
|
|
case ARM::VMLSLuv2i64:
|
|
case ARM::VMLSLuv4i32:
|
|
case ARM::VMLSLuv8i16:
|
|
case ARM::VMLSv16i8:
|
|
case ARM::VMLSv2i32:
|
|
case ARM::VMLSv4i16:
|
|
case ARM::VMLSv4i32:
|
|
case ARM::VMLSv8i16:
|
|
case ARM::VMLSv8i8:
|
|
case ARM::VQDMLALv2i64:
|
|
case ARM::VQDMLALv4i32:
|
|
case ARM::VQDMLSLv2i64:
|
|
case ARM::VQDMLSLv4i32:
|
|
case ARM::VRSRAsv16i8:
|
|
case ARM::VRSRAsv1i64:
|
|
case ARM::VRSRAsv2i32:
|
|
case ARM::VRSRAsv2i64:
|
|
case ARM::VRSRAsv4i16:
|
|
case ARM::VRSRAsv4i32:
|
|
case ARM::VRSRAsv8i16:
|
|
case ARM::VRSRAsv8i8:
|
|
case ARM::VRSRAuv16i8:
|
|
case ARM::VRSRAuv1i64:
|
|
case ARM::VRSRAuv2i32:
|
|
case ARM::VRSRAuv2i64:
|
|
case ARM::VRSRAuv4i16:
|
|
case ARM::VRSRAuv4i32:
|
|
case ARM::VRSRAuv8i16:
|
|
case ARM::VRSRAuv8i8:
|
|
case ARM::VSRAsv16i8:
|
|
case ARM::VSRAsv1i64:
|
|
case ARM::VSRAsv2i32:
|
|
case ARM::VSRAsv2i64:
|
|
case ARM::VSRAsv4i16:
|
|
case ARM::VSRAsv4i32:
|
|
case ARM::VSRAsv8i16:
|
|
case ARM::VSRAsv8i8:
|
|
case ARM::VSRAuv16i8:
|
|
case ARM::VSRAuv1i64:
|
|
case ARM::VSRAuv2i32:
|
|
case ARM::VSRAuv2i64:
|
|
case ARM::VSRAuv4i16:
|
|
case ARM::VSRAuv4i32:
|
|
case ARM::VSRAuv8i16:
|
|
case ARM::VSRAuv8i8:
|
|
case ARM::tADDi3:
|
|
case ARM::tADDrr:
|
|
case ARM::tASRri:
|
|
case ARM::tLSLri:
|
|
case ARM::tLSRri:
|
|
case ARM::tSUBi3:
|
|
case ARM::tSUBrr: printOperand(MI, 3); break;
|
|
case ARM::VDUPfdf:
|
|
case ARM::VDUPfqf: printOperand(MI, 1, "lane"); break;
|
|
case ARM::VLDRD:
|
|
case ARM::VLDRS:
|
|
case ARM::VSTRD:
|
|
case ARM::VSTRS: printAddrMode5Operand(MI, 1); break;
|
|
case ARM::t2ADCSrs:
|
|
case ARM::t2SBCSrs:
|
|
case ARM::t2SUBrSPs_: printT2SOOperand(MI, 2); break;
|
|
case ARM::t2LDRBi8:
|
|
case ARM::t2LDRHi8:
|
|
case ARM::t2LDRSBi8:
|
|
case ARM::t2LDRSHi8:
|
|
case ARM::t2LDRi8:
|
|
case ARM::t2STRBi8:
|
|
case ARM::t2STRHi8:
|
|
case ARM::t2STRi8: printT2AddrModeImm8Operand(MI, 1); break;
|
|
case ARM::t2LDRDi8:
|
|
case ARM::t2STRDi8: printT2AddrModeImm8s4Operand(MI, 2); break;
|
|
case ARM::tADDrSPi: printThumbS4ImmOperand(MI, 2); break;
|
|
case ARM::tLDR:
|
|
case ARM::tSTR: printThumbAddrModeS4Operand(MI, 1); break;
|
|
case ARM::tLDRB:
|
|
case ARM::tSTRB: printThumbAddrModeS1Operand(MI, 1); break;
|
|
case ARM::tLDRH:
|
|
case ARM::tSTRH: printThumbAddrModeS2Operand(MI, 1); break;
|
|
case ARM::tLDRSB:
|
|
case ARM::tLDRSH: printThumbAddrModeRROperand(MI, 1); break;
|
|
case ARM::tLDRspi:
|
|
case ARM::tRestore:
|
|
case ARM::tSTRspi:
|
|
case ARM::tSpill: printThumbAddrModeSPOperand(MI, 1); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::ADCrr:
|
|
case ARM::ADDrr:
|
|
case ARM::ANDrr:
|
|
case ARM::BICrr:
|
|
case ARM::Bcc:
|
|
case ARM::EORrr:
|
|
case ARM::MOVr:
|
|
case ARM::MUL:
|
|
case ARM::MVNr:
|
|
case ARM::ORRrr:
|
|
case ARM::SBCrr:
|
|
case ARM::SUBrr:
|
|
case ARM::VABSv16i8:
|
|
case ARM::VABSv2i32:
|
|
case ARM::VABSv4i16:
|
|
case ARM::VABSv4i32:
|
|
case ARM::VABSv8i16:
|
|
case ARM::VABSv8i8:
|
|
case ARM::VCLSv16i8:
|
|
case ARM::VCLSv2i32:
|
|
case ARM::VCLSv4i16:
|
|
case ARM::VCLSv4i32:
|
|
case ARM::VCLSv8i16:
|
|
case ARM::VCLSv8i8:
|
|
case ARM::VCLZv16i8:
|
|
case ARM::VCLZv2i32:
|
|
case ARM::VCLZv4i16:
|
|
case ARM::VCLZv4i32:
|
|
case ARM::VCLZv8i16:
|
|
case ARM::VCLZv8i8:
|
|
case ARM::VMOVLsv2i64:
|
|
case ARM::VMOVLsv4i32:
|
|
case ARM::VMOVLsv8i16:
|
|
case ARM::VMOVLuv2i64:
|
|
case ARM::VMOVLuv4i32:
|
|
case ARM::VMOVLuv8i16:
|
|
case ARM::VMOVNv2i32:
|
|
case ARM::VMOVNv4i16:
|
|
case ARM::VMOVNv8i8:
|
|
case ARM::VNEGs16d:
|
|
case ARM::VNEGs16q:
|
|
case ARM::VNEGs32d:
|
|
case ARM::VNEGs32q:
|
|
case ARM::VNEGs8d:
|
|
case ARM::VNEGs8q:
|
|
case ARM::VPADALsv16i8:
|
|
case ARM::VPADALsv2i32:
|
|
case ARM::VPADALsv4i16:
|
|
case ARM::VPADALsv4i32:
|
|
case ARM::VPADALsv8i16:
|
|
case ARM::VPADALsv8i8:
|
|
case ARM::VPADALuv16i8:
|
|
case ARM::VPADALuv2i32:
|
|
case ARM::VPADALuv4i16:
|
|
case ARM::VPADALuv4i32:
|
|
case ARM::VPADALuv8i16:
|
|
case ARM::VPADALuv8i8:
|
|
case ARM::VPADDLsv16i8:
|
|
case ARM::VPADDLsv2i32:
|
|
case ARM::VPADDLsv4i16:
|
|
case ARM::VPADDLsv4i32:
|
|
case ARM::VPADDLsv8i16:
|
|
case ARM::VPADDLsv8i8:
|
|
case ARM::VPADDLuv16i8:
|
|
case ARM::VPADDLuv2i32:
|
|
case ARM::VPADDLuv4i16:
|
|
case ARM::VPADDLuv4i32:
|
|
case ARM::VPADDLuv8i16:
|
|
case ARM::VPADDLuv8i8:
|
|
case ARM::VQABSv16i8:
|
|
case ARM::VQABSv2i32:
|
|
case ARM::VQABSv4i16:
|
|
case ARM::VQABSv4i32:
|
|
case ARM::VQABSv8i16:
|
|
case ARM::VQABSv8i8:
|
|
case ARM::VQMOVNsuv2i32:
|
|
case ARM::VQMOVNsuv4i16:
|
|
case ARM::VQMOVNsuv8i8:
|
|
case ARM::VQMOVNsv2i32:
|
|
case ARM::VQMOVNsv4i16:
|
|
case ARM::VQMOVNsv8i8:
|
|
case ARM::VQMOVNuv2i32:
|
|
case ARM::VQMOVNuv4i16:
|
|
case ARM::VQMOVNuv8i8:
|
|
case ARM::VQNEGv16i8:
|
|
case ARM::VQNEGv2i32:
|
|
case ARM::VQNEGv4i16:
|
|
case ARM::VQNEGv4i32:
|
|
case ARM::VQNEGv8i16:
|
|
case ARM::VQNEGv8i8:
|
|
case ARM::VRECPEd:
|
|
case ARM::VRECPEq:
|
|
case ARM::VRSQRTEd:
|
|
case ARM::VRSQRTEq:
|
|
case ARM::t2LEApcrel:
|
|
case ARM::tADDrSP:
|
|
case ARM::tADDspr:
|
|
case ARM::tADDspr_:
|
|
case ARM::tANDsp:
|
|
case ARM::tBcc:
|
|
case ARM::tCBNZ:
|
|
case ARM::tCBZ:
|
|
case ARM::tMOVSr:
|
|
case ARM::tMOVgpr2gpr:
|
|
case ARM::tMOVgpr2tgpr:
|
|
case ARM::tMOVr:
|
|
case ARM::tMOVtgpr2gpr:
|
|
return;
|
|
break;
|
|
case ARM::ADDSri:
|
|
case ARM::ADDSrr:
|
|
case ARM::ADDSrs:
|
|
case ARM::RSBSri:
|
|
case ARM::RSBSrs:
|
|
case ARM::SMMUL:
|
|
case ARM::SMULBB:
|
|
case ARM::SMULBT:
|
|
case ARM::SMULTB:
|
|
case ARM::SMULTT:
|
|
case ARM::SMULWB:
|
|
case ARM::SMULWT:
|
|
case ARM::SUBSri:
|
|
case ARM::SUBSrr:
|
|
case ARM::SUBSrs:
|
|
case ARM::SXTABrr:
|
|
case ARM::SXTAHrr:
|
|
case ARM::UXTABrr:
|
|
case ARM::UXTAHrr:
|
|
case ARM::VANDd:
|
|
case ARM::VANDq:
|
|
case ARM::VBICd:
|
|
case ARM::VBICq:
|
|
case ARM::VEORd:
|
|
case ARM::VEORq:
|
|
case ARM::VMOVDRR:
|
|
case ARM::VMOVRRD:
|
|
case ARM::VORNd:
|
|
case ARM::VORNq:
|
|
case ARM::VORRd:
|
|
case ARM::VORRq:
|
|
case ARM::t2ADCri:
|
|
case ARM::t2ADDrSPi12:
|
|
case ARM::t2ADDri12:
|
|
case ARM::t2ANDri:
|
|
case ARM::t2BICri:
|
|
case ARM::t2EORri:
|
|
case ARM::t2MUL:
|
|
case ARM::t2ORNri:
|
|
case ARM::t2ORNrr:
|
|
case ARM::t2ORNrs:
|
|
case ARM::t2ORRri:
|
|
case ARM::t2RSBSrs:
|
|
case ARM::t2RSBrs:
|
|
case ARM::t2SBCri:
|
|
case ARM::t2SMMUL:
|
|
case ARM::t2SMULBB:
|
|
case ARM::t2SMULBT:
|
|
case ARM::t2SMULTB:
|
|
case ARM::t2SMULTT:
|
|
case ARM::t2SMULWB:
|
|
case ARM::t2SMULWT:
|
|
case ARM::t2SUBrSPi12:
|
|
case ARM::t2SUBrSPs:
|
|
case ARM::t2SUBri12:
|
|
case ARM::t2SXTABrr:
|
|
case ARM::t2SXTAHrr:
|
|
case ARM::t2UXTABrr:
|
|
case ARM::t2UXTAHrr:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::ADDSri:
|
|
case ARM::RSBSri:
|
|
case ARM::SUBSri: printSOImmOperand(MI, 2); break;
|
|
case ARM::ADDSrr:
|
|
case ARM::SMMUL:
|
|
case ARM::SMULBB:
|
|
case ARM::SMULBT:
|
|
case ARM::SMULTB:
|
|
case ARM::SMULTT:
|
|
case ARM::SMULWB:
|
|
case ARM::SMULWT:
|
|
case ARM::SUBSrr:
|
|
case ARM::SXTABrr:
|
|
case ARM::SXTAHrr:
|
|
case ARM::UXTABrr:
|
|
case ARM::UXTAHrr:
|
|
case ARM::VANDd:
|
|
case ARM::VANDq:
|
|
case ARM::VBICd:
|
|
case ARM::VBICq:
|
|
case ARM::VEORd:
|
|
case ARM::VEORq:
|
|
case ARM::VMOVDRR:
|
|
case ARM::VMOVRRD:
|
|
case ARM::VORNd:
|
|
case ARM::VORNq:
|
|
case ARM::VORRd:
|
|
case ARM::VORRq:
|
|
case ARM::t2ADCri:
|
|
case ARM::t2ADDrSPi12:
|
|
case ARM::t2ADDri12:
|
|
case ARM::t2ANDri:
|
|
case ARM::t2BICri:
|
|
case ARM::t2EORri:
|
|
case ARM::t2MUL:
|
|
case ARM::t2ORNri:
|
|
case ARM::t2ORNrr:
|
|
case ARM::t2ORRri:
|
|
case ARM::t2SBCri:
|
|
case ARM::t2SMMUL:
|
|
case ARM::t2SMULBB:
|
|
case ARM::t2SMULBT:
|
|
case ARM::t2SMULTB:
|
|
case ARM::t2SMULTT:
|
|
case ARM::t2SMULWB:
|
|
case ARM::t2SMULWT:
|
|
case ARM::t2SUBrSPi12:
|
|
case ARM::t2SUBri12:
|
|
case ARM::t2SXTABrr:
|
|
case ARM::t2SXTAHrr:
|
|
case ARM::t2UXTABrr:
|
|
case ARM::t2UXTAHrr: printOperand(MI, 2); break;
|
|
case ARM::ADDSrs:
|
|
case ARM::RSBSrs:
|
|
case ARM::SUBSrs: printSORegOperand(MI, 2); break;
|
|
case ARM::t2ORNrs:
|
|
case ARM::t2RSBSrs:
|
|
case ARM::t2RSBrs:
|
|
case ARM::t2SUBrSPs: printT2SOOperand(MI, 2); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::BR_JTadd:
|
|
O << " \n";
|
|
printJTBlockOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::FCONSTD:
|
|
case ARM::FCONSTS:
|
|
case ARM::MOVrx:
|
|
case ARM::VABSD:
|
|
case ARM::VABSS:
|
|
case ARM::VABSfd:
|
|
case ARM::VABSfd_sfp:
|
|
case ARM::VABSfq:
|
|
case ARM::VCMPED:
|
|
case ARM::VCMPES:
|
|
case ARM::VCVTf2xsd:
|
|
case ARM::VCVTf2xsq:
|
|
case ARM::VCVTf2xud:
|
|
case ARM::VCVTf2xuq:
|
|
case ARM::VCVTxs2fd:
|
|
case ARM::VCVTxs2fq:
|
|
case ARM::VCVTxu2fd:
|
|
case ARM::VCVTxu2fq:
|
|
case ARM::VMOVD:
|
|
case ARM::VMOVDcc:
|
|
case ARM::VMOVS:
|
|
case ARM::VMOVScc:
|
|
case ARM::VNEGD:
|
|
case ARM::VNEGDcc:
|
|
case ARM::VNEGS:
|
|
case ARM::VNEGScc:
|
|
case ARM::VNEGf32d:
|
|
case ARM::VNEGf32d_sfp:
|
|
case ARM::VNEGf32q:
|
|
case ARM::VRECPEfd:
|
|
case ARM::VRECPEfq:
|
|
case ARM::VRSQRTEfd:
|
|
case ARM::VRSQRTEfq:
|
|
case ARM::VSQRTD:
|
|
case ARM::VSQRTS:
|
|
case ARM::t2CMNri:
|
|
case ARM::t2CMNrr:
|
|
case ARM::t2CMNrs:
|
|
case ARM::t2CMNzri:
|
|
case ARM::t2CMNzrr:
|
|
case ARM::t2CMNzrs:
|
|
case ARM::t2CMPri:
|
|
case ARM::t2CMPrr:
|
|
case ARM::t2CMPrs:
|
|
case ARM::t2CMPzri:
|
|
case ARM::t2CMPzrr:
|
|
case ARM::t2CMPzrs:
|
|
case ARM::t2LDRBi12:
|
|
case ARM::t2LDRBpci:
|
|
case ARM::t2LDRBs:
|
|
case ARM::t2LDRHi12:
|
|
case ARM::t2LDRHpci:
|
|
case ARM::t2LDRHs:
|
|
case ARM::t2LDRSBi12:
|
|
case ARM::t2LDRSBpci:
|
|
case ARM::t2LDRSBs:
|
|
case ARM::t2LDRSHi12:
|
|
case ARM::t2LDRSHpci:
|
|
case ARM::t2LDRSHs:
|
|
case ARM::t2LDRi12:
|
|
case ARM::t2LDRpci:
|
|
case ARM::t2LDRs:
|
|
case ARM::t2MOVCCi:
|
|
case ARM::t2MOVCCr:
|
|
case ARM::t2MOVsra_flag:
|
|
case ARM::t2MOVsrl_flag:
|
|
case ARM::t2MVNr:
|
|
case ARM::t2MVNs:
|
|
case ARM::t2REV:
|
|
case ARM::t2REV16:
|
|
case ARM::t2REVSH:
|
|
case ARM::t2STRBi12:
|
|
case ARM::t2STRBs:
|
|
case ARM::t2STRHi12:
|
|
case ARM::t2STRHs:
|
|
case ARM::t2STRi12:
|
|
case ARM::t2STRs:
|
|
case ARM::t2SXTBr:
|
|
case ARM::t2SXTHr:
|
|
case ARM::t2TEQri:
|
|
case ARM::t2TEQrr:
|
|
case ARM::t2TEQrs:
|
|
case ARM::t2TSTri:
|
|
case ARM::t2TSTrr:
|
|
case ARM::t2TSTrs:
|
|
case ARM::t2UXTB16r:
|
|
case ARM::t2UXTBr:
|
|
case ARM::t2UXTHr:
|
|
switch (MI->getOpcode()) {
|
|
case ARM::FCONSTD: printVFPf64ImmOperand(MI, 1); break;
|
|
case ARM::FCONSTS: printVFPf32ImmOperand(MI, 1); break;
|
|
case ARM::MOVrx: O << ", rrx"; break;
|
|
case ARM::VABSD:
|
|
case ARM::VABSS:
|
|
case ARM::VABSfd:
|
|
case ARM::VABSfd_sfp:
|
|
case ARM::VABSfq:
|
|
case ARM::VCMPED:
|
|
case ARM::VCMPES:
|
|
case ARM::VMOVD:
|
|
case ARM::VMOVS:
|
|
case ARM::VNEGD:
|
|
case ARM::VNEGS:
|
|
case ARM::VNEGf32d:
|
|
case ARM::VNEGf32d_sfp:
|
|
case ARM::VNEGf32q:
|
|
case ARM::VRECPEfd:
|
|
case ARM::VRECPEfq:
|
|
case ARM::VRSQRTEfd:
|
|
case ARM::VRSQRTEfq:
|
|
case ARM::VSQRTD:
|
|
case ARM::VSQRTS:
|
|
case ARM::t2CMNri:
|
|
case ARM::t2CMNrr:
|
|
case ARM::t2CMNzri:
|
|
case ARM::t2CMNzrr:
|
|
case ARM::t2CMPri:
|
|
case ARM::t2CMPrr:
|
|
case ARM::t2CMPzri:
|
|
case ARM::t2CMPzrr:
|
|
case ARM::t2LDRBpci:
|
|
case ARM::t2LDRHpci:
|
|
case ARM::t2LDRSBpci:
|
|
case ARM::t2LDRSHpci:
|
|
case ARM::t2LDRpci:
|
|
case ARM::t2MVNr:
|
|
case ARM::t2REV:
|
|
case ARM::t2REV16:
|
|
case ARM::t2REVSH:
|
|
case ARM::t2SXTBr:
|
|
case ARM::t2SXTHr:
|
|
case ARM::t2TEQri:
|
|
case ARM::t2TEQrr:
|
|
case ARM::t2TSTri:
|
|
case ARM::t2TSTrr:
|
|
case ARM::t2UXTB16r:
|
|
case ARM::t2UXTBr:
|
|
case ARM::t2UXTHr: printOperand(MI, 1); break;
|
|
case ARM::VCVTf2xsd:
|
|
case ARM::VCVTf2xsq:
|
|
case ARM::VCVTf2xud:
|
|
case ARM::VCVTf2xuq:
|
|
case ARM::VCVTxs2fd:
|
|
case ARM::VCVTxs2fq:
|
|
case ARM::VCVTxu2fd:
|
|
case ARM::VCVTxu2fq:
|
|
case ARM::VMOVDcc:
|
|
case ARM::VMOVScc:
|
|
case ARM::VNEGDcc:
|
|
case ARM::VNEGScc:
|
|
case ARM::t2MOVCCi:
|
|
case ARM::t2MOVCCr: printOperand(MI, 2); break;
|
|
case ARM::t2CMNrs:
|
|
case ARM::t2CMNzrs:
|
|
case ARM::t2CMPrs:
|
|
case ARM::t2CMPzrs:
|
|
case ARM::t2MVNs:
|
|
case ARM::t2TEQrs:
|
|
case ARM::t2TSTrs: printT2SOOperand(MI, 1); break;
|
|
case ARM::t2LDRBi12:
|
|
case ARM::t2LDRHi12:
|
|
case ARM::t2LDRSBi12:
|
|
case ARM::t2LDRSHi12:
|
|
case ARM::t2LDRi12:
|
|
case ARM::t2STRBi12:
|
|
case ARM::t2STRHi12:
|
|
case ARM::t2STRi12: printT2AddrModeImm12Operand(MI, 1); break;
|
|
case ARM::t2LDRBs:
|
|
case ARM::t2LDRHs:
|
|
case ARM::t2LDRSBs:
|
|
case ARM::t2LDRSHs:
|
|
case ARM::t2LDRs:
|
|
case ARM::t2STRBs:
|
|
case ARM::t2STRHs:
|
|
case ARM::t2STRs: printT2AddrModeSoRegOperand(MI, 1); break;
|
|
case ARM::t2MOVsra_flag:
|
|
case ARM::t2MOVsrl_flag: O << ", #1"; break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::LDRB_POST:
|
|
case ARM::LDRH_POST:
|
|
case ARM::LDRSB_POST:
|
|
case ARM::LDRSH_POST:
|
|
case ARM::LDR_POST:
|
|
case ARM::STRB_POST:
|
|
case ARM::STRH_POST:
|
|
case ARM::STR_POST:
|
|
case ARM::t2LDRB_POST:
|
|
case ARM::t2LDRH_POST:
|
|
case ARM::t2LDRSB_POST:
|
|
case ARM::t2LDRSH_POST:
|
|
case ARM::t2LDR_POST:
|
|
case ARM::t2STRB_POST:
|
|
case ARM::t2STRH_POST:
|
|
case ARM::t2STR_POST:
|
|
O << ", [";
|
|
printOperand(MI, 2);
|
|
O << "], ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::LDRB_POST:
|
|
case ARM::LDR_POST:
|
|
case ARM::STRB_POST:
|
|
case ARM::STR_POST: printAddrMode2OffsetOperand(MI, 3); break;
|
|
case ARM::LDRH_POST:
|
|
case ARM::LDRSB_POST:
|
|
case ARM::LDRSH_POST:
|
|
case ARM::STRH_POST: printAddrMode3OffsetOperand(MI, 3); break;
|
|
case ARM::t2LDRB_POST:
|
|
case ARM::t2LDRH_POST:
|
|
case ARM::t2LDRSB_POST:
|
|
case ARM::t2LDRSH_POST:
|
|
case ARM::t2LDR_POST:
|
|
case ARM::t2STRB_POST:
|
|
case ARM::t2STRH_POST:
|
|
case ARM::t2STR_POST: printT2AddrModeImm8OffsetOperand(MI, 3); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::LDRB_PRE:
|
|
case ARM::LDRH_PRE:
|
|
case ARM::LDRSB_PRE:
|
|
case ARM::LDRSH_PRE:
|
|
case ARM::LDR_PRE:
|
|
case ARM::t2LDRB_PRE:
|
|
case ARM::t2LDRH_PRE:
|
|
case ARM::t2LDRSB_PRE:
|
|
case ARM::t2LDRSH_PRE:
|
|
case ARM::t2LDR_PRE:
|
|
O << ", ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::LDRB_PRE:
|
|
case ARM::LDR_PRE: printAddrMode2Operand(MI, 2); break;
|
|
case ARM::LDRH_PRE:
|
|
case ARM::LDRSB_PRE:
|
|
case ARM::LDRSH_PRE: printAddrMode3Operand(MI, 2); break;
|
|
case ARM::t2LDRB_PRE:
|
|
case ARM::t2LDRH_PRE:
|
|
case ARM::t2LDRSB_PRE:
|
|
case ARM::t2LDRSH_PRE:
|
|
case ARM::t2LDR_PRE: printT2AddrModeImm8Operand(MI, 2); break;
|
|
}
|
|
O << '!';
|
|
return;
|
|
break;
|
|
case ARM::LDREX:
|
|
case ARM::LDREXB:
|
|
case ARM::LDREXH:
|
|
case ARM::t2LDREX:
|
|
case ARM::t2LDREXB:
|
|
case ARM::t2LDREXH:
|
|
O << ", [";
|
|
printOperand(MI, 1);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::LDREXD:
|
|
case ARM::STREX:
|
|
case ARM::STREXB:
|
|
case ARM::STREXH:
|
|
case ARM::t2LDREXD:
|
|
case ARM::t2STREX:
|
|
case ARM::t2STREXB:
|
|
case ARM::t2STREXH:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", [";
|
|
printOperand(MI, 2);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::MLA:
|
|
case ARM::SMLAL:
|
|
case ARM::SMULL:
|
|
case ARM::UMLAL:
|
|
case ARM::UMULL:
|
|
case ARM::VBSLd:
|
|
case ARM::VBSLq:
|
|
case ARM::VSLIv16i8:
|
|
case ARM::VSLIv1i64:
|
|
case ARM::VSLIv2i32:
|
|
case ARM::VSLIv2i64:
|
|
case ARM::VSLIv4i16:
|
|
case ARM::VSLIv4i32:
|
|
case ARM::VSLIv8i16:
|
|
case ARM::VSLIv8i8:
|
|
case ARM::VSRIv16i8:
|
|
case ARM::VSRIv1i64:
|
|
case ARM::VSRIv2i32:
|
|
case ARM::VSRIv2i64:
|
|
case ARM::VSRIv4i16:
|
|
case ARM::VSRIv4i32:
|
|
case ARM::VSRIv8i16:
|
|
case ARM::VSRIv8i8:
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
return;
|
|
break;
|
|
case ARM::MLS:
|
|
case ARM::PKHBT:
|
|
case ARM::PKHTB:
|
|
case ARM::SBFX:
|
|
case ARM::SMLABB:
|
|
case ARM::SMLABT:
|
|
case ARM::SMLATB:
|
|
case ARM::SMLATT:
|
|
case ARM::SMLAWB:
|
|
case ARM::SMLAWT:
|
|
case ARM::SMMLA:
|
|
case ARM::SMMLS:
|
|
case ARM::SXTABrr_rot:
|
|
case ARM::SXTAHrr_rot:
|
|
case ARM::UBFX:
|
|
case ARM::UMAAL:
|
|
case ARM::UXTABrr_rot:
|
|
case ARM::UXTAHrr_rot:
|
|
case ARM::VEXTd16:
|
|
case ARM::VEXTd32:
|
|
case ARM::VEXTd8:
|
|
case ARM::VEXTdf:
|
|
case ARM::VEXTq16:
|
|
case ARM::VEXTq32:
|
|
case ARM::VEXTq8:
|
|
case ARM::VEXTqf:
|
|
case ARM::t2MLA:
|
|
case ARM::t2MLS:
|
|
case ARM::t2PKHBT:
|
|
case ARM::t2PKHTB:
|
|
case ARM::t2SBFX:
|
|
case ARM::t2SMLABB:
|
|
case ARM::t2SMLABT:
|
|
case ARM::t2SMLAL:
|
|
case ARM::t2SMLATB:
|
|
case ARM::t2SMLATT:
|
|
case ARM::t2SMLAWB:
|
|
case ARM::t2SMLAWT:
|
|
case ARM::t2SMMLA:
|
|
case ARM::t2SMMLS:
|
|
case ARM::t2SMULL:
|
|
case ARM::t2SXTABrr_rot:
|
|
case ARM::t2SXTAHrr_rot:
|
|
case ARM::t2UBFX:
|
|
case ARM::t2UMAAL:
|
|
case ARM::t2UMLAL:
|
|
case ARM::t2UMULL:
|
|
case ARM::t2UXTABrr_rot:
|
|
case ARM::t2UXTAHrr_rot:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
switch (MI->getOpcode()) {
|
|
case ARM::MLS:
|
|
case ARM::SBFX:
|
|
case ARM::SMLABB:
|
|
case ARM::SMLABT:
|
|
case ARM::SMLATB:
|
|
case ARM::SMLATT:
|
|
case ARM::SMLAWB:
|
|
case ARM::SMLAWT:
|
|
case ARM::SMMLA:
|
|
case ARM::SMMLS:
|
|
case ARM::UBFX:
|
|
case ARM::UMAAL:
|
|
case ARM::VEXTd16:
|
|
case ARM::VEXTd32:
|
|
case ARM::VEXTd8:
|
|
case ARM::VEXTdf:
|
|
case ARM::VEXTq16:
|
|
case ARM::VEXTq32:
|
|
case ARM::VEXTq8:
|
|
case ARM::VEXTqf:
|
|
case ARM::t2MLA:
|
|
case ARM::t2MLS:
|
|
case ARM::t2SBFX:
|
|
case ARM::t2SMLABB:
|
|
case ARM::t2SMLABT:
|
|
case ARM::t2SMLAL:
|
|
case ARM::t2SMLATB:
|
|
case ARM::t2SMLATT:
|
|
case ARM::t2SMLAWB:
|
|
case ARM::t2SMLAWT:
|
|
case ARM::t2SMMLA:
|
|
case ARM::t2SMMLS:
|
|
case ARM::t2SMULL:
|
|
case ARM::t2UBFX:
|
|
case ARM::t2UMAAL:
|
|
case ARM::t2UMLAL:
|
|
case ARM::t2UMULL: O << ", "; break;
|
|
case ARM::PKHBT:
|
|
case ARM::t2PKHBT: O << ", LSL "; break;
|
|
case ARM::PKHTB:
|
|
case ARM::t2PKHTB: O << ", ASR "; break;
|
|
case ARM::SXTABrr_rot:
|
|
case ARM::SXTAHrr_rot:
|
|
case ARM::UXTABrr_rot:
|
|
case ARM::UXTAHrr_rot:
|
|
case ARM::t2SXTABrr_rot:
|
|
case ARM::t2SXTAHrr_rot:
|
|
case ARM::t2UXTABrr_rot:
|
|
case ARM::t2UXTAHrr_rot: O << ", ror "; break;
|
|
}
|
|
printOperand(MI, 3);
|
|
return;
|
|
break;
|
|
case ARM::MOVi32imm:
|
|
case ARM::t2MOVi32imm:
|
|
O << ", ";
|
|
printOperand(MI, 1, "lo16");
|
|
O << "\n\tmovt";
|
|
printPredicateOperand(MI, 2);
|
|
O << "\t";
|
|
printOperand(MI, 0);
|
|
O << ", ";
|
|
printOperand(MI, 1, "hi16");
|
|
return;
|
|
break;
|
|
case ARM::MOVsra_flag:
|
|
case ARM::MOVsrl_flag:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
switch (MI->getOpcode()) {
|
|
case ARM::MOVsra_flag: O << ", asr #1"; break;
|
|
case ARM::MOVsrl_flag: O << ", lsr #1"; break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::STRB_PRE:
|
|
case ARM::STRH_PRE:
|
|
case ARM::STR_PRE:
|
|
case ARM::t2STRB_PRE:
|
|
case ARM::t2STRH_PRE:
|
|
case ARM::t2STR_PRE:
|
|
O << ", [";
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::STRB_PRE:
|
|
case ARM::STR_PRE: printAddrMode2OffsetOperand(MI, 3); break;
|
|
case ARM::STRH_PRE: printAddrMode3OffsetOperand(MI, 3); break;
|
|
case ARM::t2STRB_PRE:
|
|
case ARM::t2STRH_PRE:
|
|
case ARM::t2STR_PRE: printT2AddrModeImm8OffsetOperand(MI, 3); break;
|
|
}
|
|
O << "]!";
|
|
return;
|
|
break;
|
|
case ARM::STREXD:
|
|
case ARM::t2STREXD:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << ", [";
|
|
printOperand(MI, 3);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::SXTBr_rot:
|
|
case ARM::SXTHr_rot:
|
|
case ARM::UXTB16r_rot:
|
|
case ARM::UXTBr_rot:
|
|
case ARM::UXTHr_rot:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << ", ror ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::VABDfd:
|
|
case ARM::VABDfq:
|
|
case ARM::VACGEd:
|
|
case ARM::VACGEq:
|
|
case ARM::VACGTd:
|
|
case ARM::VACGTq:
|
|
case ARM::VADDD:
|
|
case ARM::VADDS:
|
|
case ARM::VADDfd:
|
|
case ARM::VADDfd_sfp:
|
|
case ARM::VADDfq:
|
|
case ARM::VCEQfd:
|
|
case ARM::VCEQfq:
|
|
case ARM::VCGEfd:
|
|
case ARM::VCGEfq:
|
|
case ARM::VCGTfd:
|
|
case ARM::VCGTfq:
|
|
case ARM::VDIVD:
|
|
case ARM::VDIVS:
|
|
case ARM::VMAXfd:
|
|
case ARM::VMAXfq:
|
|
case ARM::VMINfd:
|
|
case ARM::VMINfq:
|
|
case ARM::VMULD:
|
|
case ARM::VMULS:
|
|
case ARM::VMULfd:
|
|
case ARM::VMULfd_sfp:
|
|
case ARM::VMULfq:
|
|
case ARM::VNMULD:
|
|
case ARM::VNMULS:
|
|
case ARM::VPADDf:
|
|
case ARM::VPMAXf:
|
|
case ARM::VPMINf:
|
|
case ARM::VRECPSfd:
|
|
case ARM::VRECPSfq:
|
|
case ARM::VRSQRTSfd:
|
|
case ARM::VRSQRTSfq:
|
|
case ARM::VSUBD:
|
|
case ARM::VSUBS:
|
|
case ARM::VSUBfd:
|
|
case ARM::VSUBfd_sfp:
|
|
case ARM::VSUBfq:
|
|
case ARM::t2ADCrr:
|
|
case ARM::t2ADCrs:
|
|
case ARM::t2ADDSri:
|
|
case ARM::t2ADDSrr:
|
|
case ARM::t2ADDSrs:
|
|
case ARM::t2ADDrSPi:
|
|
case ARM::t2ADDrSPs:
|
|
case ARM::t2ADDri:
|
|
case ARM::t2ADDrr:
|
|
case ARM::t2ADDrs:
|
|
case ARM::t2ANDrr:
|
|
case ARM::t2ANDrs:
|
|
case ARM::t2ASRri:
|
|
case ARM::t2ASRrr:
|
|
case ARM::t2BICrr:
|
|
case ARM::t2BICrs:
|
|
case ARM::t2EORrr:
|
|
case ARM::t2EORrs:
|
|
case ARM::t2LSLri:
|
|
case ARM::t2LSLrr:
|
|
case ARM::t2LSRri:
|
|
case ARM::t2LSRrr:
|
|
case ARM::t2ORRrr:
|
|
case ARM::t2ORRrs:
|
|
case ARM::t2RORri:
|
|
case ARM::t2RORrr:
|
|
case ARM::t2RSBri:
|
|
case ARM::t2SBCrr:
|
|
case ARM::t2SBCrs:
|
|
case ARM::t2SUBSri:
|
|
case ARM::t2SUBSrr:
|
|
case ARM::t2SUBSrs:
|
|
case ARM::t2SUBrSPi:
|
|
case ARM::t2SUBri:
|
|
case ARM::t2SUBrr:
|
|
case ARM::t2SUBrs:
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::VABDfd:
|
|
case ARM::VABDfq:
|
|
case ARM::VACGEd:
|
|
case ARM::VACGEq:
|
|
case ARM::VACGTd:
|
|
case ARM::VACGTq:
|
|
case ARM::VADDD:
|
|
case ARM::VADDS:
|
|
case ARM::VADDfd:
|
|
case ARM::VADDfd_sfp:
|
|
case ARM::VADDfq:
|
|
case ARM::VCEQfd:
|
|
case ARM::VCEQfq:
|
|
case ARM::VCGEfd:
|
|
case ARM::VCGEfq:
|
|
case ARM::VCGTfd:
|
|
case ARM::VCGTfq:
|
|
case ARM::VDIVD:
|
|
case ARM::VDIVS:
|
|
case ARM::VMAXfd:
|
|
case ARM::VMAXfq:
|
|
case ARM::VMINfd:
|
|
case ARM::VMINfq:
|
|
case ARM::VMULD:
|
|
case ARM::VMULS:
|
|
case ARM::VMULfd:
|
|
case ARM::VMULfd_sfp:
|
|
case ARM::VMULfq:
|
|
case ARM::VNMULD:
|
|
case ARM::VNMULS:
|
|
case ARM::VPADDf:
|
|
case ARM::VPMAXf:
|
|
case ARM::VPMINf:
|
|
case ARM::VRECPSfd:
|
|
case ARM::VRECPSfq:
|
|
case ARM::VRSQRTSfd:
|
|
case ARM::VRSQRTSfq:
|
|
case ARM::VSUBD:
|
|
case ARM::VSUBS:
|
|
case ARM::VSUBfd:
|
|
case ARM::VSUBfd_sfp:
|
|
case ARM::VSUBfq:
|
|
case ARM::t2ADCrr:
|
|
case ARM::t2ADDSri:
|
|
case ARM::t2ADDSrr:
|
|
case ARM::t2ADDrSPi:
|
|
case ARM::t2ADDri:
|
|
case ARM::t2ADDrr:
|
|
case ARM::t2ANDrr:
|
|
case ARM::t2ASRri:
|
|
case ARM::t2ASRrr:
|
|
case ARM::t2BICrr:
|
|
case ARM::t2EORrr:
|
|
case ARM::t2LSLri:
|
|
case ARM::t2LSLrr:
|
|
case ARM::t2LSRri:
|
|
case ARM::t2LSRrr:
|
|
case ARM::t2ORRrr:
|
|
case ARM::t2RORri:
|
|
case ARM::t2RORrr:
|
|
case ARM::t2RSBri:
|
|
case ARM::t2SBCrr:
|
|
case ARM::t2SUBSri:
|
|
case ARM::t2SUBSrr:
|
|
case ARM::t2SUBrSPi:
|
|
case ARM::t2SUBri:
|
|
case ARM::t2SUBrr: printOperand(MI, 2); break;
|
|
case ARM::t2ADCrs:
|
|
case ARM::t2ADDSrs:
|
|
case ARM::t2ADDrSPs:
|
|
case ARM::t2ADDrs:
|
|
case ARM::t2ANDrs:
|
|
case ARM::t2BICrs:
|
|
case ARM::t2EORrs:
|
|
case ARM::t2ORRrs:
|
|
case ARM::t2SBCrs:
|
|
case ARM::t2SUBSrs:
|
|
case ARM::t2SUBrs: printT2SOOperand(MI, 2); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::VDUPLN16d:
|
|
case ARM::VDUPLN16q:
|
|
case ARM::VDUPLN32d:
|
|
case ARM::VDUPLN32q:
|
|
case ARM::VDUPLN8d:
|
|
case ARM::VDUPLN8q:
|
|
case ARM::VDUPLNfd:
|
|
case ARM::VDUPLNfq:
|
|
case ARM::VGETLNi32:
|
|
O << ", ";
|
|
printOperand(MI, 1);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 2);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::VGETLNs16:
|
|
case ARM::VGETLNs8:
|
|
case ARM::VGETLNu16:
|
|
case ARM::VGETLNu8:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 2);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::VLD1d16:
|
|
case ARM::VLD1d32:
|
|
case ARM::VLD1d64:
|
|
case ARM::VLD1d8:
|
|
case ARM::VLD1df:
|
|
case ARM::VST1d16:
|
|
case ARM::VST1d32:
|
|
case ARM::VST1d64:
|
|
case ARM::VST1d8:
|
|
case ARM::VST1df:
|
|
case ARM::VST3q16a:
|
|
case ARM::VST3q16b:
|
|
case ARM::VST3q32a:
|
|
case ARM::VST3q32b:
|
|
case ARM::VST3q8a:
|
|
case ARM::VST3q8b:
|
|
O << "}, ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::VLD1d16:
|
|
case ARM::VLD1d32:
|
|
case ARM::VLD1d64:
|
|
case ARM::VLD1d8:
|
|
case ARM::VLD1df:
|
|
case ARM::VST3q16a:
|
|
case ARM::VST3q16b:
|
|
case ARM::VST3q32a:
|
|
case ARM::VST3q32b:
|
|
case ARM::VST3q8a:
|
|
case ARM::VST3q8b: printAddrMode6Operand(MI, 1); break;
|
|
case ARM::VST1d16:
|
|
case ARM::VST1d32:
|
|
case ARM::VST1d64:
|
|
case ARM::VST1d8:
|
|
case ARM::VST1df: printAddrMode6Operand(MI, 0); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::VLD2LNd16:
|
|
case ARM::VLD2LNd32:
|
|
case ARM::VLD2LNd8:
|
|
case ARM::VLD2LNq16a:
|
|
case ARM::VLD2LNq16b:
|
|
case ARM::VLD2LNq32a:
|
|
case ARM::VLD2LNq32b:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 8);
|
|
O << "],";
|
|
printOperand(MI, 1);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 8);
|
|
O << "]}, ";
|
|
printAddrMode6Operand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::VLD2d16:
|
|
case ARM::VLD2d32:
|
|
case ARM::VLD2d64:
|
|
case ARM::VLD2d8:
|
|
O << ',';
|
|
printOperand(MI, 1);
|
|
O << "}, ";
|
|
printAddrMode6Operand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::VLD2q16:
|
|
case ARM::VLD2q32:
|
|
case ARM::VLD2q8:
|
|
case ARM::VLD4d16:
|
|
case ARM::VLD4d32:
|
|
case ARM::VLD4d64:
|
|
case ARM::VLD4d8:
|
|
case ARM::VLD4q16a:
|
|
case ARM::VLD4q16b:
|
|
case ARM::VLD4q32a:
|
|
case ARM::VLD4q32b:
|
|
case ARM::VLD4q8a:
|
|
case ARM::VLD4q8b:
|
|
O << ',';
|
|
printOperand(MI, 1);
|
|
O << ',';
|
|
printOperand(MI, 2);
|
|
O << ',';
|
|
printOperand(MI, 3);
|
|
O << "}, ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::VLD2q16:
|
|
case ARM::VLD2q32:
|
|
case ARM::VLD2q8:
|
|
case ARM::VLD4d16:
|
|
case ARM::VLD4d32:
|
|
case ARM::VLD4d64:
|
|
case ARM::VLD4d8: printAddrMode6Operand(MI, 4); break;
|
|
case ARM::VLD4q16a:
|
|
case ARM::VLD4q16b:
|
|
case ARM::VLD4q32a:
|
|
case ARM::VLD4q32b:
|
|
case ARM::VLD4q8a:
|
|
case ARM::VLD4q8b: printAddrMode6Operand(MI, 5); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::VLD3LNd16:
|
|
case ARM::VLD3LNd32:
|
|
case ARM::VLD3LNd8:
|
|
case ARM::VLD3LNq16a:
|
|
case ARM::VLD3LNq16b:
|
|
case ARM::VLD3LNq32a:
|
|
case ARM::VLD3LNq32b:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 10);
|
|
O << "],";
|
|
printOperand(MI, 1);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 10);
|
|
O << "],";
|
|
printOperand(MI, 2);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 10);
|
|
O << "]}, ";
|
|
printAddrMode6Operand(MI, 3);
|
|
return;
|
|
break;
|
|
case ARM::VLD3d16:
|
|
case ARM::VLD3d32:
|
|
case ARM::VLD3d64:
|
|
case ARM::VLD3d8:
|
|
case ARM::VLD3q16a:
|
|
case ARM::VLD3q16b:
|
|
case ARM::VLD3q32a:
|
|
case ARM::VLD3q32b:
|
|
case ARM::VLD3q8a:
|
|
case ARM::VLD3q8b:
|
|
O << ',';
|
|
printOperand(MI, 1);
|
|
O << ',';
|
|
printOperand(MI, 2);
|
|
O << "}, ";
|
|
switch (MI->getOpcode()) {
|
|
case ARM::VLD3d16:
|
|
case ARM::VLD3d32:
|
|
case ARM::VLD3d64:
|
|
case ARM::VLD3d8: printAddrMode6Operand(MI, 3); break;
|
|
case ARM::VLD3q16a:
|
|
case ARM::VLD3q16b:
|
|
case ARM::VLD3q32a:
|
|
case ARM::VLD3q32b:
|
|
case ARM::VLD3q8a:
|
|
case ARM::VLD3q8b: printAddrMode6Operand(MI, 4); break;
|
|
}
|
|
return;
|
|
break;
|
|
case ARM::VLD4LNd16:
|
|
case ARM::VLD4LNd32:
|
|
case ARM::VLD4LNd8:
|
|
case ARM::VLD4LNq16a:
|
|
case ARM::VLD4LNq16b:
|
|
case ARM::VLD4LNq32a:
|
|
case ARM::VLD4LNq32b:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 12);
|
|
O << "],";
|
|
printOperand(MI, 1);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 12);
|
|
O << "],";
|
|
printOperand(MI, 2);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 12);
|
|
O << "],";
|
|
printOperand(MI, 3);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 12);
|
|
O << "]}, ";
|
|
printAddrMode6Operand(MI, 4);
|
|
return;
|
|
break;
|
|
case ARM::VMLAD:
|
|
case ARM::VMLAS:
|
|
case ARM::VMLAfd:
|
|
case ARM::VMLAfq:
|
|
case ARM::VMLSD:
|
|
case ARM::VMLSS:
|
|
case ARM::VMLSfd:
|
|
case ARM::VMLSfq:
|
|
case ARM::VNMLAD:
|
|
case ARM::VNMLAS:
|
|
case ARM::VNMLSD:
|
|
case ARM::VNMLSS:
|
|
case ARM::t2MOVCCasr:
|
|
case ARM::t2MOVCClsl:
|
|
case ARM::t2MOVCClsr:
|
|
case ARM::t2MOVCCror:
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
return;
|
|
break;
|
|
case ARM::VMLALslsv2i32:
|
|
case ARM::VMLALslsv4i16:
|
|
case ARM::VMLALsluv2i32:
|
|
case ARM::VMLALsluv4i16:
|
|
case ARM::VMLAslv2i32:
|
|
case ARM::VMLAslv4i16:
|
|
case ARM::VMLAslv4i32:
|
|
case ARM::VMLAslv8i16:
|
|
case ARM::VMLSLslsv2i32:
|
|
case ARM::VMLSLslsv4i16:
|
|
case ARM::VMLSLsluv2i32:
|
|
case ARM::VMLSLsluv4i16:
|
|
case ARM::VMLSslv2i32:
|
|
case ARM::VMLSslv4i16:
|
|
case ARM::VMLSslv4i32:
|
|
case ARM::VMLSslv8i16:
|
|
case ARM::VQDMLALslv2i32:
|
|
case ARM::VQDMLALslv4i16:
|
|
case ARM::VQDMLSLslv2i32:
|
|
case ARM::VQDMLSLslv4i16:
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 4);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::VMLAslfd:
|
|
case ARM::VMLAslfq:
|
|
case ARM::VMLSslfd:
|
|
case ARM::VMLSslfq:
|
|
printOperand(MI, 2);
|
|
O << ", ";
|
|
printOperand(MI, 3);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 4);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::VMULLslsv2i32:
|
|
case ARM::VMULLslsv4i16:
|
|
case ARM::VMULLsluv2i32:
|
|
case ARM::VMULLsluv4i16:
|
|
case ARM::VMULslv2i32:
|
|
case ARM::VMULslv4i16:
|
|
case ARM::VMULslv4i32:
|
|
case ARM::VMULslv8i16:
|
|
case ARM::VQDMULHslv2i32:
|
|
case ARM::VQDMULHslv4i16:
|
|
case ARM::VQDMULHslv4i32:
|
|
case ARM::VQDMULHslv8i16:
|
|
case ARM::VQDMULLslv2i32:
|
|
case ARM::VQDMULLslv4i16:
|
|
case ARM::VQRDMULHslv2i32:
|
|
case ARM::VQRDMULHslv4i16:
|
|
case ARM::VQRDMULHslv4i32:
|
|
case ARM::VQRDMULHslv8i16:
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 3);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::VMULslfd:
|
|
case ARM::VMULslfq:
|
|
printOperand(MI, 1);
|
|
O << ", ";
|
|
printOperand(MI, 2);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 3);
|
|
O << ']';
|
|
return;
|
|
break;
|
|
case ARM::VSETLNi16:
|
|
case ARM::VSETLNi32:
|
|
case ARM::VSETLNi8:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 3);
|
|
O << "], ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::VST2LNd16:
|
|
case ARM::VST2LNd32:
|
|
case ARM::VST2LNd8:
|
|
case ARM::VST2LNq16a:
|
|
case ARM::VST2LNq16b:
|
|
case ARM::VST2LNq32a:
|
|
case ARM::VST2LNq32b:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 6);
|
|
O << "],";
|
|
printOperand(MI, 5);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 6);
|
|
O << "]}, ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case ARM::VST2d16:
|
|
case ARM::VST2d32:
|
|
case ARM::VST2d64:
|
|
case ARM::VST2d8:
|
|
O << ',';
|
|
printOperand(MI, 5);
|
|
O << "}, ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case ARM::VST2q16:
|
|
case ARM::VST2q32:
|
|
case ARM::VST2q8:
|
|
case ARM::VST4d16:
|
|
case ARM::VST4d32:
|
|
case ARM::VST4d64:
|
|
case ARM::VST4d8:
|
|
O << ',';
|
|
printOperand(MI, 5);
|
|
O << ',';
|
|
printOperand(MI, 6);
|
|
O << ',';
|
|
printOperand(MI, 7);
|
|
O << "}, ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case ARM::VST3LNd16:
|
|
case ARM::VST3LNd32:
|
|
case ARM::VST3LNd8:
|
|
case ARM::VST3LNq16a:
|
|
case ARM::VST3LNq16b:
|
|
case ARM::VST3LNq32a:
|
|
case ARM::VST3LNq32b:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 7);
|
|
O << "],";
|
|
printOperand(MI, 5);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 7);
|
|
O << "],";
|
|
printOperand(MI, 6);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 7);
|
|
O << "]}, ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case ARM::VST3d16:
|
|
case ARM::VST3d32:
|
|
case ARM::VST3d64:
|
|
case ARM::VST3d8:
|
|
O << ',';
|
|
printOperand(MI, 5);
|
|
O << ',';
|
|
printOperand(MI, 6);
|
|
O << "}, ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case ARM::VST4LNd16:
|
|
case ARM::VST4LNd32:
|
|
case ARM::VST4LNd8:
|
|
case ARM::VST4LNq16a:
|
|
case ARM::VST4LNq16b:
|
|
case ARM::VST4LNq32a:
|
|
case ARM::VST4LNq32b:
|
|
O << '[';
|
|
printNoHashImmediate(MI, 8);
|
|
O << "],";
|
|
printOperand(MI, 5);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 8);
|
|
O << "],";
|
|
printOperand(MI, 6);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 8);
|
|
O << "],";
|
|
printOperand(MI, 7);
|
|
O << '[';
|
|
printNoHashImmediate(MI, 8);
|
|
O << "]}, ";
|
|
printAddrMode6Operand(MI, 0);
|
|
return;
|
|
break;
|
|
case ARM::VST4q16a:
|
|
case ARM::VST4q16b:
|
|
case ARM::VST4q32a:
|
|
case ARM::VST4q32b:
|
|
case ARM::VST4q8a:
|
|
case ARM::VST4q8b:
|
|
O << ',';
|
|
printOperand(MI, 8);
|
|
O << "}, ";
|
|
printAddrMode6Operand(MI, 1);
|
|
return;
|
|
break;
|
|
case ARM::VTBL1:
|
|
O << ", {";
|
|
printOperand(MI, 1);
|
|
O << "}, ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::VTBL2:
|
|
O << ", {";
|
|
printOperand(MI, 1);
|
|
O << ',';
|
|
printOperand(MI, 2);
|
|
O << "}, ";
|
|
printOperand(MI, 3);
|
|
return;
|
|
break;
|
|
case ARM::VTBL3:
|
|
O << ", {";
|
|
printOperand(MI, 1);
|
|
O << ',';
|
|
printOperand(MI, 2);
|
|
O << ',';
|
|
printOperand(MI, 3);
|
|
O << "}, ";
|
|
printOperand(MI, 4);
|
|
return;
|
|
break;
|
|
case ARM::VTBL4:
|
|
O << ", {";
|
|
printOperand(MI, 1);
|
|
O << ',';
|
|
printOperand(MI, 2);
|
|
O << ',';
|
|
printOperand(MI, 3);
|
|
O << ',';
|
|
printOperand(MI, 4);
|
|
O << "}, ";
|
|
printOperand(MI, 5);
|
|
return;
|
|
break;
|
|
case ARM::VTBX1:
|
|
O << ", {";
|
|
printOperand(MI, 2);
|
|
O << "}, ";
|
|
printOperand(MI, 3);
|
|
return;
|
|
break;
|
|
case ARM::VTBX2:
|
|
O << ", {";
|
|
printOperand(MI, 2);
|
|
O << ',';
|
|
printOperand(MI, 3);
|
|
O << "}, ";
|
|
printOperand(MI, 4);
|
|
return;
|
|
break;
|
|
case ARM::VTBX3:
|
|
O << ", {";
|
|
printOperand(MI, 2);
|
|
O << ',';
|
|
printOperand(MI, 3);
|
|
O << ',';
|
|
printOperand(MI, 4);
|
|
O << "}, ";
|
|
printOperand(MI, 5);
|
|
return;
|
|
break;
|
|
case ARM::VTBX4:
|
|
O << ", {";
|
|
printOperand(MI, 2);
|
|
O << ',';
|
|
printOperand(MI, 3);
|
|
O << ',';
|
|
printOperand(MI, 4);
|
|
O << ',';
|
|
printOperand(MI, 5);
|
|
O << "}, ";
|
|
printOperand(MI, 6);
|
|
return;
|
|
break;
|
|
case ARM::t2LDRpci_pic:
|
|
case ARM::tLDRpci_pic:
|
|
O << "\n";
|
|
printPCLabel(MI, 2);
|
|
O << ":\n\tadd\t";
|
|
printOperand(MI, 0);
|
|
O << ", pc";
|
|
return;
|
|
break;
|
|
case ARM::t2LEApcrelJT:
|
|
O << '_';
|
|
printNoHashImmediate(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::t2SXTBr_rot:
|
|
case ARM::t2SXTHr_rot:
|
|
case ARM::t2UXTB16r_rot:
|
|
case ARM::t2UXTBr_rot:
|
|
case ARM::t2UXTHr_rot:
|
|
printOperand(MI, 1);
|
|
O << ", ror ";
|
|
printOperand(MI, 2);
|
|
return;
|
|
break;
|
|
case ARM::tLEApcrel:
|
|
O << ", #";
|
|
printOperand(MI, 1);
|
|
return;
|
|
break;
|
|
case ARM::tLEApcrelJT:
|
|
O << ", #";
|
|
printOperand(MI, 1);
|
|
O << '_';
|
|
printNoHashImmediate(MI, 2);
|
|
return;
|
|
break;
|
|
}
|
|
return;
|
|
}
|
|
|
|
|
|
/// getRegisterName - This method is automatically generated by tblgen
|
|
/// from the register set description. This returns the assembler name
|
|
/// for the specified register.
|
|
const char *ARMAsmPrinter::getRegisterName(unsigned RegNo) {
|
|
assert(RegNo && RegNo < 100 && "Invalid register number!");
|
|
|
|
static const unsigned RegAsmOffset[] = {
|
|
0, 5, 8, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51,
|
|
54, 58, 62, 66, 70, 74, 78, 82, 86, 90, 94, 97, 101, 105,
|
|
108, 111, 114, 117, 120, 123, 129, 132, 135, 138, 141, 145, 149, 153,
|
|
157, 161, 165, 168, 171, 174, 177, 180, 183, 186, 189, 192, 195, 199,
|
|
203, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237, 241, 245,
|
|
249, 253, 257, 261, 265, 269, 273, 277, 280, 284, 288, 292, 296, 300,
|
|
304, 308, 312, 316, 320, 323, 327, 331, 334, 337, 340, 343, 346, 349,
|
|
358, 0
|
|
};
|
|
|
|
const char *AsmStrs =
|
|
"cpsr\000d0\000d1\000d10\000d11\000d12\000d13\000d14\000d15\000d16\000d1"
|
|
"7\000d18\000d19\000d2\000d20\000d21\000d22\000d23\000d24\000d25\000d26\000"
|
|
"d27\000d28\000d29\000d3\000d30\000d31\000d4\000d5\000d6\000d7\000d8\000"
|
|
"d9\000fpscr\000lr\000pc\000q0\000q1\000q10\000q11\000q12\000q13\000q14\000"
|
|
"q15\000q2\000q3\000q4\000q5\000q6\000q7\000q8\000q9\000r0\000r1\000r10\000"
|
|
"r11\000r12\000r2\000r3\000r4\000r5\000r6\000r7\000r8\000r9\000s0\000s1\000"
|
|
"s10\000s11\000s12\000s13\000s14\000s15\000s16\000s17\000s18\000s19\000s"
|
|
"2\000s20\000s21\000s22\000s23\000s24\000s25\000s26\000s27\000s28\000s29"
|
|
"\000s3\000s30\000s31\000s4\000s5\000s6\000s7\000s8\000s9\000sINVALID\000"
|
|
"sp\000";
|
|
return AsmStrs+RegAsmOffset[RegNo-1];
|
|
}
|
|
|