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616 lines
15 KiB
616 lines
15 KiB
/*-------------------------------------------------------------------------
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*
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* simd.h
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* Support for platform-specific vector operations.
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*
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* Portions Copyright (c) 1996-2025, PostgreSQL Global Development Group
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* Portions Copyright (c) 1994, Regents of the University of California
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*
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* src/include/port/simd.h
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*
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* NOTES
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* - VectorN in this file refers to a register where the element operands
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* are N bits wide. The vector width is platform-specific, so users that care
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* about that will need to inspect "sizeof(VectorN)".
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*
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*-------------------------------------------------------------------------
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*/
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#ifndef SIMD_H
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#define SIMD_H
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#if (defined(__x86_64__) || defined(_M_AMD64))
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/*
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* SSE2 instructions are part of the spec for the 64-bit x86 ISA. We assume
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* that compilers targeting this architecture understand SSE2 intrinsics.
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*
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* We use emmintrin.h rather than the comprehensive header immintrin.h in
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* order to exclude extensions beyond SSE2. This is because MSVC, at least,
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* will allow the use of intrinsics that haven't been enabled at compile
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* time.
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*/
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#include <emmintrin.h>
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#define USE_SSE2
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typedef __m128i Vector8;
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typedef __m128i Vector32;
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#elif defined(__aarch64__) && defined(__ARM_NEON)
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/*
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* We use the Neon instructions if the compiler provides access to them (as
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* indicated by __ARM_NEON) and we are on aarch64. While Neon support is
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* technically optional for aarch64, it appears that all available 64-bit
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* hardware does have it. Neon exists in some 32-bit hardware too, but we
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* could not realistically use it there without a run-time check, which seems
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* not worth the trouble for now.
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*/
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#include <arm_neon.h>
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#define USE_NEON
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typedef uint8x16_t Vector8;
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typedef uint32x4_t Vector32;
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#else
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/*
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* If no SIMD instructions are available, we can in some cases emulate vector
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* operations using bitwise operations on unsigned integers. Note that many
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* of the functions in this file presently do not have non-SIMD
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* implementations. In particular, none of the functions involving Vector32
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* are implemented without SIMD since it's likely not worthwhile to represent
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* two 32-bit integers using a uint64.
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*/
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#define USE_NO_SIMD
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typedef uint64 Vector8;
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#endif
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/* load/store operations */
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static inline void vector8_load(Vector8 *v, const uint8 *s);
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#ifndef USE_NO_SIMD
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static inline void vector32_load(Vector32 *v, const uint32 *s);
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#endif
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/* assignment operations */
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static inline Vector8 vector8_broadcast(const uint8 c);
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#ifndef USE_NO_SIMD
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static inline Vector32 vector32_broadcast(const uint32 c);
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#endif
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/* element-wise comparisons to a scalar */
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static inline bool vector8_has(const Vector8 v, const uint8 c);
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static inline bool vector8_has_zero(const Vector8 v);
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static inline bool vector8_has_le(const Vector8 v, const uint8 c);
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static inline bool vector8_is_highbit_set(const Vector8 v);
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#ifndef USE_NO_SIMD
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static inline bool vector32_is_highbit_set(const Vector32 v);
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static inline uint32 vector8_highbit_mask(const Vector8 v);
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#endif
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/* arithmetic operations */
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static inline Vector8 vector8_or(const Vector8 v1, const Vector8 v2);
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#ifndef USE_NO_SIMD
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static inline Vector32 vector32_or(const Vector32 v1, const Vector32 v2);
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#endif
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/*
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* comparisons between vectors
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*
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* Note: These return a vector rather than boolean, which is why we don't
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* have non-SIMD implementations.
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*/
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#ifndef USE_NO_SIMD
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static inline Vector8 vector8_eq(const Vector8 v1, const Vector8 v2);
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static inline Vector8 vector8_min(const Vector8 v1, const Vector8 v2);
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static inline Vector32 vector32_eq(const Vector32 v1, const Vector32 v2);
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#endif
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/*
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* Load a chunk of memory into the given vector.
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*/
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static inline void
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vector8_load(Vector8 *v, const uint8 *s)
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{
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#if defined(USE_SSE2)
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*v = _mm_loadu_si128((const __m128i *) s);
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#elif defined(USE_NEON)
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*v = vld1q_u8(s);
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#else
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memcpy(v, s, sizeof(Vector8));
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#endif
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}
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#ifndef USE_NO_SIMD
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static inline void
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vector32_load(Vector32 *v, const uint32 *s)
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{
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#ifdef USE_SSE2
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*v = _mm_loadu_si128((const __m128i *) s);
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#elif defined(USE_NEON)
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*v = vld1q_u32(s);
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Store a vector into the given memory address.
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*/
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#ifndef USE_NO_SIMD
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static inline void
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vector8_store(uint8 *s, Vector8 v)
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{
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#ifdef USE_SSE2
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_mm_storeu_si128((Vector8 *) s, v);
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#elif defined(USE_NEON)
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vst1q_u8(s, v);
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Create a vector with all elements set to the same value.
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*/
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static inline Vector8
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vector8_broadcast(const uint8 c)
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{
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#if defined(USE_SSE2)
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return _mm_set1_epi8(c);
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#elif defined(USE_NEON)
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return vdupq_n_u8(c);
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#else
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return ~UINT64CONST(0) / 0xFF * c;
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#endif
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}
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#ifndef USE_NO_SIMD
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static inline Vector32
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vector32_broadcast(const uint32 c)
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{
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#ifdef USE_SSE2
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return _mm_set1_epi32(c);
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#elif defined(USE_NEON)
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return vdupq_n_u32(c);
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Return true if any elements in the vector are equal to the given scalar.
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*/
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static inline bool
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vector8_has(const Vector8 v, const uint8 c)
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{
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bool result;
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/* pre-compute the result for assert checking */
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#ifdef USE_ASSERT_CHECKING
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bool assert_result = false;
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for (Size i = 0; i < sizeof(Vector8); i++)
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{
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if (((const uint8 *) &v)[i] == c)
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{
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assert_result = true;
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break;
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}
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}
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#endif /* USE_ASSERT_CHECKING */
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#if defined(USE_NO_SIMD)
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/* any bytes in v equal to c will evaluate to zero via XOR */
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result = vector8_has_zero(v ^ vector8_broadcast(c));
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#else
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result = vector8_is_highbit_set(vector8_eq(v, vector8_broadcast(c)));
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#endif
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Assert(assert_result == result);
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return result;
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}
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/*
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* Convenience function equivalent to vector8_has(v, 0)
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*/
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static inline bool
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vector8_has_zero(const Vector8 v)
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{
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#if defined(USE_NO_SIMD)
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/*
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* We cannot call vector8_has() here, because that would lead to a
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* circular definition.
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*/
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return vector8_has_le(v, 0);
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#else
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return vector8_has(v, 0);
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#endif
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}
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/*
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* Return true if any elements in the vector are less than or equal to the
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* given scalar.
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*/
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static inline bool
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vector8_has_le(const Vector8 v, const uint8 c)
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{
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bool result = false;
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#ifdef USE_SSE2
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Vector8 umin;
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Vector8 cmpe;
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#endif
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/* pre-compute the result for assert checking */
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#ifdef USE_ASSERT_CHECKING
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bool assert_result = false;
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for (Size i = 0; i < sizeof(Vector8); i++)
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{
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if (((const uint8 *) &v)[i] <= c)
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{
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assert_result = true;
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break;
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}
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}
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#endif /* USE_ASSERT_CHECKING */
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#if defined(USE_NO_SIMD)
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/*
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* To find bytes <= c, we can use bitwise operations to find bytes < c+1,
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* but it only works if c+1 <= 128 and if the highest bit in v is not set.
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* Adapted from
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* https://graphics.stanford.edu/~seander/bithacks.html#HasLessInWord
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*/
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if ((int64) v >= 0 && c < 0x80)
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result = (v - vector8_broadcast(c + 1)) & ~v & vector8_broadcast(0x80);
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else
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{
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/* one byte at a time */
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for (Size i = 0; i < sizeof(Vector8); i++)
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{
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if (((const uint8 *) &v)[i] <= c)
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{
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result = true;
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break;
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}
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}
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}
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#elif defined(USE_SSE2)
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umin = vector8_min(v, vector8_broadcast(c));
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cmpe = vector8_eq(umin, v);
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result = vector8_is_highbit_set(cmpe);
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#elif defined(USE_NEON)
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result = vminvq_u8(v) <= c;
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#endif
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Assert(assert_result == result);
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return result;
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}
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/*
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* Returns true if any elements in the vector are greater than or equal to the
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* given scalar.
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*/
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#ifndef USE_NO_SIMD
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static inline bool
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vector8_has_ge(const Vector8 v, const uint8 c)
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{
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#ifdef USE_SSE2
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Vector8 umax = _mm_max_epu8(v, vector8_broadcast(c));
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Vector8 cmpe = vector8_eq(umax, v);
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return vector8_is_highbit_set(cmpe);
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#elif defined(USE_NEON)
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return vmaxvq_u8(v) >= c;
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Return true if the high bit of any element is set
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*/
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static inline bool
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vector8_is_highbit_set(const Vector8 v)
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{
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#ifdef USE_SSE2
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return _mm_movemask_epi8(v) != 0;
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#elif defined(USE_NEON)
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return vmaxvq_u8(v) > 0x7F;
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#else
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return v & vector8_broadcast(0x80);
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#endif
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}
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/*
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* Exactly like vector8_is_highbit_set except for the input type, so it
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* looks at each byte separately.
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*
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* XXX x86 uses the same underlying type for 8-bit, 16-bit, and 32-bit
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* integer elements, but Arm does not, hence the need for a separate
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* function. We could instead adopt the behavior of Arm's vmaxvq_u32(), i.e.
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* check each 32-bit element, but that would require an additional mask
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* operation on x86.
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*/
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#ifndef USE_NO_SIMD
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static inline bool
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vector32_is_highbit_set(const Vector32 v)
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{
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#if defined(USE_NEON)
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return vector8_is_highbit_set((Vector8) v);
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#else
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return vector8_is_highbit_set(v);
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Return a bitmask formed from the high-bit of each element.
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*/
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#ifndef USE_NO_SIMD
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static inline uint32
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vector8_highbit_mask(const Vector8 v)
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{
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#ifdef USE_SSE2
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return (uint32) _mm_movemask_epi8(v);
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#elif defined(USE_NEON)
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/*
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* Note: It would be faster to use vget_lane_u64 and vshrn_n_u16, but that
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* returns a uint64, making it inconvenient to combine mask values from
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* multiple vectors.
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*/
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static const uint8 mask[16] = {
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1 << 0, 1 << 1, 1 << 2, 1 << 3,
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1 << 4, 1 << 5, 1 << 6, 1 << 7,
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1 << 0, 1 << 1, 1 << 2, 1 << 3,
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1 << 4, 1 << 5, 1 << 6, 1 << 7,
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};
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uint8x16_t masked = vandq_u8(vld1q_u8(mask), (uint8x16_t) vshrq_n_s8((int8x16_t) v, 7));
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uint8x16_t maskedhi = vextq_u8(masked, masked, 8);
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return (uint32) vaddvq_u16((uint16x8_t) vzip1q_u8(masked, maskedhi));
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Return the bitwise OR of the inputs
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*/
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static inline Vector8
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vector8_or(const Vector8 v1, const Vector8 v2)
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{
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#ifdef USE_SSE2
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return _mm_or_si128(v1, v2);
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#elif defined(USE_NEON)
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return vorrq_u8(v1, v2);
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#else
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return v1 | v2;
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#endif
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}
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#ifndef USE_NO_SIMD
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static inline Vector32
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vector32_or(const Vector32 v1, const Vector32 v2)
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{
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#ifdef USE_SSE2
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return _mm_or_si128(v1, v2);
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#elif defined(USE_NEON)
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return vorrq_u32(v1, v2);
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Return the bitwise AND of the inputs.
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*/
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#ifndef USE_NO_SIMD
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static inline Vector8
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vector8_and(const Vector8 v1, const Vector8 v2)
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{
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#ifdef USE_SSE2
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return _mm_and_si128(v1, v2);
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#elif defined(USE_NEON)
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return vandq_u8(v1, v2);
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Return the result of adding the respective elements of the input vectors.
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*/
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#ifndef USE_NO_SIMD
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static inline Vector8
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vector8_add(const Vector8 v1, const Vector8 v2)
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{
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#ifdef USE_SSE2
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return _mm_add_epi8(v1, v2);
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#elif defined(USE_NEON)
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return vaddq_u8(v1, v2);
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Return the result of subtracting the respective elements of the input
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* vectors using signed saturation (i.e., if the operation would yield a value
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* less than -128, -128 is returned instead). For more information on
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* saturation arithmetic, see
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* https://en.wikipedia.org/wiki/Saturation_arithmetic
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*/
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#ifndef USE_NO_SIMD
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static inline Vector8
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vector8_issub(const Vector8 v1, const Vector8 v2)
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{
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#ifdef USE_SSE2
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return _mm_subs_epi8(v1, v2);
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#elif defined(USE_NEON)
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return (Vector8) vqsubq_s8((int8x16_t) v1, (int8x16_t) v2);
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Return a vector with all bits set in each lane where the corresponding
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* lanes in the inputs are equal.
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*/
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#ifndef USE_NO_SIMD
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static inline Vector8
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vector8_eq(const Vector8 v1, const Vector8 v2)
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{
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#ifdef USE_SSE2
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return _mm_cmpeq_epi8(v1, v2);
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#elif defined(USE_NEON)
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return vceqq_u8(v1, v2);
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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#ifndef USE_NO_SIMD
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static inline Vector32
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vector32_eq(const Vector32 v1, const Vector32 v2)
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{
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#ifdef USE_SSE2
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return _mm_cmpeq_epi32(v1, v2);
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#elif defined(USE_NEON)
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return vceqq_u32(v1, v2);
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Return a vector with all bits set for each lane of v1 that is greater than
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* the corresponding lane of v2. NB: The comparison treats the elements as
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* signed.
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*/
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#ifndef USE_NO_SIMD
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static inline Vector8
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vector8_gt(const Vector8 v1, const Vector8 v2)
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{
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#ifdef USE_SSE2
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return _mm_cmpgt_epi8(v1, v2);
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#elif defined(USE_NEON)
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return vcgtq_s8((int8x16_t) v1, (int8x16_t) v2);
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Given two vectors, return a vector with the minimum element of each.
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*/
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#ifndef USE_NO_SIMD
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static inline Vector8
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vector8_min(const Vector8 v1, const Vector8 v2)
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{
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#ifdef USE_SSE2
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return _mm_min_epu8(v1, v2);
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#elif defined(USE_NEON)
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return vminq_u8(v1, v2);
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Interleave elements of low halves (e.g., for SSE2, bits 0-63) of given
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* vectors. Bytes 0, 2, 4, etc. use v1, and bytes 1, 3, 5, etc. use v2.
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*/
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#ifndef USE_NO_SIMD
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static inline Vector8
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vector8_interleave_low(const Vector8 v1, const Vector8 v2)
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{
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#ifdef USE_SSE2
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return _mm_unpacklo_epi8(v1, v2);
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#elif defined(USE_NEON)
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return vzip1q_u8(v1, v2);
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#endif
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}
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#endif /* ! USE_NO_SIMD */
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/*
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* Interleave elements of high halves (e.g., for SSE2, bits 64-127) of given
|
|
* vectors. Bytes 0, 2, 4, etc. use v1, and bytes 1, 3, 5, etc. use v2.
|
|
*/
|
|
#ifndef USE_NO_SIMD
|
|
static inline Vector8
|
|
vector8_interleave_high(const Vector8 v1, const Vector8 v2)
|
|
{
|
|
#ifdef USE_SSE2
|
|
return _mm_unpackhi_epi8(v1, v2);
|
|
#elif defined(USE_NEON)
|
|
return vzip2q_u8(v1, v2);
|
|
#endif
|
|
}
|
|
#endif /* ! USE_NO_SIMD */
|
|
|
|
/*
|
|
* Pack 16-bit elements in the given vectors into a single vector of 8-bit
|
|
* elements. The first half of the return vector (e.g., for SSE2, bits 0-63)
|
|
* uses v1, and the second half (e.g., for SSE2, bits 64-127) uses v2.
|
|
*
|
|
* NB: The upper 8-bits of each 16-bit element must be zeros, else this will
|
|
* produce different results on different architectures.
|
|
*/
|
|
#ifndef USE_NO_SIMD
|
|
static inline Vector8
|
|
vector8_pack_16(const Vector8 v1, const Vector8 v2)
|
|
{
|
|
Vector8 mask PG_USED_FOR_ASSERTS_ONLY;
|
|
|
|
mask = vector8_interleave_low(vector8_broadcast(0), vector8_broadcast(0xff));
|
|
Assert(!vector8_has_ge(vector8_and(v1, mask), 1));
|
|
Assert(!vector8_has_ge(vector8_and(v2, mask), 1));
|
|
#ifdef USE_SSE2
|
|
return _mm_packus_epi16(v1, v2);
|
|
#elif defined(USE_NEON)
|
|
return vuzp1q_u8(v1, v2);
|
|
#endif
|
|
}
|
|
#endif /* ! USE_NO_SIMD */
|
|
|
|
/*
|
|
* Unsigned shift left of each 32-bit element in the vector by "i" bits.
|
|
*
|
|
* XXX AArch64 requires an integer literal, so we have to list all expected
|
|
* values of "i" from all callers in a switch statement. If you add a new
|
|
* caller, be sure your expected values of "i" are handled.
|
|
*/
|
|
#ifndef USE_NO_SIMD
|
|
static inline Vector8
|
|
vector8_shift_left(const Vector8 v1, int i)
|
|
{
|
|
#ifdef USE_SSE2
|
|
return _mm_slli_epi32(v1, i);
|
|
#elif defined(USE_NEON)
|
|
switch (i)
|
|
{
|
|
case 4:
|
|
return (Vector8) vshlq_n_u32((Vector32) v1, 4);
|
|
default:
|
|
Assert(false);
|
|
return vector8_broadcast(0);
|
|
}
|
|
#endif
|
|
}
|
|
#endif /* ! USE_NO_SIMD */
|
|
|
|
/*
|
|
* Unsigned shift right of each 32-bit element in the vector by "i" bits.
|
|
*
|
|
* XXX AArch64 requires an integer literal, so we have to list all expected
|
|
* values of "i" from all callers in a switch statement. If you add a new
|
|
* caller, be sure your expected values of "i" are handled.
|
|
*/
|
|
#ifndef USE_NO_SIMD
|
|
static inline Vector8
|
|
vector8_shift_right(const Vector8 v1, int i)
|
|
{
|
|
#ifdef USE_SSE2
|
|
return _mm_srli_epi32(v1, i);
|
|
#elif defined(USE_NEON)
|
|
switch (i)
|
|
{
|
|
case 4:
|
|
return (Vector8) vshrq_n_u32((Vector32) v1, 4);
|
|
case 8:
|
|
return (Vector8) vshrq_n_u32((Vector32) v1, 8);
|
|
default:
|
|
Assert(false);
|
|
return vector8_broadcast(0);
|
|
}
|
|
#endif
|
|
}
|
|
#endif /* ! USE_NO_SIMD */
|
|
|
|
#endif /* SIMD_H */
|
|
|